IN N O VA T IO N a n d E X C E L L E N C E

ADS-CCD1202

12-Bit, 2MHz, Sampling A/D's

for CCD Imaging Applications

GENERAL DESCRIPTION

The functionally complete, easy-to-use ADS-CCD1202 is a
12-bit, 2MHz Sampling A/D Converter whose performance
and production testing have been optimized for use in CCD
applications. This device delivers the lowest noise (600µVrms)
and the best differential linearity error (±0.45LSB maximum) of
any commercially available 12-bit A/D in its speed class. It can
respond to full scale input steps (from empty to full well) with
less than a single count of error, and its input is immune to
overvoltages that may occur due to blooming.

Packaged in an industry-standard, 24-pin, ceramic DDIP, the
ADS-CCD1202 requires ±15V (or ±12V) and +5V supplies and
typically consumes 1.75 (1.45) Watts. The device is 100%
production tested for all critical performance parameters and is
fully specified over both the 0 to +70°C and 55 to +125°C
operating temperature ranges.

For those applications using correlated double sampling, the
ADS-CCD1202 can be supplied without its internal sample-
hold amplifier and achieve conversion rates up to 2.5MHz.

Figure 1. ADS-CCD1202 Functional Block Diagram

INPUT/OUTPUT CONNECTIONS

PIN

FUNCTION

PIN

FUNCTION

BIT 12 (LSB)

12V/15V SUPPLY

BIT 11

GROUND

BIT 10

+12V/+15V SUPPLY

BIT 9

+10V REFERENCE OUT

BIT 8

ANALOG INPUT

BIT7

GROUND

BIT 6

NO CONNECT

BIT 5

NO CONNECT

BIT 4

START CONVERT

BIT 3

EOC

BIT 2

GROUND

BIT 1 (MSB)

+5V SUPPLY

Unipolar input range (0 to +10V)

2MHz sampling rate

4096-to-1 dynamic range (72.2dB)

Low noise, 600µVrms (1/4 of an LSB)

Outstanding differential nonlinearity error (±0.45 LSB max.)

Small, 24-pin ceramic DDIP

Low power, 1.75 Watts

Operates from ±12V or ±15V supplies

Edge-triggered, no pipeline delay

Low cost

FEATURES

DATEL will also entertain discussions about including the CDS
circuit internal to the ADS-CCD1202. Contact us for details.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.)

Tel: (508) 339-3000 Fax: (508)339-6356

For immediate assistance: (800) 233-2765

FLASH

ADC

REF

DAC

DIGITAL

CORRECTION

LOGIC

12 BIT 1 (MSB)

11 BIT 2

10 BIT 3

9 BIT 4

8 BIT 5

7 BIT 6

6 BIT 7

5 BIT 8

4 BIT 9

3 BIT 10

2 BIT 11

1 BIT 12 (LSB)

TIMING AND

CONTROL LOGIC

ANALOG INPUT 20

START CONVERT 16

EOC 15

+5V SUPPLY

17, 18

NO CONNECT

+12V/+15V SUPPLY

14, 19, 23
GROUND

12V/15V SUPPLY

S/H

BUFFER

+10V REFERENCE 21

ADS-CCD1202

FUNCTIONAL SPECIFICATIONS

= +25°C, ±Vcc = ±15V (or ±12V), +V

= +5V, 1.2MHz sampling rate, and a minimum 1 minute warmup unless otherwise specified.)

+25°C

0 to +70°C

55 to +125° C

ANALOG INPUT

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNITS

Input Voltage Range

0 to +10

Volts

Input Resistance

0.99

1.01

0.99

1.01

0.99

1.01

Input Capacitance

DIGITAL INPUTS

Logic Levels

Logic "1"

Volts

Logic "0"

+0.8

Volts

Logic Loading "1"

+20

µA

Logic Loading "0"

µA

Start Convert Positive Pulse Width

200

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity (fin = 10kHz)

±0.5

±1

LSB

Differential Nonlinearity (fin = 10kHz)

+0.25

±0.45

±0.25

±0.45

±0.35

±0.75

LSB

Full Scale Absolute Accuracy

+0.1

±0.3

±0.2

±0.5

±0.3

±0.8

%FSR

Offset Error (Tech Note 2)

±0.15

±0.3

±0.2

±0.5

±1.2

%FSR

Gain Error (Tech Note 2)

±0.1

±0.4

±0.8

±0.5

±1.4

No Missing Codes (fin = 10kHz)

Bits

DYNAMIC PERFORMANCE

Peak Harmonics (0.5dB)

dc to 500kHz

500kHz to 1MHz

Total Harmonic Distortion (0.5dB)

dc to 500kHz

500kHz to 1MHz

Signal-to-Noise Ratio
(w/o distortion, 0.5dB)

dc to 500kHz

500kHz to 1MHz

Signal-to-Noise Ratio

(8 distortion, 0.5dB)
dc to 500kHz

500kHz to 1MHz

Two-tone Intermodulation Distortion

(fin = 200kHz, 500kHz
fs = 2MHz, 0.5dB)

Noise

600

µVrms

Input Bandwidth (3dB)

Small Signal (20dB input)

MHz

Large Signal(0.5dB input)

MHz

Feedthrough Rejection

(fin = 1MHz)

Slew Rate

±200

V/µs

Aperture Delay Time

±20

Aperture Uncertainty

ps rms

S/H Acquisition Time

( to ±0.01%FSR, 10V step)

150

190

230

150

190

230

150

190

230

Overvoltage Recovery Time

400

500

400

500

400

500

A/D Conversion Rate

MHz

ABSOLUTE MAXIMUM RATINGS

PARAMETERS

LIMITS

UNITS

+12V/+15V Supply (Pin 22)

0 to +16

Volts

12V/15V Supply (Pin 24)

0 to 16

Volts

+5V Supply (Pin 13)

0 to +6

Volts

Digital Input (Pin 16)

0.3 to +V

+0.3

Volts

Analog Input (Pin 20)

5 to +14

Volts

Lead Temp. (10 seconds)

+300

°C

PHYSICAL/ENVIRONMENTAL

PARAMETERS

MIN.

TYP.

MAX.

UNITS

Operating Temp. Range, Case

ADS-CCD1202MC

+70

°C

ADS-CCD1202MM

+125

°C

Thermal Impedance

°C/Watt

Storage Temperature Range

+150

°C

Package Type

24-pin, metal-sealed ceramic DDIP

Weight

0.42 ounces (12 grams)

ADS-CCD1202

Footnotes:

All power supplies must be on before applying a start convert pulse. All
supplies and the clock (START CONVERT) must be present during warmup
periods. The device must be continuously converting during this time.

Contact DATEL for availability of other input voltage ranges.

A 200ns wide start convert pulse is used for all production testing.

Effective bits is equal to:

This is the time required before the A/D output data is valid after
the analog input is back within the specified range.

+25°C

0 to +70°C

55 to +125°C

ANALOG OUTPUT

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNITS

Internal Reference

Voltage

+9.95

+10.0

+10.05

+9.95

+10.0

+10.05

+9.95

+10.0

+10.05

Volts

Drift

±5

ppm/ºC

External Current

1.5

DIGITAL OUTPUTS

Logic Levels

Logic "1"

+2.4

Volts

Logic "0"

+0.4

Volts

Logic Loading "1"

Logic Loading "0"

Delay, Falling Edge of EOC

to Output Data Valid

Output Coding

Straight Binary

POWER REQUIREMENTS, ±15V

Power Supply Range

+15V Supply

+14.5

+15.0

+15.5

+14.5

+15.0

+15.5

+14.5

+15.0

+15.5

Volts

15V Supply

14.5

15.0

15.5

14.5

15.0

15.5

14.5

15.0

15.5

Volts

+5V Supply

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

Volts

Power Supply Current

+15V Supply

+43

+55

+43

+55

+43

+55

15V Supply

+5V Supply

+82

+95

+82

+95

+82

+95

Power Dissipation

1.75

1.95

1.75

1.95

1.75

1.95

Watts

Power Supply Rejection

±0.01

%FSR/%V

POWER REQUIREMENTS, ±12V

Power Supply Range

+12V Supply

+11.5

+12.0

+12.5

+11.5

+12.0

+12.5

+11.5

+12.0

+12.5

Volts

12V Supply

11.5

12.0

12.5

11.5

12.0

12.5

11.5

12.0

12.5

Volts

+5V Supply

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

+4.75

+5.0

+5.25

Volts

Power Supply Current

+12V Supply

+43

+55

+43

+55

+43

+55

12V Supply

+5V Supply

+82

+95

+82

+95

+82

+95

Power Dissipation

1.45

1.65

1.45

1.65

1.45

1.65

Watts

Power Supply Rejection

±0.01

%FSR/%V

(SNR + Distortion) 1.76 + 20 log

Full Scale Amplitude

Actual Input Amplitude

6.02

TECHNICAL NOTES

1. Obtaining fully specified performance from the ADS-CCD1202

requires careful attention to pc-card layout and power supply
decoupling. The device's analog and digital ground systems are
connected to each other internally. For optimal performance, tie
all ground pins (14, 19, and 23) directly to a large analog
ground plane beneath the package.

Bypass all power supplies, as well as the REFERENCE

OUTPUT (pin 21), to ground with 4.7µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. Locate the bypass
capacitors as close to the unit as possible. If the user-installed
offset and gain adjusting circuit shown in Figure 2 is used, also
locate it as close to the ADS-CCD1202 as possible.

2. ADS-CCD1202 achieves its specified accuracies without

external calibration. If required, the device's small initial offset
and gain errors can be reduced to zero using the input circuit of
Figure 2. When using this circuit, or any similar offset and gain-
calibration hardware, make adjustments following warmup. To
avoid interaction, always adjust offset before gain.

3. When operating the ADS-CCD1202 from ±12V supplies, do not

drive external circuitry with the REFERENCE OUTPUT (pin 21).
The reference's accuracy and drift specifications may not be
met, and loading the circuit may cause accuracy errors within
the converter.

4. A passive bandpass filter is used at the input of the A/D for all

production testing.

5. Applying a start pulse while a conversion is in progress (EOC =

logic "1") initiates a new and inaccurate conversion cycle. Data
for the interrupted and subsequent conversions will be invalid.

Input Voltage

Zero Adjust

Gain Adjust

Range

+1/2 LSB

+FS 1 1/2 LSB

0 to +10V

+1.2207mV

+9.99634V

Table 1. Zero and Gain Adjust

ADS-CCD1202

CALIBRATION PROCEDURE
(Refer to Figures 2 and 3)

Any offset and/or gain calibration procedures should not be
implemented until devices are fully warmed up. To avoid
interaction, offset must be adjusted before gain. The ranges of
adjustment for the circuit of Figure 2 are guaranteed to
compensate for the ADS-CCD1202's initial accuracy errors and
may not be able to compensate for additional system errors.

Figure 2. ADS-CCD1202 Calibration Circuit

All fixed resistors in Figure 2 should be metal-film types, and
multi-turn potentiometers should have TCR's of 100ppm/°C or
less to minimize drift with temperature. In many applications,
the CCD will require an offset-adjust (black balance) circuit
near its output and also a gain stage, presumably with adjust
capabilities, to match the output voltage of the CCD to the
input range of the AID. If one is performing a "system I/O
calibration" (from light in to digital out), these circuits can be
used to compensate for the relatively small initial offset and
gain errors of the A/D. This would eliminate the need for the
circuit shown in Figure 2.

Figure 3. Typical ADS-CCD1202 Connection Diagram

A/D converters are calibrated by positioning their digital
outputs exactly on the transition point between two adjacent
digital output codes. This can be accomplished by connecting
LED's to the digital outputs and adjusting until certain LED's
"flicker" equally between on and off. Other approaches employ
digital comparators or microcontrollers to detect when the
outputs change from one code to the next.

For the ADS-CCD1202, offset adjusting is normally
accomplished at the point where all output bits are 0's and the
LSB just changes from a 0 to a 1. This digital output transition
ideally occurs when the applied analog input is +1/2LSB
(+1.2207mV).

Gain adjusting is accomplished when all bits are 1's and the
LSB just changes from a 1 to a 0. This transition ideally occurs
when the analog input is at +full scale minus 1 1/2 LSB's
(+9.99634V).

Offset Adjust Procedure

1. Apply a train of pulses to the START CONVERT input (pin

16) so the converter is continuously converting. If using
LED's on the outputs, a 200kHz conversion rate will reduce
flicker.

2. Apply +1.2207mV to the ANALOG INPUT (pin 20).

3. Adjust the offset potentiometer until the output bits are

0000 0000 00000 and the LSB flickers between 0 and 1.

Gain Adjust Procedure

1. Apply +9.99634V to the ANALOG INPUT (pin 20).

2. Adjust the gain potentiometer until all output bits are 1's and

the LSB flickers between 1 and 0.

Table 2. ADS-CCD1202 Output Coding

Input Voltage

Unipolar

Digital Output

(0 to +10V)

Scale

MSB LSB

+9.9976

+FS 1LSB

1111 1111 1111

+7.5000

+3/4 FS

1100 0000 0000

+5.0000

+1/2 FS

1000 0000 0000

+2.5000

+1/4 FS

0100 0000 0000

+0.0024

+1LSB

0000 0000 0001

0000 0000 0000

All DATEL sampling A/D converters are fully characterized and
specified over operating temperature (case) ranges of 0 to
+70°C and 55 to +125°C. All room-temperature (T

= +25°C)

production testing is performed without the use of heat sinks or
forced-air cooling. Thermal impedance figures for each device
are listed in their respective specification tables.

These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should
be used to ensure devices do not overheat. The ground and
power planes beneath the package, as well as all pcb signal
runs to and from the device, should be as heavy as possible to
help conduct heat away from the package. Electrically
insulating, thermally-conductive "pads" may be installed
underneath the package. Devices should be soldered to boards
rather than "socketed," and of course, minimal air flow over the
surface can greatly help reduce the package temperature.

In more severe ambient conditions, the package/junction
temperature of a given device can be reduced dramatically
(typically 35%) by using one of DATEL's HS Series heat sinks.
See Ordering Information for the assigned part number. See
page 1-183 of the DATEL Data Acquisition Components
Catalog for more information on the HS Series. Request DATEL
Application Note AN-8, "Heat Sinks for DIP Data Converters,"or
contact DATEL directly, for additional information.

THERMAL REQUIREMENTS

ADS-CCD1202

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12 (LSB)

EOC

ANALOG
INPUT

19, 23

0.1µF

4.7µF

+5V

0.1µF

4.7µF

0.1µF

4.7µF

12V/15V

+12V/+15V

0.1µF

4.7µF

21 +10V REF. OUT

0 to +10V

NO CONNECT

17, 18

To Pin 20 of
ADS-CCD1202

15V

SIGNAL

INPUT

GAIN

ADJUST

1.98k

+15V

200k

20k

15V

+15V

ZERO/

OFFSET

ADJUST

ADS-CCD1202

TIMING

The ADSCCD-1202 is an edge triggered device. A conversion
is initiated by the rising edge of the start convert pulse and no
additional external timing signals are required. The device does

not employ "pipeline" delays to increase its throughput rate. It
does not require multiple start convert pulses to bring valid
digital data to its output pins.

Figure 5.

ADS-CCD1202 Evaluation Board Schematic

200K

0.1%

1.98K

OP-77

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

2A4

2A3

2A2

2A1

1A4

1A3

1A2

1A1

74LS240

.1%

0.1%

10K

74LS86

0.1MF

C17

0.1MF

C16

0.1MF

C15

15pF

0.1MF

C10

0.1MF

C12

0.1MF

C13

2.2MF

C4 +

2.2MF

C11

2.2MF

C14

+5V

+15V

-15V

+5V

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

20K

74LS86

B14

B13

B12

B11

B10

EOC

+5V

DGND

ST. CONV

AGND

INPUT

+10VREF

+15V

AGND

-15V

SG1

AD845

0.1%

10K

0.1%

-15V

2.2

C22

0.1MF

C23

+15V

2.2MF

C19 +

0.1MF

C20

XTAL

0.1MF

C21

+5V

0.1MF

C18

SG2

SG3

2.2MF

C24

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

2A4

2A3

2A2

2A1

1A4

1A3

1A2

1A1

74LS240

B13

B11

B12

B10

B14

SEE NOTE 1

ST.CONV.

ENABLE

MSB

LSB

EOC

COG

ADJ

GAIN

ADJ

OFFSET

CONVERT

START

INPUT

ANALOG

1. FOR ADS-BCCD1201 Y1 IS 1.2MHZ

FOR ADS-BCCD1201 Y1 IS 2MHZ

NOTES:

ADS-CCD1201/1202

Figure 4. ADS-CCD1202 Timing Diagram

START

CONVERT

OUTPUT DATA

INTERNAL S/H

DATA (N-1) VALID

200ns typ.

Acquisition Time

10ns typ.

DATA N VALID

425ns min.

Note: Scale is approximately 25ns per division.

EOC

30ns typ.

Conversion Time

360ns ±20ns

INVALID

DATA

75ns max.

70ns ±10ns

310ns typ.

35ns max.

Hold

N+1

190ns typ.

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