32 Megabit FLASH EEPROM

DP5Z2MX16Pn3

PRELIMINARY

DESCRIPTION:

The DP5Z2MX16Pn3 `'SLCC'' devices are a revolutionary new memory

subsystem using Dense-Pac Microsystems' ceramic Stackable Leadless Chip

Carriers (SLCC). Available unleaded, straight leaded, `'J'' leaded, gullwing

leaded packages, or mounted on a 50-pin PGA co-fired ceramic substrate.

The Device packs 32-Megabits of FLASH EEPROM in an area as small as 0.463

, while maintaining a total height as low as 0.131 inches.

The DP5Z2MX16Pn3 is a 2 Meg x 8 FLASH EEPROM memory module. Each

SLCC is hermetically sealed making the module suitable for commercial,

industrial and military applications.
By using SLCCs, the `'Stack'' family of modules offer a higher board density

of memory than available with conventional through-hole, surface mount or

hybrid techniques.

FEATURES:

Organization: 2 Meg x 16

Fast Access Times: 120, 150, 200ns (max.)

Single 5.0 Volt

High-Density Symmetrically Blocked Architecture

- Sixteen 128 Kbyte Blocks Per Device

Extended Cycling Capability

- 100K Write/Erase Cycles

Automated Erase and Program Cycles

- Command User Interface

- Status Register

SRAM-Compatible Write Interface

Hardware Data Protection Feature

- Erase / Write Lockout during

Power Transitions

Packages Available:

DP5Z2MX16PY

48 - Pin SLCC

DP5Z2MX16PI3

48 - Pin Straight Leaded SLCC

DP5Z2MX16PH3

48 - Pin Gullwing Leaded SLCC

DP5Z2MX16PJ3

48 - Pin `'J'' Leaded SLCC

DP5Z2MX16PA3

50 - Pin PGA Dense-SLCC

DP5Z2MX16PJ3

DP5Z2MX16PI3

DP5Z2MX16PY

DP5Z2MX16PH3

DP5Z2MX16PA3

2Mx16, 120 - 200ns, STACK/PGA

30A161-02

This document contains information on a product under consideration for

development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right

hange or discontinue information on this product without prior notice.

30A161-02

REV. A

Dense-Pac Microsystems, Inc.

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

PRELIMINARY

BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard

microprocessor bus cycles.

Table 1: Bus Operation

Mode

I/O0-I/O7

UB/LB

Read

1, 4

OUT

Output Disable

HIGH-Z

Standby

HIGH-Z

Deep Power-Down

HIGH-Z

Manufacturer Identifier

1, 3

C2H

Device Identifier

F1H

Write

1, 2

NOTES:
1. X can be V

or V

for address or control pins.

2. Command for defferent Erase operations, Data program operations or Selector Protect operations can only be successfully completed through proper

command sequence.

3. V

= 11.5V - 12.5V.

4. UB/LB = V

, I/O0-I/O7(I/O8-I/O15) = Lower Bank Data In/Out. UB/LB = V

, I/O0-I/O7(I/O8-I/O15) = Uper Bank Data In/Out.

WRITE OPERATION

Commands are written to the COMMAND INTERFACE REGISTER

(CIR) using standard microprocessor write timing. The CIR serves

as the interface between the microprocessor and the internal chip

operation. The CIR can decipher Read Array, Read Silicon ID,

Erase and Program command. In the event of a read command,

the CIR simply points the read path at either the array or the Silicon

ID, depending on the specific read command given. for a program

or erase cycle, the CIR informs the write state machine that a

program or erase has been requested. During a program cycle,

the write state machine control the program sequences and the

CIR will only respond to status reads. During a sector/chip erase

cycle, the CIR will respond to status reads and erase suspend. After

the writhe state machine has completed its task, it will allow the

CIR to respond to its full command set. The CIR stays at read status

command sequence.
Device operations are selected by writing commands into the CIR.

Table 3 defines 16 Megabit Flash family command.

PIN NAMES

A0 - A19

ADDRESS INPUTS: for memory address. Addresses are internally latched during a write cycle.

I/O0 - I/O7

DATA INPUT/OUTPUT: Input data and command during Command Data Interface Register (CIR) write

cycles. Outputs array, status and identifier data in the appropriate read mode. Floated when the chip is

de-selected or the outputs are disabled.

UB/LB

UPER BANK/LOWER BANK: Used to select upper/lower 1 megabyte memory array banks during reads or

the upper/lower 64 byte banks during 128 byte page writes. This control pin should be used as the LSB

address during reads, but not used in page sector addressing during programming.

CHIP ENABLE INPUT: Activate the device's control logic, Input buffers, decoders and sense amplifiers. With

CE high, the device is de-selected and power consumption reduces to Standby level upon completion of any

current program or erase operation. CE must be low to select the device. Device selection occurs with the

falling edge of CE. The rising edge of CE disables the device.

WRITE ENABLE: Controls writes to the Command Interface Register (CIR). WE is active low.

OUTPUT ENABLE: Gates the device's data through the output buffers during a read cycle. OE is active low.

DEVICE POWER SUPPLY (+5.0 Volts

10%)

GROUND

N.C.

No Connect

30A161-02

REV. A

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

Dense-Pac Microsystems, Inc.

PRELIMINARY

DEVICE OPERATION

SILICON ID READ

The Silicon ID Read mode allows the reading out of a binary code

from the device and will identify its manufacturer and type. this is

intended for use by programming equipment for the purpose of

automatically matching the device to be programmed with its

corresponding programming algorithm. This mode is functional

over the entire temperature range of the device.
To activate the mode, the programming equipment must force V

(11.5V ~ 12.5V) on address pin A9. Two identifier bytes may then

be sequenced from the device outputs by toggling address A0 from

to V

. All addresses are don't cares except A0 and A1.

The manufacturer and device codes may also be read via the

command register, for instance when the device is erased or

programmed in a system without access to high voltage on the A9

pin. The command sequence is illustrated in Table 2.

To terminate the operation, it is necessary to write the read/reset
command sequence into the CIR.

READ RESET COMMAND

The read or reset operation is initiated by writing the read/reset
command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The device
remains enabled fro reads until the CIR contents are altered by a
valid command sequence.
The device will automatically power-up in the read/reset state. In
this case, a command sequence is not required to read data. This
default value ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.

Table 2: Command Definition

Command

Sequence

Bus

Cycles

Req'd

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Address Data Address Data Address Data

Address

Data

Address Data Address Data

Read/Reset

5555H AAH 2AAAH 55H 5555H F0H

Silicon ID Read

5555H AAH 2AAAH 55H 5555H 90H 00H/01H C2H/F1H

Page/Byte Program

5555H AAH 2AAAH 55H 5555H A0H

Chip Erase

5555H AAH 2AAAH 55H 5555H 80H

5555H

AAH

2AAAH 55H 5555H 10H

Sector Erase

5555H AAH 2AAAH 55H 5555H 80H

5555H

AAH

2AAAH 55H

30H

Erase Suspend

5555H AAH 2AAAH 55H 5555H B0H

Erase Resume

5555H AAH 2AAAH 55H 5555H D0H

Read Status Register

5555H AAH 2AAAH 55H 5555H 70H

SRD

Clear Status Register

5555H AAH 2AAAH 55H 5555H 50H

Sleep

5555H AAH 2AAAH 55H 5555H C0H

Abort

5555H AAH 2AAAH 55H 5555H E0H

NOTES:
1. Address bit A15 - A19, UL/UB = X = Don't Care for all address commands except for Programming Address (PA) and Sector Address (SA).

5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.

2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.

PA = Address of the memory to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A16 - A19 will be uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

SRD = Data read from Status Register.

Table 3: Silicon ID Code

Type

A19

A18

A17

A16

Code

(HEX)

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

Manufacturer's

Code

C2H

Device Code

FIH

30A161-02

REV. A

Dense-Pac Microsystems, Inc.

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

PRELIMINARY

PAGE PROGRAM

To initiate Page Program mode, a three-cycle command sequence

is required. There are two "unlock" write cycles. These are

followed by writing the page program command - A0H.
After three-cycle command sequence is given, a byte load is

performed by applying a low pulse on the WE or CE input with CE

or WE low (respectively) and OE high. The address is latched on

the falling edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Maximum of 128 bytes

of data may be loaded into each page by the same procedures as

outlined in the page program section below.

BYTE LOAD

Byte loads are used to enter the 128 bytes of a page to be

programmed. A byte load is performed by applying a low pulse

on the WE or CE input CE or WE low respectively) and OE high.

The address is latched on the falling edge of CE or WE, whichever

occurs last. The data is latched by the first rising edge of CE or WE.
The UB/LB control pin is used to select the upper 64 byte bank or

the lower 64 byte bank for each 128 byte page to write the entire

128 byte page, the UB/LB control pin must be used as the LSB

address pin to select both halves of the internal memory array.

PROGRAM

Any page to be programmed should have the page in the erase

state first, i.e. performing sector erase is suggested before page

programming can be performed.
The device is programmed on a page basis. If a byte of data within

a page is to be changed, data for the entire page can be loaded

into the device. Any byte that is not loaded during the

programming of its page will be still in the erase state (i.e. FFH).

Once the bytes of a page are loaded into the device, they are

simultaneously programmed during the internal programming

period. After the first data byte has been loaded into the device,

successive bytes are entered in the same manner. Each new byte

to be programmed must have its high to low transition on WE (or

CE) within 30

s of the low to high transition of WE (or CE) of the

preceding byte. A6 to A19 specify the page address, i.e. the device

is page-aligned on 128 bytes boundary The page address must be

valid during each high to low transition of WE or CE. UB/LB and

A0 to A5 specify the byte address within the page. The byte (word)

may be loaded in any order; sequential loading is not required. If

a high to low transition of CE or WE is not detected within 100

of the last low to high transition, the load period will end and the

internal programming period will start. The auto page program

terminates when status on I/O7(I/O15) is "1" at which time the

device stays at read status register mode until the CIR contents are

altered by a valid command sequence. (Refer to Table 2 & 5 and

Figure 1, 6 & 7)

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two "unlock"

write cycles. These are followed by writing the "set-up" command

- 80H. Two more "unlock" write cycles are then followed by the

chip erase command - 10H.
Chip erase does not require the user to program the device prior

to erase.
The automatic erase begins on the rising edge of the last WE pulse

in the command sequence and terminates when the status on

I/O7(I/O15) is "1" at which time the device stays at read status

command sequence. (Refer to Tables 2 & 5 and Figures 2, 6 & 8)

Table 4: Sector Address *

(using UB/LB as LSB)

A19

A18

A17

A16

Address Range

[A0-A15, UB/LB ]

SA0

000000H--01FFFFH

SA1

020000H--03FFFFH

SA2

040000H--05FFFFH

SA3

060000H--07FFFFH

SA4

080000H--09FFFFH

...

....

...

................

SA15

1E0000H--1FFFFFH

* Per 2 Meg x 8 device.

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two "unlock"

write cycles. These are followed by writing the set-up command

- 80H. Two more "unlock" write cycles are then followed by the

sector erase command - 30H. The sector address is latched on the

falling edge of WE, while the command (data) is latched on the

rising edge of WE.
Sector erase does not require the user to program the device prior

to erase. The system is not required to provide any controls or

timings during these operations.
The automatic sector erase begins on the rising edge of the last WE

pulse in the command sequence and terminates when the status

on I/O7(I/O15) is "1" at which time the device stays at read status

mode until the CIR contents are altered by a valid command

sequence. (Refer to Tables 2, & 5 and Figures 3, 4, 6 & 8)

ERASE SUSPEND

This command only has meaning while the WSM is executing

SECTOR or CHIP erase operations, and therefore will only be

responded to during SECTOR or CHIP erase operation. After this

command has been executed, the CIR will initiate the WSM to

suspend erase operations, and then return to Read Status Register

mode. The WSM will set the I/O6(I/O14) bit to a "1". Once the

WSM has reached the Suspend state, the WSM will set I/O7(I/O15)

bit to a "1". At this time, WSM allows CIR to respond to the Read

Array, Read Status Register, Abort and Erase Resume commands

only. In this mode, the CIR will not respond to any other

commands. the WSM will continue to run, idling in the SUSPEND

state, regardless of the state of all input control pins.

ERASE RESUME

This command will cause the CIR to clear the suspend state and

set the I/O6(I/O14) to a "0", but only in an Erase Suspend command

was previously used. Erase Resume will not have any effect in all

other conditions.

READ STATUS REGISTER COMMAND

The module contains a Status Register which may be read to

determine when a program or erase operation is complete, and

whether that operation completed successfully. The status register

may be read at any time by writing the Read Status command to

the CIR. After writing this command, all subsequent read

operations output data from the status register, until another valid

command is written to the CIR. A Read Array command must be

written to the CIR to return to the Read Array mode.

30A161-02

REV. A

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

Dense-Pac Microsystems, Inc.

PRELIMINARY

The status register bits are output on I/O2 - I/O7(I/O10-I/O15)

(Table 5), I/O0-I/O1(I/O8-I/O9) is set to 0H.
It should be noted that the status register are latched on the falling

edge of OE or CE whichever occurs last in the read cycle. This

prevents possible bus errors which might occur if the contents of

the status register change while reading the status register. CE or

OE must be toggled with each subsequent status read, or the

completion of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor

and the Write State Machine (WSM). When the WSM is active,

this register will indicate the status of the WSM, and will also hold

the bits indicating whether or not the WSM was successful in

performing the desired operation. The WSM sets status bits four

through seven and clears bits six and seven, but cannot clear status

bits four and five. If Erase fail or Program fail status bit is detected,

the Status Register is not cleared until the Clear Status Register

command is written. The device automatically outputs Status

Program or Read Status Command write cycle. The default state

of the Status Register after power-up is I/O7-I/O4(I/O15-I/O12) =

1000B. I/O3(I/O11) = 0 or 1 depends on sector-protect status,

can not be changed by Clear Status Register Command or Write

State Machine. I/O2(I/O10) = 0 or 1 depends on Sleep status,

During Sleep mode or Abort mode I/O2(I/O10) is set to "1";

I/O2(I/O10) is reset to "0" by Read Array command.

CLEAR STATUS REGISTER

The Erase fail status bit (I/O5 and I/O13) and Program fail status bit

(I/O4 and I/O12) are set by the write state machine, and can only

be reset by the system software. These bits can indicate various

failure conditions (see Table 5). By allowing the system software

to control the resetting of these bits, several operations may be

performed (such as cumulatively programming several pages or

erasing multiple blocks in sequence). The Status register may then

be read to determine if an error occurred during that programming

or erasing series. This adds flexibility to the way the device may

be programmed or erased. Additionally, once the program (erase)

fail bit happens

the program (erase) operation can not be

performed further. The program (erase) fail bit must be reset by

system software before further page program or sector (chip) erase

are attempted. To clear the status register, the Clear Status Register

command is written to the CIR. Then, any other command may

be issued to the CIR. Note again that before a read cycle can be

initiated, a Read command must be written to the CIR to specify

whether the read data is to come from the Array, Status Register or

Silicon ID.

SLEEP MODE

The device features two software controlled low-power modes:

Sleep and Abort modes. Sleep mode is allowable during any

current operations except that once Suspend command is issued,

Sleep command is ignored. Abort mode is executed only during

page Programming and Chip/Sector Erase mode.
To activate Sleep mode, a three-bus cycle operation is required.

C0H command (refer to Table 2) puts the device in the Sleep mode.

Once in the Sleep mode and CMOS input level applied, the power

of the device is reduced to deep power-down current levels. The

only threshold condition, input leakage, and output leakage.
The Sleep command allows the device to COMPLETE current

operations before going into Sleep mode. Once current operation

is done, device stays at read status register mode. The status

registers are not reset during sleep command. Program or Erase

Table 5: Status Register

STATUS

I/O7(I/O15) I/O6(I/O14) I/O5(I/O13) I/O4(I/O12) I/O3(I/O11) I/O2(I/O10)

PROGRESS

PROGRAM

1, 2, 6

0/1

ERASE

1, 3, 6

0/1

SUSPEND (NOT COMPLETE)

1, 4, 6

0/1

SUSPEND (COMPLETE)

1, 4, 6

0/1

COMPLETE

PROGRAM

1, 2, 6

0/1

ERASE

1, 3, 6

0/1

FAIL

PROGRAM

1, 5, 6

0/1

ERASE

1, 5, 6

0/1

AFTER CLEARING STATUS REGISTER

0/1

Note 7

NOTES:
1. I/O7(I/O15): Write State Machine Status

1 = Ready, 0 = Busy

I/O6(I/O14): Erase Suspend Status

1 = Suspend, 0 = No Suspend

I/O5(I/O13): Erase Fail Status

1 = Fail in Erase, 0 = Successful Erase

I/O4(I/O12): Program Fail Status

1 = Fail in Program, 0 = Successful Program

I/O3(I/O11): Sector-Protect Status (Not Used)

I/O2(I/O10): Sleep Status

1 = Device in Sleep Status, 0 = Device Not in Sleep Status

I/O0-I/O1(I/O8-I/O9) = Reserved for further enhancements.

These bits are reserved for future use; mask them out when polling

the Status Register.

2. Program Status is for the status during Page Programming or Sector

Unprotect mode.

3. Erase Status is for the status during Sector/Chip Erase or Sector

Protection mode.

4. Suspend Status is for both Sector and Chip Erase mode.
5. Fail Status bit (I/O4-I/O5 and I/O12-I/O13) is provided during Page

Program or Sector/Chip Erase modes respectively.

6. I/O2(I/O10) = 0 or 1 depends on whether device is in the Sleep

mode or not.

7. Once in the Sleep mode, I/O2(I/O10) is set to "1", and is reset by

read array command only.

30A161-02

REV. A

Dense-Pac Microsystems, Inc.

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

PRELIMINARY

fail bit may have been set if during program/erase mode the device

retry exceeds maximum count.
During Sleep mode, the status registers, Silicon ID codes remain

valid and can still be read. The device Sleep Status bit-I/O2(I/O10)

will indicate that the device in the sleep mode.
Write and Read Array command wakes up the device out of Sleep

mode, I/O2(I/O10) is reset to "0" and device returns to standby

current level.

ABORT MODE

To activate Abort mode, a three-bus cycle operation is required.

The E0H command (refer to Table 3) only stops page program or

Sector/Chip erase operations currently in progress and puts the

device in Sleep mode. But unlike the Sleep command, the

program or erase operation will not be completed. Since the data

in some page/sectors is no longer valid due to an incomplete

program or erase operation, the program fail I/O4(I/O12) or erase

fail I/O5(I/O13) bit will be set.
After the abort command is executed and with CMOS input levels

applied, the device current is reduced to the same level as in deep

power-down or sleep modes. Device stays at read register mode.
During Abort mode, the status register, Silicon ID codes remain

valid and can still be read. The device Sleep Status bit - I/O2(I/O10)

will indicate that the device in the sleep mode.

DATA PROTECTION

The device is designed to offer protection against accidental

erasure or programming caused by spurious system level signals

that may exit during power transitions. During power-up the

device automatically resets the internal state machine in the read

array mode. Also, with its control register architecture, alterations

of the memory contents only occurs after successful completion of

specific multi-bus cycles command sequences.
the device also incorporates several features to prevent inadvertent

write cycles resulting from V

power-up and power-down

transitions or system noise.

LOW V

WRITE INHIBIT

To avoid initiation of a write cycle during V

power-up and

power-down, a write cycle is locked out for V

less than V

LKO

(=3.2V, typically 3.5V). If V

< V

LKO

, the command register is

disabled and all internal program/erase circuits are disabled.

Under this condition the device will reset to the read mode.

Subsequent writes will be ignored until the V

level is greater

than V

LKO

. It is logically correct to prevent unintentional write

when V

is above V

LKO

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 10ns (typical) on CE or WE will not initiate

a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = V

, CE = V

WE = V

. To initiate a write cycle CE and WE must be a logical

zero while OE is a logical one.

ERASE AND PROGRAMMING PERFORMANCE

PARAMETER

LIMITS

UNITS

MIN.

TYP.

MAX.

Chip/Sector Erase Time

150

2000

Page Programming Time

Chip Program Time *

150

sec

Erase/Program Cycles

10,000

Cycles

Byte Program Time

Per 1Mx16 device.

LATCH UP CHARACTERISTICS

PARAMETER

MIN.

AMX.

UNITS

Input Voltage with Respect to V

on all pins except I/O pins

-1.0

13.5

Input Voltage with Respect to V

on all I/O pins

-1.0

+1.0

Current

-100

+100

Includes all pins except V

. Test conditions: V

= 5.0V, one pin at a time

30A161-02

REV. A

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

Dense-Pac Microsystems, Inc.

PRELIMINARY

RECOMMENDED OPERATING RANGE

Symbol

Characteristic

Min. Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

Input LOW Voltage

-0.5

0.8

Input HIGH Voltage

2.0

+0.5 V

Operating

Temperature

+25

+70

-40 +25

+85

M/B

-55 +25

+125

A9 I.D. Input/Output

11.5

12.5

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

STC

Storage Temperature

-65 to +125

BIAS

Temperature Under Bias

-55 to +125

Operating Temperature

-55 to +125

OUT

Output Short

Circuit Current

100

I/O

Input/Output Voltage

-0.5 to +7.0

Supply Voltage

-0.5 to +7.0

DC OPERATING CHARACTERISTICS: Over operating ranges

Symbol

Characteristics

Test Conditions

Limits

Unit

Min.

Typ.

Max.

Input Load Current

= V

max., V

or V

Output Leakage

Current

= V

max., V

or V

SB1

Standby Current

(CMOS)

= V

max., CE = V

0.2V

100

400

SB2

Standby Current

(TTL)

= V

max., CE = V

CC1

Read Current

= V

max., CE = V

Inputs = V

or V

, f = 10MHz, I

OUT

= 0mA

100

160

CC2

Read Current

= V

max., CE = V

Inputs = V

or V

, f = 5MHz, I

OUT

= 0mA

CC3

Erase

Suspend Current

6, 8

Block Erase in Suspend, CE = V

CC4

Program Current

Program in Progress

120

CC5

Erase Current

Erase in Progress

120

Input Low Voltage

-3.0

0.8

Input High Voltage

2.4

+0.3

Output Low Voltage

= 2.1mA

0.45

Output High Voltage

= -400mA

2.4

CAPACITANCE

: T

= 25

C, F = 1.0MHz

Symbol

Parameter

Max.

Unit Condition

ADR

Address Input

= 0V

Chip Enable

Write Enable

Output Enable

I/O

Data Input/Output

DC OUTPUT CHARACTERISTICS

Symbol

Parameter

Condition

Min. Max. Unit

HIGH

Voltage

= -400

2.4

LOW Voltage I

=2.1mA

0.45

30A161-02

REV. A

Dense-Pac Microsystems, Inc.

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

PRELIMINARY

OUTPUT LOAD

Load

Parameters Measured

100 pF

except t

, t

and t

OLZ

30pF

, t

and t

OLZ

AC TEST CONDITIONS

Input Pulse Levels

0.45V to 2.4V

Input Pulse Rise and Fall Times

10ns

Input and Output

Timing Reference Levels

0.8V, 2.0V

AC Operating Conditions and Characteristics - Read Cycle:

Over operating ranges

No. Symbol

Parameter

120ns

150ns

200ns

Unit

Min.

Max.

Min.

Max.

Min.

Max.

ACC

Address to Output Delay

120

150

Chip Enable Output Delay

120

150

Output Enable Output Delay

Output Enable to Output Delay

Address to Output Hold

AC INPUT OUTPUT REFERENCE WAVEFORM

AC test inputs are driven at V

(2.4 V

TTL

) for Logic "1'' and V

(0.45 V

TTL

) for a Logic `'0''. Input timing begins at V

(2.0 V

TTL

)

and V

(0.8 V

TTL

). Output timing ends at V

and V

. Input rise and fall times (10% to ()%) < 10ns.

OUTPUT LOAD

+5V

1.8K

DIODES = IN3064 or Equivalent

6.2K

* Including Probe and Jig Capacitance.

DEVICE

UNDER

TEST

30A161-02

REV. A

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

Dense-Pac Microsystems, Inc.

PRELIMINARY

Figure 5: READ CYCLE

ADDRESS

DATA I/O

AC Operating Conditions and Characteristics - Write/Erase/Program Cycle:

Over operating ranges

No. Symbol

Parameter

120ns

150ns

200ns

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Write Cycle Time

120

150

200

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

OES

Output Enable Setup Time

CES

Chip Enable Setup Time

GHWL

Read Recovery Time before Write

Chip Enable Setup Time

Chip Enable Hold Hold Time

Write Pulse Width

WPH

Write Pulse Width HIGH

BALC

Byte Address Load Time

0.3

BAL

Byte Address Load Time

100

SRA

Status Register Access Time

120

150

200

CESR

Chip Enable Setup before SR Read

100

VCS

Setup Time

30A161-02

REV. A

DP5Z2MX16PY/PI3/PH3/PJ3/DP5Z2MX8PA3

Dense-Pac Microsystems, Inc.

PRELIMINARY

NOTES:

All voltages are with respect to V

2. -2.0V min. for pulse width less than 20ns (V

min. = -0.5V at DC level).

3. Maximum DC voltage on V

or A9 may over shoot to +14.0V for periods less than 20ns.

4. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

5. This parameter is guaranteed and not 100% tested.
6. All currents are in RMS unless otherwise noted. Typical values at V

= 5.0V, t = 25

C. These currents are valid for all product

versions (package and speeds.).

7. I

CC3

is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of I

CC3

and I

CC1

CC2

8. V

min. = -1.0V for pulse width

50ns.

9. V

min. = -2.0V for pulse width

20ns.

10. Refer to page 5 for detail Page Program Operation.

WAVEFORM KEY

Data Valid

Transition from

Data Undefined

HIGH to LOW

LOW to HIGH

or Don't Care

30A161-02

REV. A

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DP5Z2MX16PH3

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DP5Z2MX16PH3