30A232-12
REV. A 3/03
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
256 Megabit Synchronous DRAM
DPSD16MX16TKY5
1
ADVAN C E D C O M P O N E NTS PAC K AG I N G
PIN NAMES
A0-A11
Row Address:
A0-A11
Column Address:
A0-A9
BA0, BA1
Bank Select Address
DQ0-DQ15
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Strobe
WE
Data Write Enable
DQM0, DQM1
Data Input/Output Masks
CKE
Clock Enable
CLK
System Clock
CS
Chip Select
V
CC
/V
SS
Power Supply/Ground
V
CCQ
/V
SSQ
Data Output Power/Ground
DESCRIPTION:
The Memory StackTM series is a family of interchangeable memory devices. The 256 Megabit SDRAM assembly utilizes the
space saving LP-StackTM technology to increase memory density. This stack is constructed with two 128Mb (16M x 8)
SDRAMs.
This 256Mb LP-StackTM has been designed to fit in the
same footprint as the 128Mb (16M x 8) SDRAM TSOPII
monolithic. This stack allows for system upgrade without
electrical or mechanical redesign, providing an alternative
low cost memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers' datasheets
Memory organization:
(2) 128Mb memory devices. Each device arranged
as 16M x 8 bits (4M x 8 bits x 4 banks)
Memory stack organization:
16M x 16 bits (4M x 16 bits x 4 banks)
JEDEC approved, 1 Rank stack pinout and footprint
(with 1 CS, 1 CKE, 2 DQMs and DQ0-DQ15)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII stack
PIN-OUT DIAGRAM
54
53
51
52
VSS
DQ7
VSSQ
DQ15
1
1
2
3
4
TOP VIEW
47
46
49
48
41
42
40
44
43
45
VCCQ
DQ14
DQ5
DQ12
VSS
DQM1
DQ13
DQ4
VCCQ
VSSQ
37
36
35
38
31
30
29
33
32
34
A8
CLK
CKE
NC
A11
A9
A6
A5
A4
A7
DQM0
39
8
9
6
7
11
13
14
15
12
10
18
19
20
17
22
24
25
26
23
21
16
50
DQ6
5
VCCQ
DQ8
VCC
DQ0
VCCQ
DQ2
VSSQ
DQ9
DQ11
VCC
N.C.
DQ3
VSSQ
DQ10
RAS
CS
BA0
CAS
A1
A2
A3
A10
A0
BA1
WE
DQ1
VSS
28
27
VCC
FUNCTIONAL BLOCK DIAGRAM
DQM1
CAS
WE
DQ0-DQ7
DQM0
RAS
CK
CLK
A0-A11
CKE
CS
BA0-BA1
(4M x 8 bits x 4 banks)
128 Mb SDRAM
(4M x 8 bits x 4 banks)
30A232-12
REV. A 8/01
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2003 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, LP-StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.
DPSD16MX16TKY5
256 Megabit Synchronous DRAM
MECHANICAL DIAGRAM
.020 [.51]
.0315 [.80]
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
PIN 1
INDEX
.502.008
.891 MAX.
[12.75.20]
[22.63 MAX.]
.102 MAX. [.259 MAX]
Lead Toe-to-Toe per device datasheet
Inch [mm]
END VIEW DETAIL
.463 [11.76] TYP
COPLANARITY:
.004 [.10] from seating plane
TYP.
TYP.
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers' specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215C.
ORDERING INFORMATION
DP
-
PREFIX
SD 16M
X
16
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
TK
STACKABLE TSOP
SYNCHRONOUS DRAM
SUPPLIER
- DP
SUPPLIER CODE
128 MEGABIT (X8) LVTTL BASED
MFR ID
XX
REVISION
MEMORY
X
BLANK
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
n
70P2
75P2
75
55
60
70
TIME
XXX
CYCLE
10
08
12
P12
P13
7.5ns (133MHz) CL3
5.5ns (183MHz) CL3
7ns (143MHz) CL3
6ns (166MHz) CL2
7ns (133MHz) CL2
7.5ns (133MHz) CL2
PC100 / CL2
12ns (83MHz)
8ns (125MHz)
10ns (100MHz)
PC100 / CL3
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