DESCRIPTION:
The Memory StackTM series is a family of interchangeable memory devices. The 1 Gb SDRAM assembly utilizes the space
saving LP-StackTM technology to increase memory density. This stack is constructed with two 512Mb (32M x 16) SDRAMs.
This 1 Gb LP-StackTM has been designed to fit in the same footprint as the 512Mb (32M x 16) SDRAM TSOPII monolithic.
This stack allows for system upgrade without electrical or
mechanical redesign, providing an alternative low cost
memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers' datasheets
Memory organization:
(2) 512Mb memory devices. Each device arranged
as 32M x 16 bits (8M x 16 bits x 4 banks)
Memory stack organization:
64M x 16 bits (16M x 16 bits x 4 banks)
JEDEC approved, 2 Rank stack pinout and footprint
(with 2 CS, 1 CKE)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII stack
PIN NAMES
A0-A12
Row Address:
A0-A12
Column Address:
A0-A9
BA0, BA1
Bank Select Address
DQ0-DQ15
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Strobe
WE
Data Write Enable
UDQM,
LDQM
Upper & Lower
Data Input/Output Mask
CKE
Clock Enable
CLK
System Clock
CS0, CS1
Chip Selects
V
CC/
V
SS
Power Supply/Ground
V
CCQ/
V
SSQ
Data Output Power/Ground
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
1 Gigabit Synchronous DRAM
DPSD64MX16XY5
1
ADVAN C E D C O M P O N E NTS PAC K AG I N G
30A231-10
REV. C 3/03
PIN-OUT DIAGRAM
TOP VIEW
33 A8
VCC
1
2
54 VSS
VCCQ
3
53
DQ1 4
52 VSSQ
DQ2
5
51 DQ14
VSSQ
6
50 DQ13
DQ3
7
49 VCCQ
8
48 DQ12
VCCQ
9
47
DQ5 10
46 VSSQ
DQ6 11
45 DQ10
VSSQ 12
44 DQ9
DQ7 13
43 VCCQ
VCC 14
42 DQ8
LDQM 15
41 VSS
WE 16
40 CS1
CAS 17
39 UDQM
RAS 18
38 CLK
CS0 19
37 CKE
BA0 20
36 A12
BA1 21
35 A11
A10 22
34 A9
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VCC 27
28 VSS
DQ4
DQ0
DQ11
DQ15
1
FUNCTIONAL BLOCK DIAGRAM
A0-A12
CAS
WE
512 Mb SDRAM
DQ0-DQ15
CS0
(8M x 16 bits x 4 banks)
RAS
CKE
CLK
UDQM
CS1
LDQM
BA0-BA1
(8M x 16 bits x 4 banks)
30A231-10
REV. C 3/03
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2003 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, LP-StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.
DPSD64MX16XY5
1 Gigabit Synchronous DRAM
MECHANICAL DIAGRAM
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
.934.010
.870.003*
.945 MAX.*
PIN 1
.030 MIN.
[23.72.25]
[22.35.08]*
[22.62.08]*
[.76 MIN.]
.020 [.51]
.0315 [.80]
.0805 [2.04]
* Measurments are from edge of PCB.
Inch[mm]
END VIEW
.502.008
[12.75.20]
Lead Toe-to-Toe per device datasheet
END VIEW DETAIL
.463 [11.76] TYP
COPLANARITY:
.004 [.10] from seating plane
[2.45 MAX.]
.098 MAX.
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers' specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215C.
ORDERING INFORMATION
DP
-
PREFIX
SD 64M
X
16
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
X
STACKABLE TSOP
SYNCHRONOUS DRAM
SUPPLIER
- DP
SUPPLIER CODE *
512 MEGABIT LVTTL BASED
MFR ID
XX
REVISION
MEMORY
X
BLANK
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
n
70P2
75P2
75
55
60
70
TIME
XXX
CYCLE
10
08
12
P12
P13
7.5ns (133MHz) CL3
5.5ns (183MHz) CL3
7ns (143MHz) CL3
6ns (166MHz) CL2
7ns (133MHz) CL2
7.5ns (133MHz) CL2
PC100 / CL2
12ns (83MHz)
8ns (125MHz)
10ns (100MHz)
PC100 / CL3
PDF 
ZIP