EL4584C

February

1995

Rev

EL4584C

Horizontal Genlock 4 F

Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation

4584C

1994 Elantec Inc

Features

36 MHz general purpose PLL
4 F

based timing (use the

EL4585 for 8 F

)

Compatible w EL4583 Sync

Separator

VCXO Xtal or LC tank

oscillator

2 ns jitter (VCXO)

User controlled PLL capture and

lock

Compatible with NTSC and PAL

TV formats

8 pre-programmed TV scan rate

clock divisors

Selectable external divide for

custom ratios

Single 5V low current operation

Applications

Pixel Clock regeneration
Video compression engine

(MPEG) clock generator

Video capture or digitization
PIP (Picture in Picture) timing

generator

Text or graphics overlay timing

Ordering Information

Part No

Temp Range Package Outline

EL4584CN -40 C to a85 C 16-Pin DIP MDP0031

EL4584CS -40 C to a85 C 16-Lead SO MDP0027

For 6Fsc and 8Fsc clock frequencies

see

EL4585 datasheet

Demo Board

A demo PCB is available for this
product Request ``EL4584 5 Demo
Board''

General Description

The EL4584C is a PLL (Phase Lock Loop) sub system designed
for video applications but also suitable for general purpose use
up to 36 MHz In a video application this device generates a
TTL CMOS compatible Pixel Clock (Clk Out) which is a multi-
ple of the TV Horizontal scan rate and phase locked to it

The reference signal is a horizontal sync signal TTL CMOS
format which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator An input signal
to ``coast'' is provided for applications were periodic distur-
bances are present in the reference video timing such as VTR
head switching The Lock detector output indicates correct lock

The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards by external selection of
three control pins These four ratios have been selected for com-
mon video applications including 4 F

3 F

13 5 MHz

(CCIR 601 format) and square picture elements used in some
workstation graphics To generate 8 F

6 F

27 MHz (CCIR

601 format) etc use the EL4585 which includes an additional
divide by 2 stage

For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
bypassed and an external divider chain used

FREQUENCIES and DIVISORS

Function

3Fsc

CCIR 601

Square

4Fsc

Divisor

851

864

944

1135

PAL Fosc (MHz)

13 301

13 5

14 75

17 734

Divisor

682

858

780

910

NTSC Fosc (MHz)

10 738

13 5

12 273

14 318

CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL

Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion

3Fsc numbers do not yield integer divisors

Connection Diagram

EL4584 SO P-DIP Packages

4584 17

EL4584C

Horizontal Genlock 4 F

Absolute Maximum Ratings

25 C)

Supply

Operating Junction Temp

125 C

Storage Temperature

65 C to

150 C

Power Dissipation

400 mW

Lead Temperature

260 C

Oscillator Frequency

36 MHz

Pin Voltages

0 5V to V

0 5V

Operating Ambient Temperature

Range

40 C to

85 C

Important Note
All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually
performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test
equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore T

Test Level

Test Procedure

100% production tested and QA sample tested per QA test plan QCX0002

100% production tested at T

25 C and QA sample tested at T

25 C

MAX

and T

MIN

per QA test plan QCX0002

III

QA sample tested per QA test plan QCX0002

Parameter is guaranteed (but not tested) by Design and Characterization Data

Parameter is typical value at T

25 C for information purposes only

DC Electrical Characteristics

5V T

25 C unless otherwise noted)

Parameter

Conditions

Temp

Min

Typ

Max

Test

Units

Level

5V (Note 1)

25 C

Input Low Voltage

25 C

1 5

Input High Voltage

25 C

3 5

Input Low Current

All inputs except COAST V

1 5V

25 C

100

Input High Current

All inputs except COAST V

3 5V

25 C

100

Input Low Current

COAST pin V

1 5V

25 C

100

Input High Current

COAST pin V

3 5V

25 C

100

Output Low Voltage

Lock Det I

1 6mA

25 C

0 4

Output High Voltage

Lock Det I

e b

1 6mA

25 C

2 4

Output Low Voltage

CLK I

3 2mA

25 C

0 4

Output High Voltage

CLK I

e b

3 2mA

25 C

2 4

Output Low Voltage

OSC Out I

200

25 C

0 4

Output High Voltage

OSC Out I

e b

200

25 C

2 4

Output Low Current

Filter Out V

OUT

2 5V

25 C

200

300

Output High Current

Filter Out V

OUT

2 5V

25 C

300

200

Current Ratio

Filter Out V

OUT

2 5V

25 C

1 05

1 0

0 95

LEAK

Filter Out

Coast Mode V

OUT

25 C

100

Note 1 All inputs to 0V COAST floating

35in

EL4584C

Horizontal Genlock 4 F

AC Electrical Characteristics

5V T

25 C unless otherwise noted)

Parameter

Conditions

Temp

Min

Typ

Max

Test

Units

Level

VCO Gain

20 MHz

Test Circuit 1

25 C

15 5

H-sync S N Ratio

5V (Note 2)

25 C

Jitter

VCXO Oscillator

25 C

Jitter

LC Oscillator (Typ)

25 C

Note 2 Noisy video signal input to EL4583C H-sync input to EL4584C Test for positive signal lock

Pin Description

Pin No

Pin Name

Function

16 1 2

Prog A B C

Digital inputs to select

N value for internal counter See table below for values

Osc VCO Out

Output of internal inverter oscillator Connect to external crystal or LC tank VCO circuit

(A)

Analog positive supply for oscillator PLL circuits

Osc VCO In

Input from external VCO

(A)

Analog ground for oscillator PLL circuits

Charge Pump Out Connect to loop filter If the H-sync phase is leading or H-sync frequency

CLK

N current is pumped

into the filter capacitor to increase VCO frequency If H-sync phase is lagging or frequency

CLK

current is pumped out of the filter capacitor to decrease VCO frequency During coast mode or when
locked charge pump goes to a high impedance state

Div Select

Divide select input When high the internal divider is enabled and EXT DIV becomes a test pin
outputting CLK

N When low the internal divider is disabled and EXT DIV is an input from an

external

Coast

Tri-state logic input Low(

)

normal mode Hi Z(or

)

fast lock mode

High(

)

coast mode

H-sync In

Horizontal sync pulse (CMOS level) input

(D)

Positive supply for digital I O circuits

Lock Det

Lock Detect output Low level when PLL is locked Pulses high when out of lock

Ext Div

External Divide input when DIV SEL is low internal

N output when DIV SEL is high

(D)

Ground for digital I O circuits

CLK Out

Buffered output of the VCO

VCO Divisors Table 1

Prog A

Prog B

Prog C

Div Value

Pin 16

Pin 1

Pin 2

851

864

944

1135

682

858

780

910

35in

TAB

WIDE

35in

EL4584C

Horizontal Genlock 4 F

Description Of Operation

The horizontal sync signal (CMOS level falling
leading edge) is input to H-sync input (pin 10)
This signal is delayed about 110 ns the falling
edge of which becomes the reference to which the
clock output will be locked

(See timing dia-

grams ) The clock is generated by the signal on
pin 5 OSC in There are 2 general types of VCO
that can be used with the EL4584C LC and crys-
tal controlled Additionally each type can be ei-
ther built up using discrete components includ-
ing a varactor as the frequency controlling ele-
ment or complete self contained modules can be
purchased with everything inside a metal can
The modules are very forgiving of PCB layout
but cost more than discrete solutions The VCO
or VCXO is used to generate the clock An LC
tank resonator has greater ``pull'' than a crystal
controlled circuit but will also be more likely to
drift over time and thus will generate more jit-
ter The ``pullability'' of the circuit refers to the
ability to ``pull'' the frequency of oscillation away
from its center frequency by modulating the volt-
age on the control pin of a VCO module or varac-
tor and is a function of the slope and range of
the capacitance-voltage curve of the varactor or
VCO module used The VCO signal is sent to a
divide by N counter and to the CLK out pin The
divisor N is determined by the state of pins 1 2
and 16 and is described in table 1 above The di-
vided signal is sent

along with the delayed

H-sync input to the phase frequency detector
which compares the two signals for phase and
frequency differences Any phase difference is
converted to a current at the charge pump output
FILTER (pin 7) A VCO with positive frequency
deviation with control voltage must be used Va-
ractors have negative capacitance slope with
voltage resulting in positive frequency deviation
with control voltage for the oscillators in figures
10 and 11 below

VCO

The VCO should be tuned so its frequency of os-
cillation is very close to the required clock output
frequency when the voltage on the varactor is 2 5
volts VCXO and VCO modules are already tuned
to the desired frequency so this step is not neces-
sary if using one of these units The range of the
charge pump output (pin 7) is 0 to 5 volts and it

can source or sink a maximum of about 300

so all frequency control must be accomplished
with variable capacitance from the varactor with-
in this range Crystal oscillators are more stable
than LC oscillators which translates into lower
jitter but LC oscillators can be pulled from their
mid-point values further resulting in a greater
capture and locking range If the incoming hori-
zontal sync signal is known to be very stable
then a crystal oscillator circuit can be used If the
h-sync signal experiences frequency variations of
greater than about 300 ppm an LC oscillator
should be considered as crystal oscillators are
very difficult to pull this far When H-SYNC in-
put frequency is greater than CLK frequen-
cy

N charge pump output (pin 7) sources cur-

rent into the filter capacitor increasing the volt-
age across the varactor which lowers its capaci-
tance thus tending to increase VCO frequency
Conversely filter output pulls current from the
filter capacitor when H-SYNC frequency is less
than CLK

N forcing the VCO frequency lower

Loop Filter

The loop filter controls how fast the VCO will
respond to a change in filter output stimulus Its
components should be chosen so that fast lock
can be achieved yet with a minimum of VCO
``hunting'' preferably in one to two oscillations
of charge pump output assuming the VCO fre-
quency starts within capture range If the filter is
under-damped the VCO will over and under-
shoot the desired operating point many times be-
fore a stable lock takes place It is possible to
under-damp the filter so much that the loop itself
oscillates and VCO lock is never achieved If the
filter is over-damped the VCO response time will
be excessive and many cycles will be required for
a lock condition Over-damping is also character-
ized by an easily unlocked system because the
filter can't respond fast enough to perturbations
in VCO frequency A severely over damped sys-
tem will seem to endlessly oscillate like a very
large mass at the end of a long pendulum Due to
parasitic effects of PCB traces and component
variables it will take some trial and error experi-
mentation to determine the best values to use for
any given situation Use the component tables as
a starting point but be aware that deviation from
these values is not out of the ordinary

EL4584C

Horizontal Genlock 4 F

Description of Operation

Contd

External Divide

DIV SEL (pin 8) controls the use of the internal
divider When high the internal divider is en-
abled and EXT DIV (pin 13) outputs the CLK
out divided by N This is the signal to which the
horizontal sync input will lock When divide se-
lect is low the internal divider output is disabled
and external divide becomes an input from an ex-
ternal divider so that a divisor other than one of
the 8 pre-programmed internal divisors can be
used

Normal Mode

Normal mode is enabled by pulling COAST (pin
9) low (below

) If H-sync and CLK

have any phase or frequency difference an error
signal is generated and sent to the charge pump
The charge pump will either force current into or
out of the filter capacitor in an attempt to modu-
late the VCO frequency Modulation will contin-
ue until the phase and frequency of CLK

N ex-

actly match the H-sync input When the phase
and frequency match (with some offset in phase
that is a function of the VCO characteristics) the
error signal goes to zero lock detect no longer
pulses high and the charge pump enters a high
impedance state The clock is now locked to the
H-sync input As long as phase and frequency
differences remain small the PLL can adjust the
VCO to remain locked and lock detect remains
low

Fast Lock Mode

Fast Lock mode is enabled by either allowing
coast to float or pulling it to mid supply (be-
tween

and

) In this mode lock is

achieved much faster than in normal mode but
the clock divisor is modified on the fly to achieve
this If the phase detector detects an error of
enough magnitude the clock is either inhibited
or reset to attempt a ``fast'' lock of the signals

Forcing the clock to be synchronized to the H-
sync input this way allows a lock in approximate-
ly 2 H-cycles but the clock spacing will not be
regular during this time Once the near lock con-
dition is attained charge pump output should be
very close to its lock-on value and placing the
device into normal mode should result in a nor-
mal lock very quickly Fast Lock mode is intend-
ed to be used where H-sync becomes irregular
until a stable signal is again obtained

Coast Mode

Coast mode is enabled by pulling COAST (pin 9)
high (above

) In coast mode the internal

phase detector is disabled and filter out remains
in high impedance mode to keep filter out volt-
age and VCO frequency as constant a possible
VCO frequency will drift as charge leaks from the
filter capacitor and the voltage changes the VCO
operating point Coast mode is intended to be
used when noise or signal degradation result in
loss of horizontal sync for many cycles

The

phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal
sync returns

sync lock can be re-established

quickly However if much VCO drift has oc-
curred it may take as long to re-lock as when
restarting

Lock Detect

Lock detect (pin 12) will go low when lock is es-
tablished

Any DC current path from charge

pump out will skew EXT DIV relative to
H-SYNC in tending to offset or add to the 110 ns
internal delay depending on which way the extra
current is flowing This offset is called static
phase error and is always present in any PLL
system If when the part stabilizes in a locked
mode lock detect is not low adding or subtract-
ing from the loop filter series resistor R

will

change this static phase error to allow LDET to
go low while in lock The goal is to put the rising
edge of EXT DIV in sync with the falling edge of
H-SYNC

110 ns (See timing diagrams ) In-

creasing R

decreases phase error while decreas-

ing R

increases phase error (Phase error is posi-

tive when EXT DIV lags H-SYNC ) The resist-
ance needed will depend on VCO design or VCXO
module selection

EL4584C

Horizontal Genlock 4 F

Applications Information

Choosing External Components

1 To choose LC VCO components first pick the

desired operating frequency For our example
we will use 14 31818 MHz with an H-sync fre-
quency of 15 734 kHz

2 Choose a reasonable inductor value (10 20

works well) We choose 15

3 Calculate C

needed to produce F

OSC

(14 318e6)

(15e

8 2 pF

4 From the varactor data sheet find C

2 5V

the desired lock voltage C

23 pF for our

SMV1204-12 for example

5 C

should be about 10C

so we choose

220 pF for our example

6 Calculate C

Since

)

then

)

For our example C

14 pF (A trim cap may be

used for fine tuning ) Examples for each frequen-
cy using the internal divider follow

Typical Application

Horizontal genlock provides clock for an analog
to digital converter digitizing analog video

Typical LC VCO

4584 10

Figure 10

LC VCO Component Values (Approximate)

Frequency

(MHz)

(mH)

(pF)

13 301

220

13 5

220

14 75

220

17 734

220

10 738

220

12 273

220

14 318

220

Note Use shielded inductors for optimum performance

Typical Xtal VCO

4584 11

Figure 11

4584 18

EL4584C

Horizontal Genlock 4 F

Xtal VCO Component Values (Approximate)

Frequency

(MHz)

(kX)

(pF)

(uF)

13 301

300

001

13 5

300

001

14 75

300

001

17 734

300

001

10 738

300

001

12 273

300

001

14 318

300

001

The above oscillators are arranged as Colpitts os-
cillators and the structure is redrawn here to em-
phasize the split capacitance used in a Colpitts
oscillator It should be noted that this oscillator
configuration is just one of literally hundreds
possible and the configuration shown here does
not necessarily represent the best solution for all
applications Crystal manufacturers are very in-
formative sources on the design and use of oscil-
lators in a wide variety of applications and the
reader is encouraged to become familiar with
them

Colpitts Oscillator

4584 12

is to adjust the center frequency C

DC iso-

lates the control from the oscillator and V1 is the
primary control device C

should be much larger

than C

so that V

has maximum modulation

capability The frequency of oscillation is given
by

)

Choosing Loop Filter
Components

The PLL VCO and loop filter can be described
as

4584 13

Where

phase detector gain in A rad

F(s)

loop filter impedance in V A

VCO

VCO gain in rad s V

internal or external divisor

It can be shown that for the loop filter shown
below

VCO

Where

loop filter bandwidth and

loop

filter damping factor

1 K

300

mA 2

rad

4 77e-5A rad for the

EL4584C

2 The loop bandwidth should be about H-sync

frequency 20 and the damping ratio should be
1 for optimum performance For our example

15 734 kHz 20

787 Hz

5000 rad S

3 N

910 from table 1

VCOfrequency

H-SYNCfrequency

14 31818M

15 73426k

910

4 K

VCO

represents how much the VCO frequen-

cy changes for each volt applied at the control
pin It is assumed (but probably isn't) linear
about the lock point (2 5V) Its value depends
on the VCO configuration and the varactor

EL4584C

Horizontal Genlock 4 F

transfer function C

F(V

) where V

is the

reverse bias control voltage and C

is varactor

capacitance

Since F(V

) is nonlinear

it is

probably best to build the VCO and measure
K

VCO

about 2 5V The results of one such mea-

surement are shown below The slope of the
curve is determined by linear regression tech-
niques and equals K

VCO

For our example

VCO

6 05 Mrad S V

OSC

vs V

LC VCO

4584 14

5 Now we can solve for C

and R

VCO

(4 77e

5)(6 05e6)

(910)(5000)

0 01

0 001

VCO

(2)(910)(1)(5000)

(4 77e

5)(6 05e6)

31 5 k

We choose R

30 k

X for convenience

6 Notice R

has little effect on the loop filter de-

sign R

should be large around 100k and can

be adjusted to compensate for any static phase
error T

at lock but if made too large will

slow loop response If R

is made smaller T

(see timing diagrams) increases and if R

in-

creases T

decreases For LDET to be low at

lock

50 ns C

is used mainly to attenu-

ate high frequency noise from the charge
pump

Lock Time

Let

As T increases damping increases

but so does lock time Decreasing T decreases
damping and speeds up loop response but in-
creases overshoot and thus increases the number
of hunting oscillations before lock Critical damp-
ing (

1) occurs at minimum lock time Because

decreased damping also decreases loop stability
it is sometimes desirable to design slightly over-
damped (

1) trading lock time for increased

stability

Typical Loop Filter

4584 16

LC Loop Filter Components (Approximate)

Frequency

(MHz)

(kX)

(mF)

13 301

100

0 01

0 001

13 5

100

0 01

0 001

14 75

100

0 01

0 001

17 734

100

0 01

0 001

10 738

100

0 01

0 001

12 273

100

0 01

0 001

14 318

100

0 01

0 001

Xtal Loop Filter Components (Approximate)

Frequency

(MHz)

(kX)

(MX)

(pF)

13 301

100

4 3

6 8

13 5

100

4 3

6 8

14 75

100

4 3

6 8

17 734

100

4 3

6 8

10 738

100

4 3

6 8

12 273

100

4 3

6 8

14 318

100

4 3

6 8

EL4584C

Horizontal Genlock 4 F

PCB Layout Considerations

It is highly recommended that power and ground
planes be used in layout The oscillator and filter
sections constitute a feedback loop and thus care
must be taken to avoid any feedback signal influ-
encing the oscillator except at the control input
The entire oscillator filter section should be sur-
rounded by copper ground to prevent unwanted
influences from nearby signals

Use separate

paths for analog and digital supplies keeping the
analog (oscillator section) as short and free from
spurious signals as possible Careful attention
must be paid to correct bypassing Keep lead
lengths short and place bypass caps as close to
the supply pins as possible If laying out a PCB
to use discrete components for the VCO section

care must be taken to avoid parasitic capacitance
at the OSC pins 3 and 5 and FILTER out (pin
7)

Remove ground and power plane copper

above and below these traces to avoid making a
capacitive connection to them It is also recom-
mended to enclose the oscillator section within a
shielded cage to reduce external influences on the
VCO as they tend to be very sensitive to ``hand-
waving'' influences the LC variety being more
sensitive than crystal controlled oscillators In
general the higher the operating frequency the
more important these considerations are

Self

contained VCXO or VCO modules are already
mounted in a shielding cage and therefore do not
require as much consideration in layout Many
crystal manufacturers publish informative litera-
ture regarding use and layout of oscillators which
should be helpful

EL4584C

February

1995

Rev

EL4584C

Horizontal Genlock 4 F

Component Sources

Inductors

Dale Electronics

E Highway 50
PO Box 180
Yankton SD 57078-0180
(605) 665-9301

Crystals VCXO VCO Modules

Connor-Winfield

2111 Comprehensive Drive
Aurora IL 60606
(708) 851-4722

Piezo Systems

100 K Street
PO Box 619
Carlisle PA 17013
(717) 249-2151

Reeves-Hoffman

400 West North Street
Carlisle PA 17013
(717) 243-5929

SaRonix

151 Laura Lane
Palo Alto CA 94043
(415) 856-6900

Standard Crystal

9940 Baldwin Place
El Monte CA 91731
(818) 443-2121

Varactors

Alpha Industries

20 Sylvan Road
Woburn MA 01801
(617) 935-5150

Motorola Semiconductor Products

2100 E Elliot
Tempe AZ 85284
(602) 244-6900

Note These sources are provided for information
purposes only No endorsement of these compa-
nies is implied by this listing

General Disclaimer

Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes
in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any
circuits described herein and makes no representations that they are free from patent infringement

Elantec Inc
1996 Tarob Court
Milpitas CA 95035
Telephone (408) 945-1323

(800) 333-6314

Fax (408) 945-9305

European Office 44-71-482-4596

WARNING

Life Support Policy

Elantec Inc products are not authorized for and should not be
used within Life Support Systems without the specific written
consent of Elantec Inc Life Support systems are equipment in-
tended to support or sustain life and whose failure to perform
when properly used in accordance with instructions provided can
be reasonably expected to result in significant personal injury or
death Users contemplating application of Elantec Inc products
in Life Support Systems are requested to contact Elantec Inc
factory headquarters to establish suitable terms

conditions for

these applications Elantec Inc 's warranty is limited to replace-
ment of defective components and does not cover injury to per-
sons or property or other consequential damages

Printed in U S A

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