Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a "controlled document". Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
2001 Elantec Semiconductor, Inc.
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General Description
The EL5283C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between V
S
+ and V
S
-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground-sensing applications.
The output side of the comparators can be supplied from a single sup-
ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5283C can be used to hold the comparator
output value by applying a low logic level to the pin.
The EL5283C contains two comparators set up as a window compara-
tor. A single input is compared with a high and low reference. When
the output goes beyond one of these reference signals, the relevant out-
put goes high.
The EL5283C in the 10-pin MSOP package and is specified for opera-
tion over the full -40C to +85C temperature range. Also available
are a single (EL5181C) and quad versions (EL5481C and EL5482C).
Pin Configurations
1
2
3
4
10
9
8
7
5
6
EL5283C
(10-Pin MSOP)
VS+
VREFH
IN
VREFL
VS-
VSD
OUTH
LATCH
OUTL
GND
-
+
-
+
Features
8ns typ. propagation delay
5V to 12V input supply
+2.7V to +5V output supply
True-to-ground input
Rail-to-rail outputs
Active low latch
Single available (EL5181C)
Quad available (EL5481C &
EL5482C)
Pin-compatible 4ns family
available (EL5x85C, EL5287C &
EL5486C)
Applications
Threshold detection
High speed sampling circuits
High speed triggers
Line receivers
PWM circuits
High speed V/F converters
Ordering Information
Part No.
Package
Tape & Reel
Outline #
EL5283CY
10-Pin MSOP
-
MDP0043
EL5283CY-T13
10-Pin MSOP
13"
MDP0043
EL5283C - Preliminary
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Absolute Maximum Ratings
(T
A
= 25C)
Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied.
Analog Supply Voltage (V
S
+ to V
S
-)
+13.2V
Digital Supply Voltage (V
SD
to GND)
+7V
Differential Input Voltage
[(V
S
-) -0.2V] to [(V
S
+) +0.2V]
Common-mode Input Voltage
[(V
S
-) -0.2V] to [(V
S
+) +0.2V]
Latch Input Voltage
-0.2V to [(V
SD
)
+0.2V]
Storage Temperature Range
-65C to +150C
Ambient Operating Temperature
-40C to +85C
Operating Junction Temperature
125C
Power Dissipation
See Curves
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
.
Electrical Characteristics
V
S
= 5V, V
SD
= 5V, R
L
= 2.3k
, C
L
= 15pF, T
A
= 25C, unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
Unit
Input
V
OS
Input Offset Voltage
V
CM
= 0V, V
O
= 2.5V
1
4
mV
I
B
Input Bias Current
-6
-3.5
A
C
IN
Input Capacitance
5
pF
I
OS
Input Offset Current
V
CM
= 0V, V
O
= 2.5V
-2.5
0.5
2.5
A
V
CM
Input Voltage Range
(V
S
-) - 0.1
(V
S
+) - 2.25
V
CMRR
Common-mode Rejection Ratio
-5.1V < V
CM
< +2.75V
65
90
dB
Output
V
OH
Output High Voltage
V
IN
> 250mV
V
SD
- 0.6
V
SD
- 0.4
V
V
OL
Output Low Voltage
V
IN
> 250mV
GND + 0.25
GND + 0.5
V
Dynamic Performance
t
pd
+
Positive Going Delay Time
V
IN
= 1V
P-P
, V
OD
= 50mV
8
12
ns
t
pd
-
Negative Going Delay Time
V
IN
= 1V
P-P
, V
OD
= 50mV
8
12
ns
Supply
I
S
+
Positive Analog Supply Current
(per comparator)
7
8.2
mA
I
S
-
Negative Analog Supply Current
(per comparator)
5
6.5
mA
I
SD
Digital Supply Current
(per comparator) All inputs high
4
5
mA
(per comparator) All inputs low
0.75
1
mA
PSRR
Power Supply Rejection Ratio
60
80
dB
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Typical Performance Curves
Positive Supply Current vs Temperature
(per comparator)
6.15
6.1
6.05
6
5.95
5.9
5.85
5.8
5.75
5.7
-50
-30
-10
10
30
50
70
90
Temperature (C)
I
S
+
(
m
A
)
Negative Supply Current vs Temperature
(per comparator)
-4.4
-4.5
-4.6
-4.7
-4.8
-4.9
-5
-5.1
-5.2
-50
-30
-10
10
30
50
70
90
Temperature (C)
I
S
-
(
m
A
)
Input Bias Current vs Temperature
6
5
4
3
2
1
0
-50
-30
-10
10
30
50
70
90
Temperature (C)
I
B
(
A
)
Offset Voltage vs Temperature
0.7
0.6
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-50
-30
-10
10
30
50
70
90
Temperature (C)
V
O
S
(
m
V
)
0.5
Negative Supply Current vs Negative Supply Voltage
(per comparator)
5.5
3
5
3.5
4.5
4
0
7
1
2
3
4
5
6
V
S
- (V)
I
S
-
(
m
A
)
V
S
=5V
V
SD
=5V
V
IN
=50mV
T
A
=25C
7
0
5
1
3
2
I
S
+
(
m
A
)
Positive Supply Current vs Supply Voltage
(per comparator)
0
7
1
2
3
4
5
6
V
S
+ (V)
6
4
V
S
=5V
V
SD
=5V
V
IN
=50mV
T
A
=25C
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Typical Performance Curves
Propagation Delay vs Supply Voltage
V
IN
=1V Step
10
9.5
8.5
7.5
7
6.5
6
5.5
5
9
8
4
4.5
5
5.5
6
V
S
(V)
D
e
l
a
y
T
i
m
e
(
n
s
)
T
pd
+
T
pd
-
V
SD
=V
S
+
V
IN
=1V Step
V
OD
=50mV
R
L
=2.2k
Propagation Delay vs Overdrive
V
IN
=3V
P-P
Step
10
9.5
8.5
8
7.5
7
6.5
6
9
0
0.2
0.6
1
1.2
1.6
2
V
OD
(mV)
D
e
l
a
y
T
i
m
e
(
n
s
)
T
pd
+
T
pd
-
V
S
=5V
V
SD
=5V
V
IN
=1V Step
R
L
=2.2k
0.4
0.8
1.4
1.8
Propagation Delay vs Overdrive
V
IN
=5V
P-P
Step
11
10.5
9.5
9
8.5
8
7.5
7
10
0
0.5
1
2
3
V
OD
(V)
D
e
l
a
y
T
i
m
e
(
n
s
)
T
pd
+
T
pd
-
V
S
=5V
V
SD
=5V
R
L
=2.2k
V
IN
=5V Step
1.5
2.5
Propagation Delay vs Source Resistance
V
IN
=1V Step
20
18
14
12
10
8
6
4
16
0
0.2
0.4
1
1.6
Source Resistance (k
)
D
e
l
a
y
T
i
m
e
(
n
s
)
T
pd
+
T
pd
-
0.6
1.4
1.2
0.8
V
S
=5V
V
SD
=5V
R
L
=2.2k
V
IN
=1V Step
V
OD
=50mV
Propagation Delay vs Overdrive
V
IN
=1V Step
10
9.5
8.5
7.5
7
6.5
6
5.5
5
9
8
0
100
200
300
400
500
600
V
OD
(mV)
D
e
l
a
y
T
i
m
e
(
n
s
)
T
pd
+
T
pd
-
V
S
=5V
V
SD
=5V
V
IN
=1V Step
R
L
=2.2k
Propagation Delay vs Load Capacitance
V
IN
=1V Step
12
10
9
8
7
6
11
0
20
40
60
80
100
120
C
LOAD
(pF)
D
e
l
a
y
T
i
m
e
(
n
s
)
T
pd
+
T
pd
-
V
S
=5V
V
SD
=5V
R
L
=2.2k
V
IN
=1V Step
V
OD
=50mV
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Typical Performance Curves
0
10
2
4
6
Load Current (mA)
Output Low Voltage vs Load Current
0.31
0.15
0.27
O
u
t
p
u
t
L
o
w
V
o
l
t
a
g
e
(
V
)
8
0.23
0.19
V
S
=5V
V
SD
=5V
V
IN
=-50mV
T
A
=85C
T
A
=25C
T
A
=-40C
0
10
2
4
6
Load Current (mA)
8
Output High Voltage vs Load Current
4.75
4.3
4.7
O
u
t
p
u
t
H
i
g
h
V
o
l
t
a
g
e
(
V
)
4.65
4.6
4.55
4.5
4.45
4.4
4.35
V
S
=5V
V
SD
=5V
V
IN
=50mV
T
A
=-40C
T
A
=85C
T
A
=25C
Digital Supply Current vs Input Switching Frequency (per
comparator)
50
0
40
30
20
10
0
30
25
20
15
10
5
V
SD
=5V
V
SD
=3V
V
S
=5V
T=25C
Frequency (MHz)
I
S
D
(
m
A
)
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity Test
0.6
0
0.3
P
o
w
e
r
D
i
s
s
i
p
a
t
i
o
n
(
W
)
0.5
0.1
0
100
75
50
25
Ambient Temperature (C)
125
2V
V
IN
=1V
P-P
F
IN
=30MHz
1V
20ns
V
S
=5V
V
SD
=5V
Output with 30MHz Input
V
IN
=1V
P-P
2V
2V
20ns
V
IN
=3V
P-P
F
IN
=30MHz
V
S
=5V
V
SD
=5V
Output with 30MHz Input
V
IN
=3V
P-P
V
O
V
IN
V
O
V
IN
0.2
0.4
85
486mW
MSO
P10
206
C/W
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Timing Diagram
V
IN
V
DD
t
h
t
s
t
pd
-
t
pw
(D)
t
d
+(D)
Latch
Enable
Input
Latch
Compare
Latch
Latch
Compare
Differential
Input
Voltage
Comparator
Output
1.4V
V
OS
2.4V
Definition of Terms
Terms
Definition
V
OS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
V
IN
Input Voltage Pulse Amplitude - Usually set to 100mV for comparator specifications
V
OD
Input Voltage Overdrive - Usually set to 5mV and in opposite polarity to VIN for comparator specifications
t
pd
+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
t
pd
-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
t
d
+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
t
d
-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
t
s
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
t
h
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
t
pw
(D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
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Applications Information
Power Supplies and Circuit Layout
The EL5283C comparator operates with single and dual
supply with 5V to 12V between V
S
+ and V
S
-. The out-
put side of the comparators is supplied by a single
supply from 2.7V to 5V. The rail to rail output swing
enables direct connection of the comparator to both
CMOS and TTL logic circuits. As with many high speed
devices, the supplies must be well bypassed. Elantec rec-
ommends a 4.7F tantalum in parallel with a 0.1F
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also mini-
mize unwanted parasitic feedback around the
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance sta-
bility of the comparators.
Input Voltage Considerations
The EL5283C input range is specified from 0.1V below
V
S
- to 2.25V below V
S
+. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the cor-
rect logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differ-
ential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage. Inputs of
unused channels should not be left floating. They should
be driven to a known state. For example, one input can
Pin Descriptions
Pin Number
Pin Name
Function
Equivalent Circuit
1
VS+
Positive supply voltage
2
VREFH
Upper voltage reference
Circuit 4
3
IN
Input
(Reference Circuit 4)
4
VREFL
Lower voltage reference
(Reference Circuit 4)
5
VS-
Negative supply voltage
6
GDN
Digital ground
7
OUTL
Low output
(Reference Circuit 2)
8
LATCH
Latch
(Reference Circuit 3)
9
OUTH
High output
(Reference Circuit 2)
10
VSD
Digital supply voltage
IN
VREF
V
S
+
V
S
-
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be tied to ground and the other input can be connected to
some voltage reference (like 100mV) to avoid oscilla-
tion in the output due to unwanted output to input
feedback.
Input Slew Rate
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain min-
imum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hyster-
esis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5283C, the propagation delay increases when the
input slew rate increases for low overdrive voltages.
With high overdrive voltages, the propagation delay
does not change much with the input slew rate.
Latch Pin Dynamics
The EL5283C contains a "transparent" latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is con-
nected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
latches remains latched to its value just before the latch
high-to-low transition. To guarantee data retention, the
input signal must remain the same state at least 1ns (hold
time) after the latch goes low and at least 2ns (setup
time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approxi-
mately 8ns (latch propagation delay).
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
T
JMAX
(125C).
An approximate equation for the device power dissipa-
tion is as follows. Assume the power dissipation in the
load is very small:
where:
V
S
is the analog supply voltage from V
S
+ to V
S
-
I
S
is the analog quiescent supply current per comparator
V
SD
is the digital supply voltage from V
SD
to ground
I
SD
is the digital supply current per comparator
N is the number of comparators in the package
I
SD
strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipa-
tion, the maximum junction temperature can be
determined as follows:
where:
T
MAX
is the maximum ambient temperature
JA
is the thermal resistance of the package
Window Detector
If V
IN
is in the range of V
REFL
< V
IN
< V
REFH
, both out-
puts go high and the input in range is high. If V
IN
is out
of the range set by V
REFH
and V
REFL
, the input in range
is low.
P
DISS
V
S
I
S
V
SD
I
SD
)
N
+
(
=
T
JMAX
T
MAX
JA
P
DISS
+
=
-
+
-
+
OUTH
Input In
Range
OUTL
V
REFL
V
IN
V
REFH
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General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.'s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
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Printed in U.S.A.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
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