1
FN7311.2
EL5172, EL5372
250MHz Differential Line Receivers
The EL5172 and EL5372 are single
and triple high bandwidth amplifiers
designed to extract the difference
signal from noisy environments. They are primarily targeted
for applications such as receiving signals from twisted-pair
lines or any application where common mode noise injection
is likely to occur.
The EL5172 and EL5372 are stable for a gain of one and
requires two external resistors to set the voltage gain.
The output common mode level is set by the reference pin
(V
REF
), which has a -3dB bandwidth of over 120MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
The output can deliver a maximum of 60mA and is short
circuit protected to withstand a temporary overload
condition.
The EL5172 is available in the 8-pin SO and 8-pin MSOP
packages and the EL5372 in a 24-pin QSOP package. Both
are specified for operation over the full -40C to +85C
temperature range.
Features
Differential input range 2.3V
250MHz 3dB bandwidth
800V/s slew rate
60mA maximum output current
Single 5V or dual 5V supplies
Low power - 5mA to 6mA per channel
Applications
Twisted-pair receivers
Differential line receivers
VGA over twisted-pair
ADSL/HDSL receivers
Differential to single-ended amplification
Reception of analog signals in a noisy environment
Ordering Information
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL5172IS
8-Pin SO
-
MDP0027
EL5172IS-T7
8-Pin SO
7"
MDP0027
EL5172IS-T13
8-Pin SO
13"
MDP0027
EL5172IY
8-Pin MSOP
-
MDP0043
EL5172IY-T7
8-Pin MSOP
7"
MDP0043
EL5172IY-T13
8-Pin MSOP
13"
MDP0043
EL5372IU
24-Pin QSOP
-
MDP0040
EL5372IU-T7
24-Pin QSOP
7"
MDP0040
EL5372IU-T13
24-Pin QSOP
13"
MDP0040
Pinouts
EL5172
(8-PIN SO, MSOP)
TOP VIEW
EL5372
(24-PIN QSOP)
TOP VIEW
1
2
3
4
8
7
6
5
-
+
OUT
VS-
VS+
EN
FB
IN+
IN-
REF
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
REF1
INP1
INN1
NC
REF2
INP2
INN2
NC
REF3
INP3
INN3
NC
NC
FB1
OUT1
NC
VSP
VSN
NC
FB2
OUT2
EN
FB3
OUT3
-
+
-
+
-
+
Data Sheet
August 22, 2003
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
2
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Absolute Maximum Ratings
(T
A
= 25C)
Supply Voltage (V
S
+ to V
S
-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
S
+ = +5V, V
S
- = -5V, T
A
= 25C, V
IN
= 0V, R
L
= 500
, R
F
= 0, R
G
= OPEN, C
L
= 2.7pF, unless otherwise
specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW -3dB
Bandwidth
A
V
=1,
C
L
= 2.7pF
250
MHz
A
V
=2,
R
F
= 1000
, C
L
= 2.7pF
70
MHz
A
V
=10,
R
F
= 1000
, C
L
= 2.7pF
10
MHz
BW
0.1dB Bandwidth
A
V
=1,
C
L
= 2.7pF
25
MHz
SR
Slew Rate
V
OUT
= 3V
P-P
, 20% to 80%, EL5172
600
800
1000
V/s
V
OUT
= 3V
P-P
, 20% to 80%, EL5372
550
700
1000
V/s
T
STL
Settling Time to 0.1%
V
OUT
= 2V
P-P
10
ns
T
OVR
Output Overdrive Recovery time
20
ns
GBWP
Gain Bandwidth Product
100
MHz
V
REF
BW
(-3dB) V
REF
-3dB Bandwidth
A
V
=1,
C
L
= 2.7pF
120
MHz
V
REF
SR
V
REF
Slew Rate
V
OUT
= 2V
P-P
, 20% to 80%
600
V/s
V
N
Input Voltage Noise
at f = 11kHz
26
nV/
Hz
I
N
Input Current Noise
at f = 11kHz
2
pA/
Hz
HD2
Second Harmonic Distortion
V
OUT
= 1V
P-P
, 5MHz
-66
dBc
V
OUT
= 2V
P-P
, 50MHz
-63
dBc
HD3
Third Harmonic Distortion
V
OUT
= 1V
P-P
, 5MHz
-84
dBc
V
OUT
= 2V
P-P
, 50MHz
-76
dBc
dG
Differential Gain at 3.58MHz
R
L
= 150
,
A
V
=2
0.04
%
d
Differential Phase at 3.58MHz
R
L
= 150
,
A
V
=2
0.41
e
S
Channel Separation at 100kHz
EL5372 only
90
dB
INPUT CHARACTERISTICS
V
OS
Input Referred Offset Voltage
7
25
mV
I
IN
Input Bias Current (V
IN
, V
INB
, V
REF
)
-14
-6
-3
A
R
IN
Differential Input Resistance
300
k
C
IN
Differential Input Capacitance
1
pF
DMIR
Differential Input Range
2.1
2.38
2.5
V
CMIR
Common Mode Input Range at V
IN
+, V
IN
-
-4.3
3.3
V
V
REFIN
Reference Input Voltage Range
V
IN
+ = V
IN
- = 0V
-3.6
3.3
V
EL5172, EL5372
3
CMRR
Input Common Mode Rejection Ratio
V
IN
= 2.5V
75
95
dB
Gain
Gain Accuracy
V
IN
= 1
0.985
1
1.015
V
OUTPUT CHARACTERISTICS
V
OUT
Positive Output Voltage Swing
R
L
= 500
to GND
3.3
3.63
V
Negative Output Voltage Swing
R
L
= 500
to GND
-3.87
-3.5
V
I
OUT
(Max)
Maximum Output Current
R
L
= 10
60
95
mA
R
OUT
Output Impedance
100
m
SUPPLY
V
SUPPLY
Supply Operating Range
V
S
+ to V
S
-
4.75
11
V
I
S (on)
Power Supply Current Per Channel -
Enabled
4.6
5.6
7
mA
I
S (off)
+
Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5172
80
100
A
EN pin tied to 4.8V, EL5372
1.7
5
A
I
S (off)
-
Negative Power Supply Current -
Disabled
-150
-120
-90
A
PSRR
Power Supply Rejection Ratio
V
S
from 4.5V to 5.5V
50
58
dB
ENABLE
t
EN
Enable Time
150
ns
t
DS
Disable Time
1.4
s
V
IH
EN Pin Voltage for Power-up
V
S
+
-1.5
V
V
IL
EN Pin Voltage for Shut-down
V
S
+
-0.5
V
I
IH-EN
EN Pin Input Current High Per Channel
At V
EN
= 5V
40
60
A
I
IL-EN
EN Pin Input Current Low Per Channel
At V
EN
= 0V
-10
-3
A
Electrical Specifications
V
S
+ = +5V, V
S
- = -5V, T
A
= 25C, V
IN
= 0V, R
L
= 500
, R
F
= 0, R
G
= OPEN, C
L
= 2.7pF, unless otherwise
specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
EL5172, EL5372
4
Pin Descriptions
EL5172
EL5372
PIN NAME
PIN FUNCTION
1
FB
Feedback input
2
IN+
Non-inverting input
3
IN-
Inverting input
4
REF
Sets the common mode output voltage level
5
EN
Enabled when this pin is floating or the applied voltage
V
S
+ - 1.5
6
VS+
Positive supply voltage
7
VS-
Negative supply voltage
8
OUT
Output voltage
1, 5, 9
REF1, 2, 3
Reference input, controls common-mode output voltage
2, 6, 10
INP1, 2, 3
Non-inverting inputs
3, 7, 11
INN1, 2, 3
Inverting inputs
4, 8, 12, 18, 21, 24
NC
No connect, grounded for best crosstalk performance
13, 16, 22
OUT1, 2, 3
Non-inverting outputs
14, 17, 23
FB1, 2, 3
Feedback from outputs
15
EN
Enabled when this pin is floating or the applied voltage
V
S
+ - 1.5
19
VSN
Negative supply
20
VSP
Positive supply
EL5172, EL5372
5
Connection Diagrams
FB
INP
INN
REF
OUT
VSN
VSP
EN
1
2
3
4
8
7
6
5
INP
INN
REF
R
G
R
S3
EN
VOUT
-5V
+5V
R
F
=0
50
R
S2
50
R
S2
50
C
L
2.7pF
R
L
500
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
REF1
INP1
INN1
NC
REF2
INP2
INN2
NC
REF3
INP3
INN3
NC
NC
FB1
OUT1
NC
VSP
VSN
NC
FB2
OUT2
EN
FB3
OUT3
R
SR3
50
R
SN3
50
R
SP3
50
R
SR2
50
R
SN2
50
R
SP2
50
R
SR1
50
R
SN1
50
R
SP1
50
REF1
INP1
INN1
REF2
INP2
INN2
REF3
INP3
INN3
+5V
C
L2
2.7pF
C
L3
2.7pF
OUT3
OUT1
R
G
R
F
R
L1
500
C
L1
2.7pF
-5V
OUT2
R
G
R
F
R
L2
500
ENABLE
R
L3
500
R
G
R
F
EL5172
EL5372
EL5172, EL5372
6
Typical Performance Curves
FIGURE 1. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 3. FREQUENCY RESPONSE vs VARIOUS GAIN
FIGURE 4. FREQUENCY RESPONSE vs C
L
FIGURE 5. FREQUENCY RESPONSE vs C
L
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS R
F
4
3
1
0
-2
-3
-5
-6
10M
100M
1G
MA
GNITUDE (dB)
FREQUENCY (Hz)
-4
-1
2
1M
V
S
= 5V
V
S
= 2.5V
A
V
= 1, R
L
= 500
, C
L
= 2.7pF
4
3
1
0
-2
-3
-5
-6
10M
100M
1G
FREQUENCY (Hz)
-4
-1
2
1M
V
S
= 5V
V
S
= 2.5V
MA
GNI
T
U
D
E
(
d
B)
A
V
= 1, R
L
= 100
, C
L
= 2.7pF
4
3
1
0
-2
-3
-5
-6
10M
100M
1G
NORMAL
IZED GAIN
(dB)
FREQUENCY (Hz)
-4
-1
2
1M
A
V
= 1
A
V
= 2
A
V
= 5
A
V
= 10
V
S
= 5V, R
L
= 500
, C
L
= 2.7pF
5
4
2
1
-1
-2
-4
-5
10M
100M
1G
FREQUENCY (Hz)
-3
0
3
1M
C
L
= 56pF
C
L
= 33pF
C
L
= 15pF
C
L
= 10pF
C
L
= 2.7pF
M
A
GN
ITUDE
(
d
B)
V
S
= 5V, A
V
= 1, R
L
= 500
10M
100M
1G
FREQUENCY (Hz)
1M
C
L
= 56pF
C
L
= 33pF
C
L
= 15pF
C
L
= 10pF
C
L
= 2.7pF
MA
GNITUDE (dB)
5
4
2
1
-1
-2
-4
-5
-3
0
3
V
S
= 5V, A
V
= 1, R
L
= 500
4
3
1
0
-2
-3
-5
-6
10M
100M
1G
NORMALIZED GAIN
(
d
B)
FREQUENCY (Hz)
-4
-1
2
1M
R
F
= 1k
R
F
= 200
R
F
= 500
V
S
= 5V, A
V
=2, R
L
= 500
, C
L
= 2.7pF
EL5172, EL5372
7
FIGURE 7. FREQUENCY RESPONSE FOR V
REF
FIGURE 8. OPEN LOOP GAIN
FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 10. PSRR vs FREQUENCY
FIGURE 11. CMRR vs FREQUENCY
FIGURE 12. VOLTAGE AND CURRENT NOISE vs FREQUENCY
Typical Performance Curves
(Continued)
4
3
1
0
-2
-3
-5
-6
10M
100M
1G
NORMINALIZED GAIN
(dB)
FREQUENCY (Hz)
-4
-1
2
1M
V
S
= 2.5V
V
S
= 5V
A
V
= 1, R
L
= 500
, C
L
= 2.7pF
60
50
30
20
0
-10
-30
-40
100K
10M
500M
GAI
N
(d
B)
FREQUENCY (Hz)
-20
10
40
10K
1M
100M
270
225
135
90
0
-45
-135
-180
-90
45
180
PHAS
E ()
100
10
1
0.1
100K
1M
100M
IMP
E
DENCE (
)
FREQUENCY (Hz)
10K
10M
0
-10
-30
-50
-60
-80
-90
10K
1M
100M
PS
R
R
(dB)
FREQUENCY (Hz)
-70
-40
-20
1K
100K
10M
PSRR+
PSRR-
1M
100M
CMRR (dB)
FREQUENCY (Hz)
100K
10M
1G
100
90
70
60
40
30
10
0
20
50
80
1K
100
10
1
V
O
L
T
A
G
E
NO
IS
E
(nV/
Hz
)
,
100
100K
10M
FREQUENCY (Hz)
10
10K
1M
1K
E
N
I
N
CUR
RE
NT
NOISE
(pA/
Hz
)
EL5172, EL5372
8
FIGURE 13. CHANNEL ISOLATION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FIGURE 15. HARMONIC DISTORTION vs LOAD RESISTANCE
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
Typical Performance Curves
(Continued)
1M
100M
GAI
N
(
d
B)
FREQUENCY (Hz)
100K
10M
1G
0
-10
-30
-40
-60
-70
-90
-100
-80
-50
-20
CH1 <=> CH2, CH2 <=> CH3
CH1 <=> CH3
-45
-50
-60
-70
-80
-85
DI
ST
OR
T
I
ON (d
B)
-75
-65
-55
2
5
V
OP-P
(V)
1
4
6
3
7
HD
2 (A
V
= 2
)
HD3 (A
V
= 2)
HD2
(A
V
= 1
)
HD3 (A
V
= 1)
V
S
= 5V, R
L
= 500
, f = 5MHz
-45
-50
-60
-70
-80
-85
DIS
T
OR
TI
ON (d
B)
-75
-65
-55
200
700
R
LOAD
(
)
100
600
900
400
1000
HD3 (A
V
= 1)
-80
300
500
800
HD3
(A
V
= 2)
V
S
= 5V, f = 5MHz, V
OP-P
= 1V @A
V
= 1,
V
OP-P
= 2 V @A
V
= 2
HD2 (A
V
= 2)
HD2 (A
V
= 1)
-40
-50
-60
-70
-90
DIS
T
OR
TI
ON (d
B)
-80
5
25
FREQUENCY (MHz)
0
35
15
40
-100
10
20
30
HD2
(A
V
= 2)
HD3 (A
V
= 1)
HD2 (A
V
= 1)
V
S
= 5V, R
L
= 500
, V
OP-P
= 1V for A
V
= 1,
V
OP-P
= 2V for A
V
= 2
HD3 (A
V
= 2)
50mV/DIV
10ns/DIV
0.5V/DIV
10ns/DIV
EL5172, EL5372
9
Simplified Schematic
FIGURE 19. ENABLED RESPONSE
FIGURE 20. DISABLED RESPONSE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves
(Continued)
CH1
CH2
100ns/DIV
M = 100ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
CH1
CH2
400ns/DIV
M = 400ns, CH1 = 200mV/DIV, CH2 = 5V/DIV
486mW
JA
=206C/W
MSOP8
870mW
JA
=115C/W
QSOP24
1.2
1
0.8
0.6
0.4
0
0
25
50
75
100
150
AMBIENT TEMPERATURE (C)
POWER DIS
S
IP
AT
ION (W)
125
85
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.2
625mW
JA
=160C/W
SO8
1.136W
JA
=88C/W
QSOP24
1.4
1.2
1
0.8
0.6
0.2
0
0
25
50
75
100
150
AMBIENT TEMPERATURE (C)
POWER DIS
S
IP
AT
ION (W)
125
85
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.4
909mW
JA
=110C/W
SO8
870mW
JA
=115C/W
MSOP8/10
R
2
R
1
R
4
R
3
R
D2
R
D1
Q
8
FBN
Q
4
FBP
Q
3
VIN-
Q
2
VIN+
Q
1
Q
6
V
S
+
I
4
I
3
I
2
I
1
Q
7
V
B1
V
S
-
25
Q
9
V
B2
x1
V
OUT
C
C
EL5172, EL5372
10
Description of Operation and Application
Information
Product Description
The EL5172 and EL5372 are wide bandwidth, low power
and single/differential ended to single ended output
amplifiers. The EL5172 is a single channel differential to
single ended amplifier. The EL5372 is a triple channel
differential to single ended amplifier. The EL5172 and
EL5372 are internally compensated for closed loop gain of
+1 of greater. Connected in gain of 1 and driving a 500
load, the EL5172 and EL5372 have a -3dB bandwidth of
250MHz. Driving a 150
load at gain of 2, the bandwidth is
about 50MHz. The bandwidth at the REF input is about
450MHz. The EL5172 and EL5372 is available with a power
down feature to reduce the power while the amplifier is
disabled.
Input, Output, and Supply Voltage Range
The EL5172 and EL5372 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
5V supply. The differential mode input range (DMIR)
between the two inputs is about from -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal
distorted.
The output of the EL5172 and EL5372 can swing from -3.8V
to 3.6V at 500
load at 5V supply. As the load resistance
becomes lower, the output swing is reduced respectively.
Over All Gain Settings
The gain setting for the EL5172 and EL5372 is similar to the
conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus V
REF
and then
times the gain.
FIGURE 23.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Therefore, R
F
has some maximum value that should not be
exceeded for optimum performance. If a large value of R
F
must be used, a small capacitor in the few Pico farad range
in parallel with R
F
can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5172 and EL5372 depends on the
load and the feedback network. R
F
and R
G
appear in
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, R
F
also has a minimum value that should not
be exceeded for optimum bandwidth performance. For gain
of +1, R
F
= 0 is optimum. For the gains other than +1,
optimum response is obtained with R
F
between 500
to
1k
. For A
V
= 2 and R
F
= R
G
= 1k
, the BW is about 80MHz
and the frequency response is very flat.
The EL5172 and EL5372 have a gain bandwidth product of
100MHz. For gains
5, its bandwidth can be predicted by the
following equation:
Driving Capacitive Loads and Cables
The EL5172 and EL5372 can drive 56pF capacitance in
parallel with 500
load to ground with 4dB of peaking at gain
of +1. If less peaking is desired in applications, a small
series resistor (usually between 5
to 50) can be placed in
series with each output to eliminate most peaking. However,
this will reduce the gain slightly. If the gain setting is greater
than 1, the gain resistor R
G
can then be chosen to make up
for any gain loss which may be created by the additional
series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5172 and EL5372 can be disabled and placed its
outputs in a high impedance state. The turn off time is about
1.4s and the turn on time is about 150ns. When disabled,
the amplifier's supply current is reduced to 80A for I
S
+ and
V
O
V
(
IN
+
V
IN
-
V
REF
+
)
1
R
F
R
G
--------
+
=
-
+
-
+
G/B
V
O
EN
V
IN
+
V
IN
-
V
REF
FB
R
G
R
F
Gain
BW
100MHz
=
EL5172, EL5372
11
120A for I
S
- typically, thereby effectively eliminating the
power consumption. The amplifier's power down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to V
S
+ pin. Letting the
EN pin float or applying a signal that is less than 1.5V below
V
S
+ will enable the amplifier. The amplifier will be disabled
when the signal at EN pin is above V
S
+ - 0.5V. If a TTL
signal is used to control the enabled/disabled function,
Figure 24 could be used to convert the TTL signal to CMOS
signal.
FIGURE 24.
Output Drive Capability
The EL5172 and EL5372 have internal short circuit
protection. Its typical short circuit current is 95mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds 60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5172 and
EL5372. It is possible to exceed the 135C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to:
T
JMAX
= Maximum junction temperature
T
AMAX
= Maximum ambient temperature
JA
= Thermal resistance of the package
Assume the REF pin is tired to GND for V
S
= 5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
For sourcing:
For sinking:
Where:
V
S
= Total supply voltage
I
SMAX
= Maximum quiescent supply current per channel
V
OUT
= Maximum output voltage of the application
R
LOAD
= Load resistance
I
LOAD
= Load current
i = Number of channels
By setting the two PD
MAX
equations equal to each other, we
can solve the output current and R
LOAD
to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the V
S
- pin is
connected to the ground plane, a single 4.7F tantalum
capacitor in parallel with a 0.1F ceramic capacitor from V
S
+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V
S
- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
1K
10K
5V
EN
CMOS/TTL
PD
MAX
T
JMAX
T
AMAX
JA
---------------------------------------------
=
PD
MAX
V
S
I
SMAX
V
S
+
(
V
OUT
)
V
OUT
R
LOAD
--------------------
i
+
=
PD
MAX
V
S
I
SMAX
V
OUT
(
V
S
-
)
I
LOAD
]
i
+
[
=
EL5172, EL5372
12
Typical Applications
FIGURE 25. TWISTED PAIR CABLE RECEIVER
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
FIGURE 26. COMPENSATED LINE RECEIVER
Level Shifter and Signal Summer
The EL5172 and EL5372 contains two pairs of differential
pair input stages. It makes the inputs are all high impedance
inputs. To take advantage of the two high impedance inputs,
the EL5172 and EL5372 can be used as a signal summer to
add two signals together. Like, one signal can be applied to
VIN+, the second signal can be applied to REF and V
IN
- is
ground. The output is equal to:
Also, the EL5172 and EL5372 can be used as a level shifter
by applying a level control signal to the REF input.
0
V
FB
V
INB
V
REF
EL5172/
EL5372
EL5173/
EL5373
or
EL5172/
EL5372
V
OUT
50
50
Z
O
= 100
V
IN
50
50
R
2
V
FB
V
INB
V
REF
EL5172/
EL5372
V
OUT
V
IN
50
50
R
1
R
3
C
1
Z
O
= 100
f
A
f
C
f
Gain
(dB)
1 + R
2
/ R
1
1 + R
2
/ (R
1
+ R
3
)
V
O
V
IN
(
+
V
REF
)
Gain
+
=
EL5172, EL5372
13
SO Package Outline Drawing
EL5172, EL5372
14
MSOP Package Outline Drawing
EL5172, EL5372
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
QSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
EL5172, EL5372
PDF 
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