Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a "controlled document". Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
2001 Elantec Semiconductor, Inc.
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General Description
The EL7562C is an integrated, synchronous step-down regulator with
output voltage adjustable from 1.0V to 3.8V. It is capable of delivering
2A continuous current at up to 95% efficiency. The EL7562C operates
at a constant frequency pulse width modulation (PWM) mode, making
external synchronization possible. Patented on-chip resistorless cur-
rent sensing enables current mode control, which provides cycle-by-
cycle current limiting, over-current protection, and excellent step load
response. The EL7562C is available in a fused-lead 16-pin QSOP
package. With proper external components, the whole converter fits
into a less than 0.5 in
2
area. The minimal external components and
small size make this EL7562C ideal for desktop and portable
applications.
The EL7562C is specified for operation over the -40C to +85C tem-
perature range.
Typical Application Diagram
Manufactured under U.S. Patent No. 57,323,974
1
2
3
4
16
15
14
13
5
6
7
12
11
10
8
9
SGND
COSC
VDD
PGND
PGND
VIN
VIN
EN
PGND
VREF
FB
VDRV
LX
LX
VHI
PGND
R
3
R
2
L
1
2.37k
C
3
C
4
C
1
C
2
C
5
R
1
C
6
C
7
V
O
(3.3V,
2A)
V
IN
(4.5V-
5.5V)
0.1F 270pF
39
100F 0.1F
0.1F
1k
0.1F
4.7F
100F
Features
Integrated synchronous MOSFETs
and current mode controller
2A continuous output current
Up to 95% efficiency
4.5V to 5.5V input voltage
Adjustable output from 1V to 3.8V
Cycle-by-cycle current limit
Precision reference
0.5% load and line regulation
Adjustable switching frequency to
1MHz
Oscillator synchronization
possible
Internal soft start
Over temperature protection
Under voltage lockout
16-pin QSOP package
Applications
DSP, CPU Core and IO Supplies
Logic/Bus Supplies
Portable Equipment
DC:DC Converter Modules
GTL + Bus Power Supply
Ordering Information
Part No
Package
Tape & Reel
Outline #
EL7562CU
16-Pin QSOP
-
MDP0040
EL7562C - Preliminary
Monolithic 2 Amp DC:DC Step-down Regulator
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Absolute Maximum Ratings
(T
A
= 25C)
Supply Voltage between V
IN
or V
DD
and GND
+6.5V
V
LX
Voltage
V
IN
+0.3V
Input Voltage
GND -0.3V, V
DD
+0.3V
V
HI
Voltage
GND -0.3V, V
LX
+6V
Storage Temperature
-65C to +150C
Operating Ambient Temperature
-40C to +85C
Operating Junction Temperature
+135C
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
.
DC Characteristics
V
DD
= V
IN
= 5V, T
A
= T
J
= 25C, C
OSC
= 1.2nF, unless otherwise specified.
Parameter
Description
Conditions
Min
Typ
Max
Unit
V
REF
Reference Accuracy
1.24
1.26
1.28
V
V
REFTC
Reference Temperature Coefficient
50
ppm/C
V
REFLOAD
Reference Load Regulation
0 < I
REF
< 50A
-1
%
V
RAMP
Oscillator Ramp Amplitude
1.15
V
I
OSC_CHG
Oscillator Charge Current
0.1V < V
OSC
< 1.25V
200
A
I
OSC_DIS
Oscillator Discharge Current
0.1V < V
OSC
< 1.25V
8
mA
I
VDD
+V
DRV
V
DD
+V
DRV
Supply Current
V
EN
= 4V, F
OSC
= 120kHz
2
3.5
5
mA
I
VDD_OFF
V
DD
Standby Current
EN = 0
1
1.5
mA
V
DD_OFF
V
DD
for Shutdown
3.5
3.9
V
V
DD_ON
V
DD
for Startup
3.95
4.35
V
T
OT
Over Temperature Threshold
135
C
T
HYS
Over Temperature Hysteresis
20
C
I
LEAK
Internal FET Leakage Current
EN = 0, L
X
= 5V (low FET), L
X
= 0V (high FET)
10
A
I
LMAX
Peak Current Limit
3
A
R
DSON
FET On Resistance
Wafer level test only
60
120
m
R
DSONTC
R
DSON
Tempco
0.2
m
/C
V
FB
Output Initial Accuracy
I
LOAD
= 0A
0.960
0.975
0.99
V
V
FB_LINE
Output Line Regulation
V
IN
= 5V,
V
IN
= 10%, I
LOAD
= 0A
0.5
%
V
FB_LOAD
Output Load Regulation
0.1A < I
LOAD
< 1A
0.5
%
V
FB_TC
Output Temperature Stability
-40C < T
A
< 85C, I
LOAD
= 0.5A
1
%
I
FB
Feedback Input Pull Up Current
V
FB
= 0V
100
200
nA
V
EN_HI
EN Input High Level
3.2
4
V
V
EN_LO
EN Input Low Level
1
V
I
EN
Enable Pull Up Current
V
EN
= 0
-4
-2.5
A
Closed Loop AC Electrical Characteristics
V
S
= V
IN
= 5V, T
A
= T
J
= 25C, C
OSC
= 1.2nF, unless otherwise specified.
Parameter
Description
Conditions
Min
Typ
Max
Unit
F
OSC
Oscillator Initial Accuracy
105
117
130
kHz
t
SYNC
Minimum Oscillator Sync Width
25
ns
M
SS
Soft Start Slope
0.5
V/ms
t
BRM
FET Break Before Make Delay
15
ns
t
LEB
High Side FET Minimum On Time
150
ns
D
MAX
Maximum Duty Cycle
95
%
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Pin Descriptions
Pin Number
Pin Name
Pin Function
1
SGND
Control circuit negative supply.
2
COSC
Oscillator timing capacitor. FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in F.
3
VDD
Control circuit positive supply.
4
PGND
Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET.
5
PGND
Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET.
6
VIN
Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET.
7
VIN
Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET.
8
EN
Chip Enable, active high. A 2A internal pull-up current enables the device if the pin is left open.
9
PGND
Ground return of the regulator.
10
VHI
Positive supply of the high-side driver.
11
LX
Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage.
12
LX
Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage.
13
VDRV
Positive supply of the low-side driver and input voltage for the high-side boot strap.
14
FB
Voltage feedback input. Connected to an external resistor divider between VOUT and GND. A 125nA pull-up current
forces VOUT to VS in the event that FB is floating.
15
VREF
Bandgap reference bypass capacitor. Typically 0.1F to GND.
16
PGND
Ground return of the regulator.
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Typical Performance Curves
Efficiency vs I
O
V
IN
=5V
100
95
90
85
80
75
70
65
60
0.1
1
2
Load Current I
O
(A)
E
f
f
i
c
i
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c
y
(
%
)
L=Coilcraft DO3316P-472
V
O
=2.5V
V
O
=1.8V
V
O
=1.5V
V
O
=1.2V
V
O
=3.3V
Power Loss vs I
O
V
IN
=5V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
Load Current I
O
(A)
P
o
w
e
r
L
o
s
s
(
W
)
Load Regulation
V
O
=3.3V
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
0.5
1
1.5
2
Load Current I
O
(A)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
%
)
V
REF
vs Temperature
1.258
1.256
1.254
1.252
1.25
1.248
1.246
1.244
1.242
-40
10
60
110
160
Temperature (C)
V
R
E
F
(
V
)
Efficiency vs I
O
V
O
=3.3V
100
95
90
85
80
75
70
65
60
0
0.5
1
1.5
2
Load Current I
O
(A)
E
f
f
i
c
i
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n
c
y
(
%
)
Line Regulation
V
O
=3.3V
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
4.5
4.7
5.1
5.3
5.5
V
IN
(V)
V
O
(
%
)
V
IN
=4.5V
V
IN
=5V
V
IN
=5.5V
V
IN
=4.5V
V
IN
=5V
V
IN
=5.5V
4.9
I
O
=0.1A
I
O
=1A
I
O
=2A
Power Loss vs I
O
V
IN
=5V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
Load Current I
O
(A)
P
o
w
e
r
L
o
s
s
(
W
)
V
O
=2.5V
V
O
=1.8V
V
O
=1.5V
V
O
=1.2V
V
O
=3.3V
F
S
=500kHz
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Typical Performance Curves
Oscillator Frequency vs Temperature
390
385
380
375
370
365
360
-40
10
60
110
160
Temperature (C)
O
s
c
i
l
l
a
t
o
r
F
r
e
q
u
e
n
c
y
(
k
H
z
)
Input Current vs Temperature
(Enable connected to GND)
0.96
0.94
0.92
0.88
0.86
0.84
0.82
0.8
-40
10
60
110
160
Temperature (C)
I
n
p
u
t
C
u
r
r
e
n
t
(
A
)
Switching Frequency vs C
OSC
1400
1200
1000
800
600
400
200
0
0
400
600
800
1000
C
OSC
(pF)
F
S
(
k
H
z
)
0.9
V
IN
=4.5V
V
IN
=5V
V
IN
=5.5V
200
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Block Diagram
Drivers
PWM
Controller
Current
Sense
Junction
Temperature
Voltage
Reference
Oscillator
0.1F
39
Controlle
r Supply
SGND
Power
Power
FET
FET
270pF
0.1F
0.1F
4.7H
V
OUT
2370
1k
100F
VREF
COSC
VHI
VIN
PGND
VDD
VDRV
FB
EN
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Applications Information
Circuit Description
General
The EL7562C is a fixed frequency, current mode con-
trolled DC:DC converter with integrated N-channel
power MOSFETs and a high precision reference. The
device incorporates all the active circuitry required to
implement a cost effective, user-programmable 2A syn-
chronous step-down regulator suitable for use in DSP
core power supplies.
Theory of Operation
The EL7562C is composed of 5 major blocks:
1. PWM Controller
2. NMOS Power FETs and Drive Circuitry
3. Bandgap Reference
4. Oscillator
5. Thermal Shut-down
PWM Controller
The EL7562C regulates output voltage through the use
of current-mode controlled pulse width modulation. The
three main elements in a PWM controller are the feed-
back loop and reference, a pulse width modulator whose
duty cycle is controlled by the feedback error signal, and
a filter which averages the logic level modulator output.
In a step-down (buck) converter, the feedback loop
forces the time-averaged output of the modulator to
equal the desired output voltage. Unlike pure voltage-
mode control systems, current-mode control utilizes
dual feedback loops to provide both output voltage and
inductor current information to the controller. The volt-
age loop minimizes DC and transient errors in the output
voltage by adjusting the PWM duty-cycle in response to
changes in line or load conditions. Since the output volt-
age is equal to the time-averaged of the modulator
output, the relatively large LC time constant found in
power supply applications generally results in low band-
width and poor transient response. By directly
monitoring changes in inductor current via a series sense
resistor the controller's response time is not entirely lim-
ited by the output LC filter and can react more quickly to
changes in line and load conditions. This feed-forward
characteristic also simplifies AC loop compensation
since it adds a zero to the overall loop response. Through
proper selection of the current-feedback to voltage-feed-
back ratio the overall loop response will approach a one-
pole system. The resulting system offers several advan-
tages over traditional voltage control systems, including
simpler loop compensation, pulse by pulse current limit-
ing, rapid response to line variation and good load step
response.
The heart of the controller is an input direct summing
comparator which sum voltage feedback, current feed-
back, slope compensation ramp and power tracking
signals together. Slope compensation is required to pre-
vent system instability that occurs in current-mode
topologies operating at duty-cycles greater than 50%
and is also used to define the open-loop gain of the over-
all system. The slope compensation is fixed internally
and optimized for 500mA inductor ripple current. The
power tracking will not contribute any input to the com-
parator steady-state operation. Current feedback is
measured by the patented sensing scheme that senses the
inductor current flowing through the high-side switch
whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned
on. The comparator inputs are gated off for a minimum
period of time of about 150ns (LEB) after the high-side
switch is turned on to allow the system to settle. The
Leading Edge Blanking (LEB) period prevents the
detection of erroneous voltages at the comparator inputs
due to switching noise. If the inductor current exceeds
the maximum current limit (ILMAX) a secondary over-
current comparator will terminate the high-side switch
on time. If ILMAX has not been reached, the feedback
voltage FB derived from the regulator output voltage
VOUT is then compared to the internal feedback refer-
ence voltage. The resultant error voltage is summed with
the current feedback and slope compensation ramp. The
high-side switch remains on until all four comparator
inputs have summed to zero, at which time the high-side
switch is turned off and the low-side switch is turned on.
However, the maximum on-duty ratio of the high-side
switch is limited to 95%. In order to eliminate cross-con-
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duction of the high-side and low-side switches a 15ns
break-before-make delay is incorporated in the switch
drive circuitry. The output enable (EN) input allows the
regulator output to be disabled by an external logic con-
trol signal.
Output Voltage Setting
In general:
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and
loop-gain is changed. This is shown in the performance
curves. A 100nA pull-up current from FB to VDD forces
VOUT to GND in the event that FB is floating.
NMOS Power FETs and Drive Circuitry
The EL7562C integrates low on-resistance (60m
)
NMOS FETs to achieve high efficiency at 2A. In order
to use an NMOS switch for the high-side drive it is nec-
essary to drive the gate voltage above the source voltage
(LX). This is accomplished by bootstrapping the VHI
pin above the LX voltage with an external capacitor
CVHI and internal switch and diode. When the low-side
switch is turned on and the LX voltage is close to GND
potential, capacitor CVHI is charged through internal
switch to VDRV, typically 5V. At the beginning of the
next cycle the high-side switch turns on and the LX pins
begin to rise from GND to VIN potential. As the LX pin
rises the positive plate of capacitor CVHI follows and
eventually reaches a value of VDRV+VIN, typically
10V, for VDRV=VIN=5V. This voltage is then level
shifted and used to drive the gate of the high-side FET,
via the VHI pin. A value of 0.1F for CVHI is
recommended.
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7562C. The external VREF capaci-
tor acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection.
A value of 0.1F is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately
95%. Operating frequency can be adjusted through the
COSC pin or can be driven by an external source. If the
oscillator is driven by an external source care must be
taken in selecting the ramp amplitude. Since CSLOPE
value is derived from the COSC ramp, changes to COSC
ramp will change the CSLOPE compensation ramp
which determine the open-loop gain of the system.
When external synchronization is required, always
choose C
OSC
such that the free-running frequency is at
least 20% lower than that of sync source to accommo-
date component and temperature variations. Figure 1
shows a typical connection.
Thermal Shut-down
An internal temperature sensor continuously monitors
die temperature. In the event that die temperature
exceeds the thermal trip-point, the system is in fault state
and will be shut down. The upper and low trip-points are
set to 135C and 115C respectively.
VOUT
0.975V
1
R2
R1
------
+
=
Figure 1. Oscillator Synchronization
2
3
11
10
9
6
7
8
15
14
EL7562C
1
16
External
Oscillator
BAT54S
100pF
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Start-up Delay
A capacitor can be added to the EN pin to delay the con-
verter start-up (Figure 2) by utilizing the pull-up current.
The delay time is approximately:
Layout Considerations
The layout is very important for the converter to func-
tion properly. Power Ground ( ) and Signal Ground (
---
)
should be separated to ensure that the high pulse current
in the Power Ground never interferes with the sensitive
signals connected to Signal Ground. They should only
be connected at one point (normally at the negative side
of either the input or output capacitor.)
The trace connected to pin 14 (FB) is the most sensitive
trace. It needs to be as short as possible and in a "quiet"
place, preferably between PGND or SGND traces.
In addition, the bypass capacitor connected to the VDD
pin needs to be as close to the pin as possible.
The heat of the chip is mainly dissipated through the
PGND pins. Maximizing the copper area around these
pins is preferable. In addition, a solid ground plane is
always helpful for the EMI performance.
The demo board is a good example of layout based on
these principles. Please refer to the EL7562C Applica-
tion Brief for the layout.
td ms
(
)
1200 C
F
(
)
=
Figure 2. Start-up Delay
TIME
V
O
V
IN
t
d
V
OUT
C
2
3
11
10
9
6
7
8
15
14
EL7562C
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General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.'s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
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Printed in U.S.A.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
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