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Электронный компонент: EBD11UD8ADDA

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Document No. E0431E20 (Ver. 2.0)
Date Published April 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2004
DATA SHEET
1GB DDR SDRAM SO-DIMM
EBD11UD8ADDA
(128M words



64 bits, 2 Ranks)
Description
The EBD11UD8ADDA is 128M words
64 bits, 2
ranks Double Data Rate (DDR) SDRAM Small Outline
Dual In-line Memory Module, mounting 16 pieces of
512M bits DDR SDRAM sealed in TCP package. Read
and write operations are performed at the cross points
of the CK and the /CK. This high-speed data transfer
is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TCP on the module board.

Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs and DM are synchronized with
DQS
4 internal banks for concurrent operation
(Components)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
EBD11UD8ADDA
Data Sheet E0431E20 (Ver. 2.0)
2
Ordering Information

Part number
Data rate
Mbps (max.)
Component JEDEC speed bin
(CL-tRCD-tRP)

Package
Contact
pad

Mounted devices
EBD11UD8ADDA-6B
EBD11UD8ADDA-7A
EBD11UD8ADDA-7B
333
266
266
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
200-pin
SO-DIMM
Gold
512M bits DDR
SDRAM TCP*
1
Note: 1. Please refer to 512Mb DDR TSOP product datasheet (E0384E) for electrical characteristics.
Pin Configurations
1 pin
2 pin
Front side
Back side
39 pin
40 pin
41 pin
42 pin
199 pin
200 pin
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VREF 51
VSS 2
VREF 52
VSS
3 VSS 53 DQ19 4
VSS 54 DQ23
5 DQ0 55 DQ24 6
DQ4 56 DQ28
7 DQ1 57 VDD 8
DQ5 58 VDD
9 VDD
59 DQ25
10 VDD
60 DQ29
11
DQS0
61 DQS3
12 DM0
62 DM3
13
DQ2
63 VSS
14 DQ6
64 VSS
15
VSS
65 DQ26
16 VSS
66 DQ30
17
DQ3
67 DQ27
18 DQ7
68 DQ31
19
DQ8
69 VDD
20 DQ12
70 VDD
21
VDD
71 NC 22 VDD
72 NC
23
DQ9
73 NC 24 DQ13
74 NC
25
DQS1
75 VSS
26 DM1
76 VSS
27
VSS
77 NC 28 VSS
78 NC
29
DQ10
79 NC 30 DQ14
80 NC
31
DQ11
81 VDD
32 DQ15
82 VDD
33
VDD
83 NC 34 VDD
84 NC
35
CK0
85 NC 36 VDD
86 NC
37
/CK0
87 VSS
38 VSS
88 VSS
39
VSS
89 CK2
40 VSS
90 VSS
41
DQ16
91 /CK2
42 DQ20
92 VDD
43
DQ17
93 VDD
44 DQ21
94 VDD
45
VDD
95 CKE1
46 VDD
96 CKE0
47
DQS2
97 NC 48 DM2
98 NC
49
DQ18
99 A12 50 DQ22
100 A11


EBD11UD8ADDA
Data Sheet E0431E20 (Ver. 2.0)
3
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
101 A9 151 DQ42
102 A8 152 DQ46
103 VSS 153 DQ43
104 VSS 154 DQ47
105 A7 155 VDD 106 A6 156 VDD
107 A5 157 VDD 108 A4 158 /CK1
109 A3 159 VSS 110 A2 160 CK1
111 A1 161 VSS 112 A0 162 VSS
113 VDD 163 DQ48
114 VDD 164 DQ52
115 A10/AP
165 DQ49
116 BA1 166 DQ53
117 BA0 167 VDD 118 /RAS
168 VDD
119 /WE 169 DQS6
120 /CAS
170 DM6
121 /CS0
171 DQ50
122 /CS1
172 DQ54
123 NC 173 VSS 124 NC 174 VSS
125 VSS 175 DQ51
126 VSS 176 DQ55
127 DQ32 177 DQ56 128 DQ36 178 DQ60
129 DQ33
179 VDD 130 DQ37
180 VDD
131 VDD 181 DQ57
132 VDD 182 DQ61
133 DQS4 183 DQS7 134 DM4 184 DM7
135 DQ34
185 VSS 136 DQ38
186 VSS
137 VSS 187 DQ58
138 VSS 188 DQ62
139 DQ35 189 DQ59 140 DQ39 190 DQ63
141 DQ40
191 VDD 142 DQ44
192 VDD
143 VDD 193 SDA 144 VDD 194 SA0
145 DQ41
195 SCL 146 DQ45
196 SA1
147 DQS5
197 VDDSPD
148 DM5 198 SA2
149 VSS 199 VDDID
150 VSS 200 NC
EBD11UD8ADDA
Data Sheet E0431E20 (Ver. 2.0)
4
Pin Description
Pin name
Function
A0 to A12
Address input
Row address
A0 to A12
Column address
A0 to A9, A11
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE Write
enable
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0 to CK2
Clock input
/CK0 to /CK2
Differential clock input
DQS0 to DQS7
Input and output data strobe
DM0 to DM7
Input mask
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0 to SA2
Serial address input
VDD Power
for
internal
circuit
VDDSPD
Power for serial EEPROM
VREF Input
reference
voltage
VSS Ground
VDDID VDD
identification
flag
NC No
connection
EBD11UD8ADDA
Data Sheet E0431E20 (Ver. 2.0)
5
Serial PD Matrix
Byte
No. Function
described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex
value Comments
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
128
bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256
bytes
2
Memory
type
0 0 0 0 0 1 1 1 07H
DDR
SDRAM
3
Number
of
row
address
0 0 0 0 1 1 0 1 0DH
13
4
Number
of
column
address
0 0 0 0 1 0 1 1 0BH
11
5
Number
of
DIMM
ranks
0 0 0 0 0 0 1 0 02H
2
6
Module
data
width
0 1 0 0 0 0 0 0 40H
64
bits
7
Module
data
width
continuation
0 0 0 0 0 0 0 0 00H
0
8
Voltage
interface
level
of
this
assembly
0 0 0 0 0 1 0 0 04H
SSTL2.5V
9
DDR SDRAM cycle time, CL = X
-6B
0 1 1 0 0 0 0 0 60H
CL
=
2.5*
1
-7A,-7B
0 1 1 1 0 1 0 1 75H
10
SDRAM access from clock (tAC)
-6B
0 1 1 1 0 0 0 0 70H
0.70ns*
1
-7A,
-7B
0 1 1 1 0 1 0 1 75H
0.75ns*
1
11
DIMM
configuration
type
0 0 0 0 0 0 0 0 00H
None
12
Refresh
rate/type
1 0 0 0 0 0 1 0 82H
7.6
s
Self refresh
13
Primary
SDRAM
width
0 0 0 0 1 0 0 0 08H
8
14
Error
checking
SDRAM
width
0 0 0 0 0 0 0 0 00H
Not
used
15
SDRAM device attributes:
Minimum clock delay back-to-back
column access
0 0 0 0 0 0 0 1 01H
1
CLK
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
2,4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0 0 0 0 0 1 0 0 04H
4
18
SDRAM
device
attributes:
/CAS
latency
0 0 0 0 1 1 0 0 0CH
2,
2.5
19
SDRAM
device
attributes:
/CS
latency
0 0 0 0 0 0 0 1 01H
0
20
SDRAM
device
attributes:
/WE
latency
0 0 0 0 0 0 1 0 02H
1
21
SDRAM
module
attributes
0 0 1 0 0 0 0 0 20H
Unbuffered
22
SDRAM
device
attributes:
General 1 1 0 0 0 0 0 0 C0H
VDD
0.2V
23
Minimum clock cycle time at
CL = X 0.5
-6B, -7A
0 1 1 1 0 1 0 1 75H
CL
=
2*
1
-7B
1 0 1 0 0 0 0 0 A0H
24
Maximum data access time (tAC) from
clock at CL = X 0.5
-6B
0 1 1 1 0 0 0 0 70H
0.70ns*
1
-7A,
-7B
0 1 1 1 0 1 0 1 75H
0.75ns*
1
25
to
26
0 0 0 0 0 0 0 0 00H
27
Minimum row precharge time (tRP)
-6B
0 1 0 0 1 0 0 0 48H
18ns
-7A,
-7B
0 1 0 1 0 0 0 0 50H
20ns