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Электронный компонент: EBD21RD4ABNA

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Document No. E0273E20 (Ver. 2.0)
Date Published
Aug 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
PRELIMINARY DATA SHEET
2GB Registered DDR SDRAM DIMM
EBD21RD4ABNA
(256M words



72 bits, 2 Banks)
Description
The EBD21RD4ABNA is a 256M words
72 bits, 2
bank Double Data Rate (DDR) SDRAM Module,
mounted 36 pieces of DDR SDRAM sealed in TCP
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2-bit prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each TCP
on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 266Mbps/200Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
LL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 1 piece of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
EBD21RD4ABNA
Preliminary Data Sheet E0273E20 (Ver. 2.0)
2
Ordering Information

Part number
Data rate
Mbps (max.)
Component JEDEC speed bin*
1
(CL-tRCD-tRP)

Package
Contact
pad

Mounted devices
EBD21RD4ABNA-7A
EBD21RD4ABNA-7B
EBD21RD4ABNA-10
266
266
200
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
184-pin
DIMM
Gold
512M bits DDR
SDRAM TCP*
2
Notes: 1. Module /CAS latency = component CL + 1
2. Please refer to 512Mb DDR TSOP product datasheet (E0237E) for electrical characteristics.
Pin Configurations
1 pin
Front side
Back side
52 pin 53 pin
92 pin
93 pin
144 pin 145 pin 184 pin
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VREF
47
DQS8
93
VSS
139
VSS
2
DQ0
48
A0
94
DQ4
140
DM8/DQS17
3
VSS
49
CB2
95
DQ5
141
A10
4
DQ1
50
VSS
96
VDDQ
142
CB6
5
DQS0
51
CB3
97
DM0/DQS9
143
VDDQ
6
DQ2
52
BA1
98
DQ6
144
CB7
7
VDD
53
DQ32
99
DQ7
145
VSS
8
DQ3
54
VDDQ
100
VSS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
/RESET
56
DQS4
102
NC
148
VDD
11
VSS
57
DQ34
103
NC
149
DM4/DQS13
12
DQ8
58
VSS
104
VDDQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
VSS
15
VDDQ
61
DQ40
107
DM1/DQS10
153
DQ44
16
NC
62
VDDQ
108
VDD
154
/RAS
17
NC
63
/WE
109
DQ14
155
DQ45
18
VSS
64
DQ41
110
DQ15
156
VDDQ
19
DQ10
65
/CAS
111
CKE1
157
/CS0
20
DQ11
66
VSS
112
VDDQ
158
/CS1
21
CKE0
67
DQS5
113
NC
159
DM5/DQS14
22
VDDQ
68
DQ42
114
DQ20
160
VSS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
VDD
116
VSS
162
DQ47
25
DQS2
71
NC
117
DQ21
163
NC
26
VSS
72
DQ48
118
A11
164
VDDQ
27
A9
73
DQ49
119
DM2/DQS11
165
DQ52
28
DQ18
74
VSS
120
VDD
166
DQ53
EBD21RD4ABNA
Preliminary Data Sheet E0273E20 (Ver. 2.0)
3
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
29
A7
75
NC
121
DQ22
167
NC
30
VDDQ
76
NC
122
A8
168
VDD
31
DQ19
77
VDDQ
123
DQ23
169
DM6/DQS15
32
A5
78
DQS6
124
VSS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
VSS
80
DQ51
126
DQ28
172
VDDQ
35
DQ25
81
VSS
127
DQ29
173
NC
36
DQS3
82
VDDID
128
VDDQ
174
DQ60
37
A4
83
DQ56
129
DM3/DQS12
175
DQ61
38
VDD
84
DQ57
130
A3
176
VSS
39
DQ26
85
VDD
131
DQ30
177
DM7/DQS16
40
DQ27
86
DQS7
132
VSS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
VSS
88
DQ59
134
CB4
180
VDDQ
43
A1
89
VSS
135
CB5
181
SA0
44
CB0
90
NC
136
VDDQ
182
SA1
45
CB1
91
SDA
137
CK0
183
SA2
46
VDD
92
SCL
138
/CK0
184
VDDSPD
EBD21RD4ABNA
Preliminary Data Sheet E0273E20 (Ver. 2.0)
4
Pin Description
Pin name
Function
A0 to A12
Address input
Row address
A0 to A12
Column address
A0 to A9, A11, A12
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE
Write enable
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0
Clock input
/CK0
Differential clock input
DQS0 to DQS8
Input and output data strobe
DM0 to DM8/DQS9 to DQS17
Input and output data strobe
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0 to SA2
Serial address input
VDD
Power for internal circuit
VDDQ
Power for DQ circuit
VDDSPD
Power for serial EEPROM
VREF
Input reference voltage
VSS
Ground
VDDID
VDD identification flag
/RESET
Reset pin (forces register inputs low)
NC
No connection
EBD21RD4ABNA
Preliminary Data Sheet E0273E20 (Ver. 2.0)
5
Serial PD Matrix*
1
Byte No.
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128
1
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
256 byte
2
Memory type
0
0
0
0
0
1
1
1
07H
SDRAM DDR
3
Number of row address
0
0
0
0
1
1
0
1
0DH
13
4
Number of column address
0
0
0
0
1
1
0
0
0CH
12
5
Number of DIMM banks
0
0
0
0
0
0
1
0
02H
2
6
Module data width
0
1
0
0
1
0
0
0
48H
72 bits
7
Module data width continuation
0
0
0
0
0
0
0
0
00H
0 (+)
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
0
04H
SSTL 2.5V
9
DDR SDRAM cycle time, CL = X
-7A, -7B
0
1
1
1
0
1
0
1
75H
CL = 2.5*
3
-10
1
0
1
0
0
0
0
0
A0H
10
SDRAM access from clock (tAC)
-7A, -7B
0
1
1
1
0
1
0
1
75H
0.75ns*
3
-10
1
0
0
0
0
0
0
0
80H
0.8ns*
3
11
DIMM configuration type
0
0
0
0
0
0
1
0
02H
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
7.8 s
Self refresh
13
Primary SDRAM width
0
0
0
0
0
1
0
0
04H
4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04H
4
15
SDRAM device attributes:
Minimum clock delay back-to-back
column access
0
0
0
0
0
0
0
1
01H
1 CLK
16
SDRAM device attributes:
Burst length supported
0
0
0
0
1
1
1
0
0EH
2, 4, 8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
4
18
SDRAM device attributes:
/CAS latency
0
0
0
0
1
1
0
0
0CH
2, 2.5
19
SDRAM device attributes:
/CS latency
0
0
0
0
0
0
0
1
01H
0
20
SDRAM device attributes:
/WE latency
0
0
0
0
0
0
1
0
02H
1
21
SDRAM module attributes
0
0
1
0
0
1
1
0
26H
Registered
22
SDRAM device attributes: General
1
1
0
0
0
0
0
0
C0H
0.2V
23
Minimum clock cycle time at CLX - 0.5
-7A
0
1
1
1
0
1
0
1
75H
CL = 2*
3
-7B, -10
1
0
1
0
0
0
0
0
A0H
24
Maximum data access time (tAC) from
clock at CLX - 0.5
-7A, -7B
0
1
1
1
0
1
0
1
75H
0.75ns*
3
-10
1
0
0
0
0
0
0
0
80H
0.8ns*
3
25
Minimum clock cycle time at CLX - 1
0
0
0
0
0
0
0
0
00H
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00H
27
Minimum row precharge time (tRP)
0
1
0
1
0
0
0
0
50H
20ns
28
Minimum row active to row active
delay (tRRD)
0
0
1
1
1
1
0
0
3CH
15ns
29
Minimum /RAS to /CAS delay (tRCD) 0
1
0
1
0
0
0
0
50H
20ns