Document Outline
- COVER
- Description
- Features
- Ordering Information
- Pin Configurations
- Pin Description
- Serial PD Matrix
- Block Diagram
- Electrical Specifications
- Absolute Maximum Ratings
- DC Operating Conditions
- DC Characteristics 1
- AC Timing for IDD Test Conditions
- DC Characteristics 2
- DC Characteristics 3
- ODT DC Electrical Characteristics
- OCD Default Characteristics
- Pin Capacitance
- AC Characteristics
- ODT AC Electrical Characteristics
- Pin Functions
- Detailed Operation Part and Timing Waveforms
- Physical Outline
Document No. E0827E10 (Ver. 1.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
DATA SHEET
1GB DDR2 SDRAM SO-DIMM
EBE11UD8AGSA (128M words
64 bits, 2 Ranks)
Description
The EBE11UD8AGSA is 128M words
64 bits, 2 ranks
DDR2 SDRAM Small Outline Dual In-line Memory
Module, mounting 16 pieces of 512M bits DDR2
SDRAM sealed in FBGA (
BGA
) package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 4 bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write
are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology. Decoupling
capacitors are mounted beside each FBGA (
BGA) on
the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
Power supply: VDD
=
1.8V
0.1V
Data rate: 667Mbps/533Mbps (max.)
SSTL_18 compatible I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(components)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8
s at 0
C
TC
+
85
C
3.9
s at
+
85
C
<
TC
+
95
C
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
EBE11UD8AGSA
Data Sheet E0827E10 (Ver. 1.0)
2
Ordering Information
Part number
Data rate
Mbps (max.)
Component
JEDEC speed bin
(CL-tRCD-tRP)
Package
Contact
pad
Mounted devices
EBE11UD8AGSA-6E-E 667
DDR2-667 (5-5-5)
200-pin SO-DIMM
(lead-free)
Gold EDE5108AGSE-6E-E
EBE11UD8AGSA-5C-E 533
DDR2-533 (4-4-4)
EDE5108AGSE-6E-E
EDE5108AGSE-5C-E
Pin Configurations
1 pin
2 pin
Front side
Back side
39 pin
40 pin
41 pin
42 pin
199 pin
200 pin
Front side
Back side
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1 VREF
51 DQS2
2 VSS
52 DM2
3 VSS
53 VSS
4 DQ4
54 VSS
5 DQ0
55 DQ18
6 DQ5
56 DQ22
7 DQ1
57 DQ19
8 VSS
58 DQ23
9 VSS
59 VSS
10 DM0
60 VSS
11
/DQS0
61 DQ24
12 VSS
62 DQ28
13
DQS0
63 DQ25
14 DQ6
64 DQ29
15
VSS
65 VSS
16 DQ7
66 VSS
17
DQ2
67 DM3
18 VSS
68 /DQS3
19
DQ3
69 NC 20 DQ12
70 DQS3
21
VSS
71 VSS
22 DQ13
72 VSS
23
DQ8
73 DQ26
24 VSS
74 DQ30
25
DQ9
75 DQ27
26 DM1
76 DQ31
27 VSS 77 VSS 28 VSS 78 VSS
29
/DQS1
79 CKE0
30 CK0
80 CKE1
31
DQS1
81 VDD
32 /CK0
82 VDD
33
VSS
83 NC 34 VSS
84 NC
35
DQ10
85 NC 36 DQ14
86 NC
37
DQ11
87 VDD
38 DQ15
88 VDD
39
VSS
89 A12
40 VSS
90 A11
41
VSS
91 A9 42 VSS
92 A7
43
DQ16
93 A8 44 DQ20
94 A6
45
DQ17
95 VDD
46 DQ21
96 VDD
47
VSS
97 A5 48 VSS
98 A4
49 /DQS2
99 A3 50 NC 100 A2
EBE11UD8AGSA
Data Sheet E0827E10 (Ver. 1.0)
3
Front side
Back side
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
101 A1
151 DQ42 102 A0
152 DQ46
103 VDD 153 DQ43 104 VDD 154 DQ47
105 A10/AP
155 VSS 106 BA1 156 VSS
107 BA0 157 DQ48 108 /RAS 158 DQ52
109 /WE 159 DQ49 110 /CS0 160 DQ53
111 VDD 161 VSS 112 VDD 162 VSS
113 /CAS 163 NC
114 ODT0 164 CK1
115 /CS1 165 VSS 116 A13 166 /CK1
117 VDD 167 /DQS6 118 VDD 168 VSS
119 ODT1 169 DQS6 120 NC
170 DM6
121
VSS 171 VSS 122 VSS 172 VSS
123 DQ32 173 DQ50 124 DQ36 174 DQ54
125 DQ33 175 DQ51 126 DQ37 176 DQ55
127
VSS 177 VSS 128 VSS 178 VSS
129 /DQS4 179 DQ56 130 DM4 180 DQ60
131 DQS4 181 DQ57 132 VSS 182 DQ61
133 VSS 183 VSS 134 DQ38 184 VSS
135 DQ34 185 DM7 136 DQ39 186 /DQS7
137
DQ35
187 VSS 138 VSS 188 DQS7
139 VSS 189 DQ58 140 DQ44 190 VSS
141 DQ40 191 DQ59 142 DQ45 192 DQ62
143
DQ41
193 VSS 144 VSS 194 DQ63
145 VSS 195 SDA 146 /DQS5 196 VSS
147 DM5 197 SCL 148 DQS5 198 SA0
149 VSS 199 VDDSPD
150 VSS 200 SA1
EBE11UD8AGSA
Data Sheet E0827E10 (Ver. 1.0)
4
Pin Description
Pin name
Function
A0 to A13
Address input
Row address
A0 to A13
Column address
A0 to A9
A10 (AP)
Auto precharge
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE Write
enable
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0, CK1
Clock input
/CK0, /CK1
Differential clock input
DQS0 to DQS7, /DQS0 to /DQS7
Input and output data strobe
DM0 to DM7
Input mask
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0, SA1
Serial address input
VDD
Power for internal circuit
VDDSPD
Power for serial EEPROM
VREF
Input reference voltage
VSS Ground
ODT0, ODT1
ODT control
NC No
connection
EBE11UD8AGSA
Data Sheet E0827E10 (Ver. 1.0)
5
Serial PD Matrix
Byte No.
Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
value
Comments
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H 128
bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H 256
bytes
2
Memory
type
0 0 0 0 1 0 0 0 08H DDR2
SDRAM
3
Number
of
row
address
0 0 0 0 1 1 1 0 0EH 14
4
Number
of
column
address
0 0 0 0 1 0 1 0 0AH 10
5
Number
of
DIMM
ranks
0 1 1 0 0 0 0 1 61H 2
6
Module
data
width
0 1 0 0 0 0 0 0 40H 64
7
Module
data
width
continuation
0 0 0 0 0 0 0 0 00H 0
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
1
05H
SSTL 1.8V
9
DDR SDRAM cycle time, CL = 5
-6E
0 0 1 1 0 0 0 0 30H 3.0ns*
1
-5C
0 0 1 1 1 1 0 1 3DH 3.75ns*
1
10
SDRAM access from clock (tAC)
-6E
0 1 0 0 0 1 0 1 45H 0.45ns*
1
-5C
0 1 0 1 0 0 0 0 50H 0.5ns*
1
11
DIMM
configuration
type
0 0 0 0 0 0 0 0 00H None.
12
Refresh
rate/type
1 0 0 0 0 0 1 0 82H 7.8
s
13
Primary
SDRAM
width
0 0 0 0 1 0 0 0 08H
8
14
Error
checking
SDRAM
width
0 0 0 0 0 0 0 0 00H None.
15
Reserved
0 0 0 0 0 0 0 0 00H 0
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH 4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0 0 0 0 0 1 0 0 04H 4
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H 3,
4,
5
19
DIMM
Mechanical
Characteristics 0 0 0 0 0 0 0 1 01H 3.80mm
max.
20
DIMM
type
information
0 0 0 0 0 1 0 0 04H SO-DIMM
21
SDRAM
module
attributes
0 0 0 0 0 0 0 0 00H Normal
22
SDRAM device attributes: General
0
0
0
0
0
0
1
1
03H
Weak Driver
50
ODT Support
23
Minimum clock cycle time at CL = 4
0
0
1
1
1
1
0
1
3DH
3.75ns*
1
24
Maximum data access time (tAC) from
clock at CL = 4
0 1 0 1 0 0 0 0 50H 0.5ns*
1
25
Minimum clock cycle time at CL = 3
0
1
0
1
0
0
0
0
50H
5.0ns*
1
26
Maximum data access time (tAC) from
clock at CL = 3
0 1 1 0 0 0 0 0 60H 0.6ns*
1
27
Minimum row precharge time (tRP)
0
0
1
1
1
1
0
0
3CH
15ns
28
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH 7.5ns
29
Minimum /RAS to /CAS delay (tRCD) 0
0
1
1
1
1
0
0
3CH
15ns
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH 45ns
31
Module
rank
density
1 0 0 0 0 0 0 0 80H 512M
bytes
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