Document Outline
- COVER
- Description
- Features
- Ordering Information
- Pin Configurations
- Pin Description
- Serial PD Matrix
- Block Diagram
- Electrical Specifications
- Absolute Maximum Ratings
- DC Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- Test Conditions
- Relationship Between Frequency and Minimum Latency
- Pin Functions
- Detailed Operation Part
- Physical Outline
Document No. E0105E50 (Ver. 5.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
DATA SHEET
2GB Registered SDRAM DIMM
EBS21RC2ACNA (256M words
72 bits, 2 banks)
Description
The EBS21RC2ACNA is 256M words
72 bits, 2
banks Synchronous Dynamic RAM Registered Module,
mounted 72 pieces of 256M bits SDRAM sealed in
TCP package. This module provides high density and
large quantities of memory in a small space without
utilizing the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
Fully compatible with 8 bytes DIMM: JEDEC
standard outline
168-pin socket type dual in line memory module
(DIMM)
PCB height: 41.91mm (1.65inch )
Lead pitch: 1.27mm
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Data bus width:
72 ECC
Single pulsed /RAS
4 Banks can operates simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8
2 variations of burst sequence
Sequential
Interleave
Programmable /CAS latency (CL): 2, 3
Registered inputs with one clock delay
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 3 pieces of register driver
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (SPD) on PCB.
EBS21RC2ACNA
Data Sheet E0105E50 (Ver. 5.0)
2
Ordering Information
Part number
Clock frequency
MHz (max.)
/CAS latency
Package
Contact pad
Mounted devices
EBS21RC2ACNA-7A
EBS21RC2ACNA-75*
1
133
133
2, 3
3
168-pin DIMM
Gold
256M bits SDRAM
TCP*
2
Note: 1. 100MHz operation at /CAS latency = 2.
2. Please refer to the TSOP products EDS25XXACTA datasheet (E0277E) for detail information.
Pin Configurations
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
/CS2
87
DQ33
129
/CS3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
NC
90
VDD
132
NC
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
VDD
68
VSS
110
VDD
152
VSS
27
/WE
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
EBS21RC2ACNA
Data Sheet E0105E50 (Ver. 5.0)
3
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
30
/CS0
72
DQ27
114
/CS1
156
DQ59
31
NC
73
VDD
115
/RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CLK2
121
A9
163
CLK3
38
A10 (AP)
80
NC
122
BA0
164
NC
39
BA1
81
NC
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
VDD
83
SCL
125
CLK1
167
SA2
42
CLK0
84
VDD
126
A12
168
VDD
Pin Description
Pin name
Function
A0 to A12
Address input
Row address
A0 to A12
Column address A0 to A9, A11, A12
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
/CS0 to /CS3
Chip select input
/RAS
Row enable (/RAS) input
/CAS
Column enable (/CAS) input
/WE
Write enable input
DQMB0 to DQMB7
Byte data mask
CLK0 to CLK3
Clock input
CKE0
Clock enable input
REGE*
1
Register/Buffer enable
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
SA0 to SA2
Serial address input
VDD
Primary positive power supply
VSS
Ground
NC
No connection
Note: 1. REGE
VIH: Register mode.
REGE
VIL: Buffer mode.
EBS21RC2ACNA
Data Sheet E0105E50 (Ver. 5.0)
4
Serial PD Matrix*
1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0
Number of bytes used by module
manufacturer
1
0
0
0
0
0
0
0
80H
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08H
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04H
SDRAM
3
Number of row addresses bits
0
0
0
0
1
1
0
1
0DH
13
4
Number of column addresses bits
0
0
0
0
1
1
0
0
0CH
12
5
Number of banks
0
0
0
0
0
0
1
0
02H
2
6
Module data width
0
1
0
0
1
0
0
0
48H
72 bit
7
Module data width (continued)
0
0
0
0
0
0
0
0
00H
0 (+)
8
Module interface signal levels
0
0
0
0
0
0
0
1
01H
LVTTL
9
SDRAM cycle time
(highest /CAS latency)
7.5ns
0
1
1
1
0
1
0
1
75H
CL = 3*
5
10
SDRAM access from Clock
(highest /CAS latency)
5.4ns
0
1
0
1
0
1
0
0
54H
11
Module configuration type
0
0
0
0
0
0
1
0
02H
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
Normal
(7.8125 s)
Self refresh
13
SDRAM width
0
0
0
0
0
0
1
0
02H
128M
2
14
Error checking SDRAM width
0
0
0
0
0
0
1
0
02H
2
15
SDRAM device attributes:
minimum clock delay for back-to-
back random column addresses
0
0
0
0
0
0
0
1
01H
1 CLK
16
SDRAM device attributes:
Burst lengths supported
0
0
0
0
1
1
1
1
0FH
1, 2, 4, 8
17
SDRAM device attributes: number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
4
18
SDRAM device attributes:
/CAS latency
0
0
0
0
0
1
1
0
06H
2, 3
19
SDRAM device attributes:
/CS latency
0
0
0
0
0
0
0
1
01H
0
20
SDRAM device attributes:
/WE latency
0
0
0
0
0
0
0
1
01H
0
21
SDRAM device attributes
0
0
0
1
1
1
1
1
1FH
Registered
22
SDRAM device attributes: General
0
0
0
0
1
1
1
0
0EH
VDD 10%
23
SDRAM cycle time
(2nd highest /CAS latency)
(-7A) 7.5ns
0
1
1
1
0
1
0
1
75H
CL = 2*
5
(-75) 10ns
1
0
1
0
0
0
0
0
A0H
24
SDRAM access from Clock
(2nd highest /CAS latency)
(-7A)5.4ns
0
1
0
1
0
1
0
0
54H
(-75) 6ns
0
1
1
0
0
0
0
0
60H
25
SDRAM cycle time
(3rd highest /CAS latency)
Undefined
0
0
0
0
0
0
0
0
00H
26
SDRAM access from Clock (3rd
highest /CAS latency)
Undefined
0
0
0
0
0
0
0
0
00H
EBS21RC2ACNA
Data Sheet E0105E50 (Ver. 5.0)
5
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
27
Minimum row precharge time
(-7A)
0
0
0
0
1
1
1
1
0FH
15ns
(-75)
0
0
0
1
0
1
0
0
14H
20ns
28
Row active to row active min
0
0
0
0
1
1
1
1
0FH
15ns
29
/RAS to /CAS delay min
(-7A)
0
0
0
0
1
1
1
1
0FH
15ns
(-75)
0
0
0
1
0
1
0
0
14H
20ns
30
Minimum /RAS pulse width
0
0
1
0
1
1
0
1
2DH
45ns
31
Density of each bank on module
0
0
0
0
0
0
0
1
01H
2 bank
1G byte
32
Address and command signal input
setup time
0
0
0
1
0
1
0
1
15H
1.5ns*
5
33
Address and command signal input
hold time
0
0
0
0
1
0
0
0
08H
0.8ns*
5
34
Data signal input setup time
0
0
0
1
0
1
0
1
15H
1.5ns*
5
35
Data signal input hold time
0
0
0
0
1
0
0
0
08H
0.8ns*
5
36 to 40
Superset information
0
0
0
0
0
0
0
0
00H
Future use
41
Minimum bank Cycle
(-7A)
0
0
1
1
1
1
0
0
3CH
60ns
(-75)
0
1
0
0
0
0
1
1
43H
67.5ns
42 to 61
Superset information
0
0
0
0
0
0
0
0
00H
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12H
Rev. 1.2
63
Checksum for bytes 062
(-7A)
0
0
1
1
0
1
1
0
36H
54
(-75)
0
1
1
1
1
1
1
0
7EH
126
64 to 65
Manufacturer's JEDEC ID code
0
1
1
1
1
1
1
1
7FH
Continuation code
66
Manufacturer's JEDEC ID code
1
1
1
1
1
1
1
0
FEH
Elpida Memory
67 to 71
Manufacturer's JEDEC ID code
0
0
0
0
0
0
0
0
00H
72
Manufacturing location
*
2
(ASCII-8bit code)
73
Manufacturer's part number
0
1
0
0
0
1
0
1
45H
E
74
Manufacturer's part number
0
1
0
0
0
0
1
0
42H
B
75
Manufacturer's part number
0
1
0
1
0
0
1
1
53H
S
76
Manufacturer's part number
0
0
1
1
0
0
1
0
32H
2
77
Manufacturer's part number
0
0
1
1
0
0
0
1
31H
1
78
Manufacturer's part number
0
1
0
1
0
0
1
0
52H
R
79
Manufacturer's part number
0
1
0
0
0
0
1
1
43H
C
80
Manufacturer's part
0
0
1
1
0
0
1
0
32H
2
81
Manufacturer's part number
0
1
0
0
0
0
0
1
41H
A
82
Manufacturer's part number
0
1
0
0
0
0
1
1
43H
C
83
Manufacturer's part number
0
1
0
0
1
1
1
0
4EH
N
84
Manufacturer's part number
0
1
0
0
0
0
0
1
41H
A
85
Manufacturer's part number
0
0
1
0
1
1
0
1
2DH
--
86
Manufacturer's part number
0
0
1
1
0
1
1
1
37H
7
87
Manufacturer's part number
(-7A)
0
1
0
0
0
0
0
1
41H
A
(-75)
0
0
1
1
0
1
0
1
35H
5
88
Manufacturer's part number
0
0
1
0
0
0
0
0
20H
(Space)
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