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Электронный компонент: EDD1232AAFA-7A-E

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Document No. E0432E50 (Ver.5.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005
DATA SHEET
128M bits DDR SDRAM
EDD1232AAFA (4M words
32 bits)
Description
The EDD1232AAFA is a 128M bits DDR SDRAM
organized as 1,048,576 words
32 bits
4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 100-pin plastic LQFP package.
Features
Power supply: VDDQ = 2.5V
0.2V
: VDD = 2.5V
0.2V
Data rate: 333Mbps/266Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5, 3
Programmable output driver strength: half/weak
Refresh cycles: 4096 refresh cycles/32ms
7.8
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
LQFP package with lead free solder (Sn-Bi)
RoHS compliant
EDD1232AAFA
Data Sheet E0432E50 (Ver.5.0)
2
Ordering Information

Part number
Mask
version
Organization
(words
bits)
Internal
banks
Data Rate
Mbps (max.)
JEDEC speed bin
(CL-tRCDRD-tRP)

Package
EDD1232AAFA-6B-E
EDD1232AAFA-7A-E
A 4M
32
4
333
266
DDR333B (2.5-3-3)
DDR266A (2-3-3)
100-pin Plastic
LQFP
Part Number
Elpida Memory
Density / Bank
12: 128M / 4-bank
Organization
32: x32
Power Supply, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
FA: LQFP
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
Product Family
D: DDR SDRAM
Type
D: Monolithic Device
E D D 12 32 A A FA - 6B - E
Environment Code
E: Lead Free
EDD1232AAFA
Data Sheet E0432E50 (Ver.5.0)
3
Pin Configurations
/xxx indicates active low signal.
A7
A6
A5
A4
VSS
A9
NC
NC
NC
NC
NC
NC
NC
A11
A10
VDD
A3
A2
A1
A0
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
NC
NC
NC
VSSQ
NC
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin
plastic
LQFP
(Top view)
DQ28
VDDQ
DQ27
DQ25
DQ24
VDDQ
DQ15
DQ13
DQ12
DQ10
VSSQ
VDDQ
VREF
DM3
DM1
CKE
MCL
A8 (AP)
DQ26
V
SSQ
DQ14
VSSQ
DQ9
DQ8
CK
/CK
VSS
DQ11
VDDQ
VDD
DQ3
VDDQ
DQ4
DQ6
DQ7
VDDQ
DQ16
DQ18
DQ19
DQ21
VSSQ
VDDQ
DM0
DM2
/WE
/CS
BA0
BA1
DQ5
V
SSQ
DQ17
VSSQ
DQ22
DQ23
/CAS
/RAS
VDD
DQ20
VDDQ
VSS
NC
NC
20
14mm2
0.65mm pin pitch
Pin name
Function
Pin name
Function
A0 to A11
Address inputs
CK
Clock input
BA0, BA1
Bank select address
/CK
Differential Clock input
DQ0 to DQ31
Data-input/output
CKE
Clock enable
DQS
Input and output data strobe
VREF
Input reference voltage
/CS
Chip select
VDD
Power for internal circuit
/RAS
Row address strobe command
VSS
Ground for internal circuit
/CAS
Column address strobe command
VDDQ
Power for DQ circuit
/WE
Write enable
VSSQ
Ground for DQ circuit
DM0 to DM3
Input mask
MCL
Must be connected with VSS
NC No
connection
EDD1232AAFA
Data Sheet E0432E50 (Ver.5.0)
4
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................11
Pin Function.................................................................................................................................................12
Command Operation ...................................................................................................................................14
Simplified State Diagram .............................................................................................................................21
Operation of the DDR SDRAM ....................................................................................................................22
Timing Waveforms.......................................................................................................................................41
Package Drawing ........................................................................................................................................47
Recommended Soldering Conditions..........................................................................................................48
EDD1232AAFA
Data Sheet E0432E50 (Ver.5.0)
5
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200 s and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Note
Voltage on any pin relative to VSS
VT
1.0 to +3.6
V
Supply voltage relative to VSS
VDD
1.0 to +3.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70
C)
Parameter Symbol
min.
typ.
max.
Unit
Notes
Supply voltage
VDD,
VDDQ
2.3 2.5
2.7 V
1
VSS,
VSSQ
0 0
0 V
Input reference voltage
VREF
0.49
VDDQ
0.50
VDDQ 0.51
VDDQ
V
Termination voltage
VTT
VREF 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
--
VDDQ + 0.3
V
2
Input low voltage
VIL (DC)
0.3
--
VREF 0.15
V
3
Input voltage level,
CK and /CK inputs
VIN (DC)
0.3
--
VDDQ + 0.3
V
4
Input differential cross point
voltage, CK and /CK inputs
VIX (DC)
0.5
VDDQ
-
0.2V 0.5
VDDQ
0.5
VDDQ + 0.2V V
Input differential voltage,
CK and /CK inputs
VID (DC)
0.36
--
VDDQ + 0.6
V
5, 6
Notes: 1. VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to 1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable DC execution of each differential input.
5. VID (DC) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF 0.18V
if measurement.