Document Outline
- COVER
- Description
- Features
- Ordering Information
- Part Number
- Pin Configurations
- Electrical Specifications
- Absolute Maximum Ratings
- Recommended DC Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- AC Electrical Characteristics and Operating Conditions
- Test Conditions
- Block Diagram
- Pin Function
- Command Operation
- Command Truth Table
- CKE Truth Table
- Function Truth Table
- Simplified State Diagram
- Operation of DDR2 SDRAM
- Power On and Initialization
- Power-Up and Initialization Sequence
- Programming the Mode Register
- DDR2 SDRAM Mode Register Set
- DDR2 SDRAM Extended Mode Register Set
- DLL Enable/Disable
- Off-Chip Driver (OCD) Impedance Adjustment
- ODT(On Die Termination)
- Bank Activate Command
- Read and Write Access Modes
- Posted /CAS
- Burst Mode Operation
- Burst Read Command
- Burst Write Command
- Write data mask
- Precharge Command
- Burst Read Operation Followed by Precharge
- Burst Write followed by Precharge
- Auto-Precharge Operation
- Burst Read with Auto Precharge
- Burst Write with Auto-Precharge
- Refresh Requirements
- Automatic Refresh Command
- Self Refresh Command
- Power-Down
- Burst Interruption
- No Operation Command
- Deselect Command
- Package Drawing
- 64-ball FBGA (uBGA)
- 80-ball FBGA (uBGA)
- Recommended Soldering Conditions
Document No. E0323E30 (Ver. 3.0)
Date Published March 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002-2003
PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104ABSE (128M words
4 bits)
EDE5108ABSE (64M words
8 bits)
EDE5116ABSE (32M words
16 bits)
Description
The EDE5104AB is a 512M bits DDR2 SDRAM
organized as 33,554,432 words
4 bits
4 banks.
The EDE5108AB is a 512M bits DDR2 SDRAM
organized as 16,777,216 words
8 bits
4 banks.
They are packaged in 64-ball FBGA (
BGA
) package.
The EDE5116AB is a 512M bits DDR2 SDRAM
organized as 8,388,608 words
16 bits
4 banks.
It is packaged in 84-ball FBGA (
BGA) package.
Features
1.8V power supply
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8
s average periodic refresh interval
1.8V (SSTL_18 compatible) I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
8
organization compatible to
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA(
BGA) package is lead free solder (Sn-Ag-Cu)
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Preliminary Data Sheet E0323E30 (Ver. 3.0)
2
Ordering Information
Part number
Mask
version
Organization
(words
bits)
Internal
Banks
Speed bin
(CL-tRCD-tRP)
Package
EDE5104ABSE-5C-E
EDE5104ABSE-4A-E
EDE5104ABSE-4C-E
B 128M
4
4
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
64-ball FBGA (
BGA)
EDE5108ABSE-5C-E
EDE5108ABSE-4A-E
EDE5108ABSE-4C-E
64M
8
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
EDE5116ABSE-5C-E
EDE5116ABSE-4A-E
EDE5116ABSE-4C-E
32M
16
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-400 (4-4-4)
84-ball FBGA (
BGA)
Part Number
Elpida Memory
Density / Bank
51: 512M /4 banks
Bit Organization
04: x4
08: x8
16: x16
Voltage, Interface
A: 1.8V, SSTL_18
Die Rev.
Package
SE: FBGA (
BGA with back cover)
Speed
5C: DDR2-533 (4-4-4)
4A: DDR2-400 (3-3-3)
4C: DDR2-400 (4-4-4)
Product Code
E: DDR2
Type
D: Monolithic Device
E D E 51 04 A B SE - 5C - E
Environment code
Blank: Sn-Pb solder
E: Lead Free
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Preliminary Data Sheet E0323E30 (Ver. 3.0)
3
Pin Configurations
/xxx indicates active low signal.
VDD
1
DQ6
(NC)*
VDDQ
DQ4
(NC)*
VDDL
VSS
VDD
2
NU/ /RDQS
(NC)*
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
3
VSS
DM/RDQS
(DM)*
VDDQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
8
/DQS
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
9
VDDQ
DQ7
(NC)*
VDDQ
DQ5
(NC)*
VDD
VDD
VSS
(Top view)
64-ball FBGA (
BGA)
Note: ( )* marked pins are for
4 organization.
NC
ODT
(
8,
4 organization)
A
B
C
D
E
F
G
H
J
K
L
VDD
1
VDDQ
VDD
VDDL
2
VSSQ
UDM
DQ14
DQ9
VSSQ
DQ12
NC
VREF
3
VSS
NC
VDDQ
DQ11
VSS
CKE
/WE
VSS
7
VSSQ
UDQS
VDDQ
DQ10
VSSQ
/RAS
8
/UDQS
VSSQ
DQ15
DQ8
VSSQ
DQ13
/LDQS
/CK
M
N
P
R
VDD
A12
NC
NC
NC
9
VDDQ
VDDQ
DQ6
DQ4
VSSQ
DQ1
VDDQ
VSSQ
LDM
VDDQ
DQ3
LDQS
VDDQ
VSSQ
DQ0
VDDQ
DQ2
VSSQ
DQ5
DQ7
VDDQ
VSSDL
CK
VDD
VSS
A10
A3
A7
A1
A5
A9
A2
A6
A11
A0
A4
A8
VDD
VSS
(Top view)
84-ball FBGA (
BGA)
BA0
BA1
/CAS
/CS
NC
ODT
(
16 organization)
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
Pin name
Function
Pin name
Function
A0 to A13
Address inputs
ODT
ODT control
BA0, BA1
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ15
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
UDQS, /UDQS
LDQS, /LDQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
RDQS, /RDQS
Differential data strobe for read
VSSQ
Ground for DQ circuit
/CS
Chip select
VREF
Input reference voltage
/RAS, /CAS, /WE
Command input
VDDL
Supply voltage for DLL circuit
CKE
Clock enable
VSSDL
Ground for DLL circuit
CK, /CK
Differential Clock input
NC*
1
No
connection
DM, UDM, LDM
Write Data mask
NU*
2
Not
usable
Notes: 1. Not internally connected with die.
2. Don't use other than reserved functions.
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Preliminary Data Sheet E0323E30 (Ver. 3.0)
4
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of DDR2 SDRAM ........................................................................................................................21
Package Drawing ........................................................................................................................................54
Recommended Soldering Conditions ..........................................................................................................56
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Preliminary Data Sheet E0323E30 (Ver. 3.0)
5
Electrical Specifications
All voltages are referenced to VSS (GND)
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Note
Power supply voltage
VDD
0.5 to +2.3
V
1
Power supply voltage for output
VDDQ
0.5 to +2.3
V
1
Input voltage
VIN
0.5 to +2.3
V
1
Output voltage
VOUT
0.5 to +2.3
V
1
Operating temperature (ambient)
TA
0 to +70
C 1
Storage temperature
TSTG
55 to +150
C 1
Power dissipation
PD
1.0
W
1
Short circuit output current
IOUT
50
mA
1
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (SSTL_18)
There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all
conditions VDDQ must be less than or equal to VDD.
Parameter Symbol
min.
Typ.
max.
Unit
Notes
Supply voltage
VDD
1.7
1.8
1.9
V
4
Supply voltage for output
VDDQ
1.7
1.8
1.9
V
4
Input reference voltage
VREF
0.49
VDDQ
0.50
VDDQ 0.51
VDDQ
V
1, 2
Termination voltage
VTT
VREF 0.04
VREF
VREF + 0.04
V
3
DC input logic high
VIH (dc)
VREF + 0.125
VDDQ
+
0.3V
V
DC input low
VIL (dc)
0.3
VREF 0.125
V
AC input logic high
VIH (ac)
VREF + 0.250
V
AC input low
VIL (ac)
VREF 0.250
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5
VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed
2% VREF (dc).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and
VDDL tied together.
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