Document Outline
- COVER
- Description
- Features
- Pin Configurations
- Ordering Information
- Part Number
- Electrical Specifications
- Absolute Maximum Ratings
- Recommended DC Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- Test Conditions
- Synchronous Characteristics
- Asynchronous Characteristics
- Block Diagram
- Pin Function
- Command Operation
- Truth Table
- Command Truth Table
- DQM Truth Table
- CKE Truth Table
- Function Truth Table
- Simplified State Diagram
- Initialization
- Programming Mode Registers
- Mode register
- Extended Mode Register
- Mode Register Definition
- Burst Length and Sequence
- Address Bits of Bank-Select and Precharge
- Operation of the Mobile RAM
- Precharge
- Auto Precharge
- Read / Write Command Interval
- Burst Termination
- Timing Waveforms
- AC Parameters for Read Timing with Manual Precharge
- AC Parameters for Read Timing with Auto Precharge
- AC Parameters for Write Timing
- Mode Register Set
- Extended Mode Register Set
- Power On Sequence
- /CS Function
- Clock Suspension during Burst Read
- Clock Suspension during Burst Write
- Power Down Mode and Clock Mask
- Auto Refresh
- Self Refresh (Entry and Exit)
- Deep Power Down Entry
- Deep Power Down Exit
- Random Column Read
- Random Column Write
- Random Row Read
- Random Row Write
- Read and Write
- Interleaved Column Read Cycle
- Interleaved Column Write Cycle
- Auto Precharge after Read Burst
- Auto Precharge after Write Burst
- Precharge Termination
- Package Drawing
- Recommended Soldering Conditions
Document No. E0490E30 (Ver. 3.0)
Date Published September 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
PRELIMINARY DATA SHEET
512M bits Mobile RAM MCP
2 pcs of 256Mb components
EDL5132CBMA (16M words
32 bits)
Description
The EDL5132CBMA is a 512M bits Mobile RAM MCP
(Multi Chip Package) organized as 4,194,304 words
32 bits
4 banks, 2 pieces of 256M bits Mobile RAM in
one package. It is packaged in 90-ball FBGA.
Features
Low voltage power supply
VDD: 1.7V
to
1.95V
VDDQ: 1.7V to 1.95V
Wide temperature range (
-
25
C to 85
C)
Programmable Partial Array Self Refresh
Programmable Driver Strength
Auto Temperature Compensated Self Refresh by
built-in temperature sensor.
Deep power down mode
Fully Synchronous Dynamic RAM, with all signals
referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every
cycle
Quad internal banks controlled by BA0 and BA1
Byte control by DQM
Wrap sequence = Sequential/ Interleave
/CAS latency (CL) = 2, 3
Automatic precharge and controlled precharge
Auto refresh and self refresh
32 organization
8,192 refresh cycles/64ms
Burst termination by Burst stop command and
Precharge command
FBGA package with lead free solder (Sn-Ag-Cu)
Pin Configurations
/xxx indicates active low signal.
DQ26
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
A12
A9
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
/RAS
(Top view)
DQM1
NC
NC
/CAS
/WE DQM0
VDDQ DQ8
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
DQ13 DQ15 VSS
VDD
DQ0
DQ2
90-ball FBGA
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection
A0 to A12
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
EDL5132CBMA
Preliminary Data Sheet E0490E30 (Ver. 3.0)
2
Ordering Information
Part number
Organization
(words
bits)
Internal banks
Clock frequency
MHz (max.)
/CAS latency
Package
EDL5132CBMA-10-E 16M
32
4
100
3
90-ball FBGA
Part Number
Environment Code
E: Lead Free
Elpida Memory
Density / Bank
51: 512M /4-bank
Bit Organization
32: x32
Voltage, Interface
C: VDD = 1.8V, VDDQ = 1.8V, LVCMOS
Die Rev.
Package
MA: Stacked FBGA
Speed
10: 100MHz/CL3
Product Code
L: Mobile RAM
Type
D: Monolithic Device
E D L 51 32 C B MA - 10 - E
EDL5132CBMA
Preliminary Data Sheet E0490E30 (Ver. 3.0)
3
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Truth Table ..................................................................................................................................................17
Simplified State Diagram .............................................................................................................................23
Initialization ..................................................................................................................................................24
Programming Mode Registers.....................................................................................................................24
Address Bits of Bank-Select and Precharge ...............................................................................................28
Operation of the Mobile RAM ......................................................................................................................29
Timing Waveforms.......................................................................................................................................37
Package Drawing ........................................................................................................................................59
Recommended Soldering Conditions..........................................................................................................60
EDL5132CBMA
Preliminary Data Sheet E0490E30 (Ver. 3.0)
4
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200
s and then, execute Power on sequence and two Auto Refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Note
Voltage on any pin relative to VSS
VT
0.5 to +2.6
V
Supply voltage relative to VSS
VDD, VDDQ
0.5 to +2.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
25 to +85
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 25 to +85
C)
Parameter Symbol
min.
typ.
max.
Unit
Notes
Supply
voltage
VDD
1.7 1.8 1.95 V
VSS,
VSSQ
0 0 0 V
DQ Supply voltage
VDDQ
1.7
1.8
1.95
V
Input high voltage
VIH
0.8
VDDQ
VDDQ
+
0.3
V
1
Input low voltage
VIL
0.3
0.3 V
2
Notes: 1. VIH (max.) = 2.6V (pulse width
5ns)
2. VIL (min.) = 1.0V (pulse width
5ns)
EDL5132CBMA
Preliminary Data Sheet E0490E30 (Ver. 3.0)
5
DC Characteristics 1 (TA = 25 to +85
C, VDD = VDDQ = 1.7V to 1.95V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
(CL = 2)
IDD1
80 mA
1
(CL = 3)
IDD1
80 mA
Burst length = 1
tRC
tRC min., IO = 0mA,
One bank active
Standby current in power down
IDD2P
1.2 mA
CKE
VIL max., tCK = 15ns
Standby current in power down
(input signal stable)
IDD2PS
1 mA
CKE
VIL max., tCK =
Standby current in non power down
IDD2N
6 mA
CKE
VIH min., tCK = 15ns,
/CS
VIH min.,
Input signals are changed one
time during 30ns.
Standby current in non power down
(input signal stable)
IDD2NS
4 mA
CKE
VIH min., tCK =
,
Input signals are stable.
Active standby current in power down
IDD3P
2 mA
CKE
VIL max., tCK = 15ns
Active standby current in power down
(input signal stable)
IDD3PS
1.6 mA
CKE
VIL max., tCK =
Active standby current in non power
down
IDD3N
30 mA
CKE
VIH min., tCK = 15 ns,
/CS
VIH min.,
Input signals are changed one
time during 30ns.
Active standby current in non power
down (input signal stable)
IDD3NS
10 mA
CKE
VIH min., tCK =
,
Input signals are stable.
Burst operating current
(CL = 2)
IDD4
90 mA
tCK
tCK min.,
IOUT = 0mA, All banks active
2
(CL = 3)
IDD4
120 mA
Refresh current
(CL = 2)
IDD5
110 mA
tRC
tRC min.
3
(CL = 3)
IDD5
110 mA
Standby current in deep power down
mode
IDD7
20
A CKE
0.2V
Self refresh current
Symbol
Grade
typ.
max.
Unit
Condition
Notes
PASR="000" (Full)
IDD6
800
A
TA
85C +0C/
-
15C,
CKE
0.2V
4
PASR="001" (2BK)
600
A
PASR="010" (1BK)
500
A
PASR="000" (Full)
IDD6
400
A TA
45C, CKE
0.2V
4
PASR="001" (2BK)
360
A
PASR="010" (1BK)
300
A
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD1 is measured on condition that addresses are changed only one time during
tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured on condition that addresses are changed only one time during
tCK (min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
4. IDD6 is specified when self refresh state is maintained long enough under the specified TA condition, after
a busy sequence of read and write operations.
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