Document Outline
- COVER
- Specifications
- Features
- Pin Configurations
- Ordering Information
- Part Number
- Electrical Specifications
- Absolute Maximum Ratings
- Recommended DC Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- Test Conditions
- Relationship Between Frequency and Minimum Latency
- Block Diagram
- Pin Function
- Command Operation
- Command Truth Table
- DQM Truth Table
- CKE Truth Table
- Function Truth Table
- Command Truth Table for CKE
- Simplified State Diagram
- Mode Register Configuration
- Power-up sequence
- Power-up sequence
- Initialization sequence
- Operation of the SDRAM
- Read/Write Operations
- Auto Precharge
- Burst Stop Command
- Command Intervals
- DQM Control
- Refresh
- Others
- Timing Waveforms
- Read Cycle
- Write Cycle
- Mode Register Set Cycle
- Read Cycle/Write Cycle
- Read/Single Write Cycle
- Read/Burst Write Cycle
- Auto Refresh Cycle
- Self Refresh Cycle
- Clock Suspend Mode
- Power Down Mode
- Initialization Sequence
- Package Drawing
- Recommended Soldering Conditions
Document No. E0847E20 (Ver. 2.0)
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005-2006
PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1216AGTA (8M words
16 bits)
Specifications
Density: 128M bits
Organization
2M words
16 bits
4 banks
Package: 54-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ
=
3.3V
0.3V
Clock frequency: 166MHz/133MHz (max.)
Four internal banks for concurrent operation
Interface: LVTTL
Burst lengths (BL): 1, 2, 4, 8, full page
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
/CAS Latency (CL): 2, 3
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6
s
Operating ambient temperature range
TA = 0
C to +70
C
Features
Single pulsed /RAS
Burst read/write operation and burst read/single write
operation capability
Byte control by UDQM and LDQM
Pin Configurations
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
54-pin Plastic TSOP (II)
(Top view)
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
2
Ordering Information
Part number
Supply
voltage
Organization
(words
bits)
Internal
Banks
Clock frequency
MHz (max.)
/CAS latency
Package
EDS1216AGTA-6B-E 3.3V
8M
16
4
166
100
3
2
54-pin plastic TSOP (II)
EDS1216AGTA-75-E
133
100
3
2
Part Number
Environment Code
E: Lead Free
Elpida Memory
Density / Bank
12: 128M/4-bank
Organization
16: x16
Power Supply, Interface
A: 3.3V, LVTTL
Die Rev.
Package
TA: TSOP (II)
Speed
6B: 166MHz/CL3
100MHz/CL2
75: 133MHz/CL3
100MHz/CL2
Product Family
S: SDRAM
Type
D: Monolithic Device
E D S 12 16 A G TA - 6B - E
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
3
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................12
Simplified State Diagram .............................................................................................................................20
Mode Register Configuration.......................................................................................................................21
Power-up sequence.....................................................................................................................................23
Operation of the SDRAM.............................................................................................................................24
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
4
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter Symbol
Rating Unit
Note
Voltage on any pin relative to VSS
VT
0.5 to VDD + 0.5 ( 4.6 (max.))
V
Supply voltage relative to VSS]
VDD
0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70
C)
Parameter Symbol
min.
max.
Unit
Notes
Supply voltage
VDD, VDDQ
3.0
3.6
V
1
VSS,
VSSQ
0
0
V
2
Input high voltage
VIH
2.0
VDD + 0.3
V
3
Input low voltage
VIL
0.3
0.8
V
4
Notes: 1. The supply voltage with all VDD
and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 1.5V (pulse width 5ns).
4. VIL (min.) = VSS 1.5V (pulse width 5ns).
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
5
DC Characteristics 1 (TA = 0 to +70
C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
IDD1
-6B
-75
120
100
mA
Burst length = 1
tRC = tRC (min.)
1, 2, 3
Standby current in power down
IDD2P
3
mA
CKE = VIL,
tCK = tCK (min.)
6
Standby current in power down
(input signal stable)
IDD2PS
2
mA
CKE = VIL, tCK =
7
Standby current in non power down
IDD2N
20
mA
CKE, /CS = VIH,
tCK = tCK (min.)
4
Standby current in non power down
(input signal stable)
IDD2NS
9
mA
CKE = VIH, tCK =
,
/CS = VIH
8
Active standby current in power down
IDD3P
4
mA
CKE = VIL,
tCK = tCK (min.)
1, 2, 6
Active standby current in power down
(input signal stable)
IDD3PS
3
mA
CKE = VIL, tCK =
2,
7
Active standby current in non power down IDD3N
30
mA
CKE, /CS = VIH,
tCK = tCK (min.)
1, 2, 4
Active standby current in non power down
(input signal stable)
IDD3NS
25
mA
CKE = VIH, tCK =
,
/CS = VIH
2, 8
Burst operating current
IDD4
-6B
-75
140
120
mA
tCK = tCK (min.),
BL = 4
1, 2, 5
Refresh current
IDD5
-6B
-75
220
200
mA
tRC = tRC (min.)
3
Self refresh current
IDD6
2
mA
VIH VDD 0.2V
VIL 0.2V
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2.
One
bank
operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
6
DC Characteristics 2 (TA = 0 to +70
C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
Parameter Symbol
min.
max.
Unit
Test
condition
Notes
Input leakage current
ILI
1
1
A
0 VIN VDD
Output leakage current
ILO
1.5
1.5
A
0 VOUT VDD, DQ = disable
Output high voltage
VOH
2.4
--
V
IOH = 2 mA
Output low voltage
VOL
--
0.4
V
IOL = 2 mA
Pin Capacitance (TA = 25C, VDD, VDDQ = 3.3V 0.3V)
Parameter Symbol
Pins
min.
typ.
max.
Unit
Notes
Input capacitance
CI1
CLK
2.5
--
3.5
pF
1, 2, 4
CI2
Address, CKE, /CS,
/RAS, /CAS, /WE,
DQM
2.5
--
3.8
pF
1, 2, 4
Data input/output
capacitance
CI/O
DQ
4
--
6.5
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
7
AC Characteristics (TA = 0 to +70
C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
-6B
-75
Parameter
Symbol
min. max. min. max. Unit
Notes
System clock cycle time
(CL = 2)
tCK
10 -- 10 -- ns
1
(CL = 3)
tCK
6
--
7.5
--
ns
1
CLK high pulse width
tCH
2.5
--
2.5
--
ns
1
CLK low pulse width
tCL
2.5
--
2.5
--
ns
1
Access time from CLK
tAC
--
5.4
--
5.4
1, 2
Data-out
hold
time
tOH
2.5 -- 2.5 -- ns
1,
2
CLK to Data-out low impedance
tLZ
0
--
0
--
ns
1, 2, 3
CLK to Data-out high impedance
tHZ
--
5.4
--
5.4
ns
1, 4
Input setup time
tSI
1.5
--
1.5
--
ns
1
Input hold time
tHI
0.8
--
0.8
--
ns
1
Ref/Active to Ref/Active command
period
tRC
60 -- 67.5
-- ns
1
Active to Precharge command
period
tRAS
42
120000 45
120000 ns 1
Active command to column
command
(same bank)
tRCD
18 -- 20 -- ns
1
Precharge to active command
period
tRP
18 -- 20 -- ns
1
Write recovery or data-in to
precharge lead time
tDPL
12 -- 15 -- ns
1
Last data into active latency
tDAL
2CLK + 18ns --
2CLK + 20ns --
Active (a) to Active (b) command
period
tRRD
12 -- 15 -- ns
1
Transition time (rise and fall)
tT
0.5
5
0.5
5
ns
Refresh period
(4096 refresh cycles)
tREF
-- 64 -- 64 ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
8
Test Conditions
AC high level voltage/low level input voltage: 2.4V/0.4V
Input and output timing reference levels: 1.4V
Input waveform and output load: See following figures
tT
2.4 V
0.4 V
0.8 V
2.0 V
input
t
T
I/O
CL
Input waveform and Output load
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
9
Relationship Between Frequency and Minimum Latency
Parameter
-6B
-75
Frequency
(MHz)
166 100 133 100
tCK
(ns)
Symbol
6 10 7.5 10 Unit
Notes
Active command to column command
(same bank)
lRCD
3 2 3 2 tCK
1
Active command to active command
(same bank)
lRC
10 7 9 7 tCK
1
Active command to precharge command
(same bank)
lRAS
7 5 6 5 tCK
1
Precharge command to active command
(same bank)
lRP
3 2 3 2 tCK
1
Write recovery or data-in to precharge
command (same bank)
lDPL
2 2 2 2 tCK
1
Active command to active command
(different bank)
lRRD
2 2 2 2 tCK
1
Self refresh exit time
lSREX
1 1 1 1 tCK
2
Last data in to active command
(Auto precharge, same bank)
lDAL
5 4 5 4 tCK
=
[lDPL + lRP]
Self refresh exit to command input
lSEC
10 7 9 7 tCK
= [lRC]
3
Precharge command to high impedance
(CL = 2)
lHZP
2
2 tCK
(CL = 3)
lHZP
3 3 3 3 tCK
Last data out to active command
(Auto precharge, same bank)
lAPR
1 1 1 1 tCK
Last data out to precharge (early precharge)
(CL = 2)
lEP
1
1 tCK
(CL = 3)
lEP 2 2 2 2 tCK
Column command to column command
lCCD
1 1 1 1 tCK
Write command to data in latency
lWCD
0 0 0 0 tCK
DQM to data in
lDID
0 0 0 0 tCK
DQM to data out
lDOD
2 2 2 2 tCK
CKE to CLK disable
lCLE
1 1 1 1 tCK
Register set to active command
lMRD
2 2 2 2 tCK
/CS to command disable
lCDD
0 0 0 0 tCK
Power down exit to command input
lPEC
1 1 1 1 tCK
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
10
Block Diagram
Clock
Generator
Mode
Register
Command Decoder
Control Logic
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Data Control Circuit
Latch Circuit
Input & Output
Buffer
DQ
UDQM and LDQM
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Bank 3
Bank 2
Bank 1
Sense Amplifier
Column Decoder &
Latch Circuit
Bank 0
Row Decoder
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
11
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A8 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
UDQM and LDQM
(input pins)
UDQM and LDQM control input/output buffers. UDQM and LDQM control upper byte (DQ8 to DQ15) and lower byte
(DQ0 to DQ7).
DQ0 to DQ15 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
12
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Symbol n
1
n /CS /RAS /CAS /WE BA1 BA0 A10
A0 to
A11
Device deselect
DESL
H
H
No operation
NOP
H
L H H H
Burst stop
BST
H
L H H L
Read READ
H
L H L H V V L V
Read with auto precharge
READA
H
L H L H V V H V
Write WRIT
H
L H L L V V L V
Write with auto precharge
WRITA
H
L H L L V V H V
Bank activate
ACT
H
L L H H V V V V
Precharge select bank
PRE
H
L L H L V V L
Precharge all banks
PALL
H
L L H L
H
Mode register set
MRS
H
L L L L L L L V
Remark: H: VIH. L: VIL.
: VIH or VIL. V: Valid address input.
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
13
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (A0 to A11). (See
Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and
the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]
The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins
(A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the Mode Register Configuration. After
power on, the contents of the mode register are undefined, execute the mode register set command to set up the
mode register.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
14
DQM Truth Table
CKE
Commands
Symbol
n 1
n
UDQM
LDQM
Upper byte write enable/output enable
ENBU
H
L
Lower byte write enable/output enable
ENBL
H
L
Upper byte write inhibit/output disable
MASKU
H
H
Lower byte write inhibit/output disable
MASKL
H
H
Remark: H: VIH. L: VIL.
: VIH or VIL
Write:
lDID is needed.
Read:
lDOD is needed.
CKE Truth Table
CKE
Current state
Function
Symbol
n 1
n
/CS
/RAS
/CAS
/WE
Address
Activating
Clock suspend mode entry
H
L
Any
Clock suspend mode
L
L
Clock suspend
Clock suspend mode exit
L
H
Idle
CBR (auto) refresh command
REF
H
H
L
L
L
H
Idle
Self refresh entry
SELF
H
L
L
L
L
H
Self refresh
Self refresh exit
L
H
L
H
H
H
L
H
H
Idle
Power down entry
H
L
L
H
H
H
H
L
H
Power down
Power down exit
L
H
H
L H L H H H
Remark: H: VIH. L: VIL.
: VIH or VIL
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
15
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current
state
/CS /RAS /CAS /WE Address
Command
Operation
Precharge H
DESL
Enter IDLE after tRP
L H H H
NOP
Enter IDLE after tRP
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
3
L H L L BA,
CA,
A10
WRIT/WRITA ILLEGAL*
3
L
L
H
H
BA,
RA
ACT
ILLEGAL*
3
L L H L BA,
A10 PRE,
PALL NOP*
5
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Idle H
DESL NOP
L H H H
NOP NOP
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L H L L BA,
CA,
A10
WRIT/WRITA ILLEGAL*
4
L
L
H
H
BA, RA
ACT
Bank and row active
L L H L BA,
A10 PRE,
PALL NOP
L L L H
REF,
SELF
Refresh
L L L L MODE
MRS
Mode
register
set*
8
Row active
H
DESL NOP
L H H H
NOP NOP
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Begin read*
6
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write*
6
L
L
H
H
BA,
RA
ACT
Other bank active
ILLEGAL on same bank*
2
L L H L BA,
A10 PRE,
PALL Precharge*
7
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Read
H
DESL
Continue burst to end
L H H H
NOP
Continue burst to end
L H H L
BST Burst
stop
L
H
L
H
BA, CA, A10
READ/READA
Continue burst read to /CAS
latency and New read
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst read/start write
L L H H BA,
RA ACT
Other bank active
ILLEGAL on same bank*
2
L
L
H
L
BA, A10
PRE, PALL
Term burst read and Precharge
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
16
Current
state
/CS /RAS /CAS /WE Address
Command
Operation
Read with auto-
precharge
H
DESL
Continue burst to end and
precharge
L H H H
NOP
Continue burst to end and
precharge
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
3
L H L L BA,
CA,
A10
WRIT/WRITA ILLEGAL*
3
L
L
H
H
BA,
RA
ACT
Other bank active
ILLEGAL on same bank*
2
L L H L BA,
A10 PRE,
PALL ILLEGAL*
3
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Write H
DESL
Continue burst to end
L H H H
NOP
Continue burst to end
L H H L
BST Burst
stop
L
H
L
H
BA, CA, A10
READ/READA
Term burst and New read
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst and New write
L
L
H
H
BA,
RA
ACT
Other bank active
ILLEGAL on same bank*
3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and Precharge*
1
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Write with auto-
precharge
H
DESL
Continue burst to end and
precharge
L H H H
NOP
Continue burst to end and
precharge
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
3
L H L L BA,
CA,
A10
WRIT/WRITA ILLEGAL*
3
L L H H BA,
RA ACT
Other bank active
ILLEGAL on same bank*
3
L L H L BA,
A10 PRE,
PALL ILLEGAL*
3
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Refresh (auto-refresh) H
DESL
Enter IDLE after tRC
L H H H
NOP
Enter IDLE after tRC
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L H L L BA,
CA,
A10
WRIT/WRITA ILLEGAL*
4
L L H H BA,
RA ACT
ILLEGAL*
4
L L H L BA,
A10 PRE,
PALL ILLEGAL*
4
L L L H
REF,
SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
17
Current
state
/CS /RAS /CAS /WE Address
Command
Operation
Mode register set
H
DESL NOP
L H H H
NOP NOP
L H H L
BST ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L H L L BA,
CA,
A10
WRIT/WRITA ILLEGAL*
4
L
L
H
H
BA, RA
ACT
Bank and row active*
9
L L H L BA,
A10 PRE,
PALL NOP
L L L H
REF,
SELF
Refresh*
9
L L L L MODE
MRS
Mode
register
set*
8
Remark: H: VIH. L: VIL.
: VIH or VIL
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9.
Illegal
if
lMRD is not satisfied.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
18
Command Truth Table for CKE
CKE
Current State
n 1 n
/CS /RAS /CAS /WE Address
Operation
Notes
Self refresh
H
INVALID, CLK (n 1) would exit self refresh
L
H
H
Self refresh recovery
L
H
L
H
H
Self refresh recovery
L
H
L
H
L
ILLEGAL
L
H
L
L
ILLEGAL
L
L
Continue self refresh
Self refresh recovery H
H
H
Idle after t
RC
H
H
L
H
H
Idle after t
RC
H
H
L
H
L
ILLEGAL
H
H
L
L
ILLEGAL
H
L
H
ILLEGAL
H
L
L
H
H
ILLEGAL
H
L
L
H
L
ILLEGAL
H
L
L
L
ILLEGAL
Power down
H
INVALID, CLK (n 1) would exit power down
L
H
H
EXIT power down
L
H
L
H
H
H
EXIT power down
L
L
Continue power down mode
All banks idle
H
H
H
Refer to operations in Function Truth Table
H
H
L
H
Refer to operations in Function Truth Table
H H L L H
Refer to operations in Function Truth Table
H H L L L H
CBR (auto) Refresh
H
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
Begin power down next cycle
H
L
L
H
Refer to operations in Function Truth Table
H L L L H
Refer to operations in Function Truth Table
H L L L L H
Self
refresh
1
H
L
L
L
L
L
OPCODE Refer to operations in Function Truth Table
L
H
Exit power down next cycle
L
L
Power
down
1
Row active
H
Refer to operations in Function Truth Table
L
Clock
suspend
1
Any state other than H
H
Refer to operations in Function Truth Table
listed above
H
L
Begin clock suspend next cycle
2
L
H
Exit clock suspend next cycle
L
L
Maintain
clock
suspend
Remark: H: VIH. L: VIL.
: VIH or VIL
Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle. Clock suspend can be entered only from following states, row active, read, read with auto-
precharge, write and write with auto precharge.
2. Must be legal command as defined in Function Truth Table.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
19
Clock suspend mode entry
The SDRAM enters clock suspend mode from active mode by setting CKE to Low. If command is input in the clock
suspend mode entry cycle, the command is valid. The clock suspend mode changes depending on the current
status (1 clock before) as shown below.
ACTIVE clock suspend
This suspend mode ignores inputs after the next clock by internally maintaining the bank active status.
READ suspend and READ with Auto-precharge suspend
The data being output is held (and continues to be output).
WRITE suspend and WRIT with Auto-precharge suspend
In this mode, external signals are not accepted. However, the internal state is held.
Clock suspend
During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit
The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state.
IDLE
In this state, all banks are not selected, and completed precharge operation.
Auto-refresh command [REF]
When this command is input from the IDLE state, the SDRAM starts auto-refresh operation. (The auto-refresh is the
same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank
select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is
updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh
command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically
performed after auto-refresh, no precharge command is required after auto-refresh.
Self-refresh entry [SELF]
When this command is input during the IDLE state, the SDRAM starts self-refresh operation. After the execution of
this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically,
external refresh operations are unnecessary.
Power down mode entry
When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down
mode, power consumption is suppressed by cutting off the initial input circuit.
Self-refresh exit
When this command is executed during self-refresh mode, the SDRAM can exit from self-refresh mode. After exiting
from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit
When this command is executed at the power down mode, the SDRAM can exit from power down mode. After
exiting from power down mode, the SDRAM enters the IDLE state.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
20
Simplified State Diagram
PRECHARGE
WRITE
SUSPEND
READ
SUSPEND
ROW
ACTIVE
IDLE
IDLE
POWER
DOWN
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
ON
WRITEA
WRITEA
SUSPEND
READA
READA
SUSPEND
ACTIVE
CLOCK
SUSPEND
SR ENTRY
SR EXIT
MRS
REFRESH
CKE
CKE_
ACTIVE
WRITE
READ
WRITE
WITH AP
READ
WITH AP
POWER
APPLIED
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
PRECHARGE
AP
READ
WRITE
WRITE
WITH
AP
READ
WITH
READ
WITH AP
WRITE
WITH AP
PRECHARGE
PRECHARGE
PRECHARGE
BST
BST
*1
READ
Read
WRITE
Write
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
21
Mode Register Configuration
Mode Register Set
The mode register is set by the input to the address pins (A0 to A11, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode,
and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
A2
A1 A0
Burst length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
1
1
BT=0
BT=1
1
0
0
R
1
1
0
R
1
2
4
8
R
R
R
A3
0
Sequential
1
Interleave
Burst type
A6 A5
A4
CAS latency
0
0
0
R
0
0
1
R
0
1
0
2
0
1
1
3
1
X
X
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
R
Write mode
A8
0
1
Burst read and burst write
1
Burst read and single write
0
1
R
1
1
0
1
R
R
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
X
X
X
A11
X
X
X
0
0
BA0
BA1
BA1 BA0
0
0
0
0
0
0
0
0
X
R
X
X
R
X
X
R
X
X
X
X
X
X
X
1
0
1
0
1
1
F.P.
Mode Register Set
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
22
A2
A1
A0
Addressing(decimal)
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
Interleave
Sequential
1
0
0
1
1
0
1
0
1
Starting Ad.
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0,
0, 1,
0, 1, 2,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
6,
4, 5,
6, 5, 4,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
6, 5, 4, 3, 2, 1, 0,
Burst length = 8
A1
A0
Addressing(decimal)
0
0
0
1
1
0
1
1
Interleave
Sequential
Starting Ad.
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Burst length = 4
A0
Addressing(decimal)
0
1
Interleave
Sequential
Starting Ad.
0, 1,
1, 0,
0, 1,
1, 0,
Burst length = 2
Burst Sequence
Full page burst is available only for sequential addressing. The addressing sequence is started from the column
address that is asserted by read/write command. And the address is increased one by one.
It is back to the address 0 when the address reaches at the end of address 511. "Full page burst" stops the burst
read/write with burst stop command.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
23
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these
pins go high before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 s or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
VDD, VDDQ
Power up sequence
Initialization sequence
100
s
0 V
Low
Low
Low
CKE,
UDQM, LDQM
CLK
/CS, DQ
200
s
Power stabilize
Power-up sequence and Initialization sequence
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
24
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
READ
CLK
Command
DQ
ACT
Row
Column
Address
CL = 2
CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
tRCD
CL = /CAS latency
Burst Length = 4
/CAS Latency
READ
CLK
Command
DQ
ACT
Row
Column
out 0
out 6
out 7
Address
out 0 out 1
out 4
out 5
out 0 out 1 out 2 out 3
BL = 1
out 0 out 1 out 2
out 3
BL = 2
BL = 4
BL = 8
tRCD
BL : Burst Length
/CAS Latency = 2
Burst Length
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
25
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
WRIT
CLK
Command
DQ
ACT
Row
Column
in 0
in 6
in 7
Address
in 1
in 4
in 5
in 3
BL = 1
BL = 2
BL = 4
BL = 8
tRCD
in 0
in 0
in 0
in 1
in 1
in 2
in 2
in 3
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CLK
Command
DQ
ACT
Row
Column
in 0
Address
tRCD
Single write
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
26
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
l
APR
l
RAS
l
APR
CL=2 Command
CL=3 Command
DQ
DQ
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (
l
RAS) is required between previous active (ACT) command and internal precharge " ".
ACT
READA
ACT
out3
out2
out1
out0
l
RAS
ACT
READA
ACT
out3
out2
out1
out0
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
CLK
Command
DQ
l
DAL
l
RAS
ACT
WRITA
in0
in1
in2
in3
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (
l
RAS) is required between previous active (ACT) command
and internal precharge " ".
Burst Write (BL = 4)
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
27
CLK
Command
DQ
l
DAL
l
RAS
ACT
WRITA
in
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (
l
RAS) is required between previous active (ACT) command
and internal precharge " ".
Single Write
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
28
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
Command
DQ
(CL = 2)
DQ
(CL = 3)
READ
BST
out
out
out
out
out
out
High-Z
High-Z
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
Command
DQ
in
in
in
BST
WRITE
in
High-Z
Burst Stop at Write
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
29
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
DQ
out B3
Address
out B1 out B2
BS
ACT
Row
Column A
READ
READ
Column B
out A0 out B0
Bank0
Active
Column =A
Read
Column =B
Read
Column =A
Dout
Column =B
Dout
CL = 3
BL = 4
Bank 0
READ to READ Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
DQ
out B3
Address
out B1 out B2
BS
ACT
Row 0
Row 1
ACT
READ
Column A
out A0 out B0
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
READ
Column B
Bank0
Dout
Bank3
Dout
CL = 3
BL = 4
READ to READ Command Interval (different bank)
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
30
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
DQ
in B3
Address
in B1
in B2
BS
ACT
Row
Column A
WRIT
WRIT
Column B
in A0
in B0
Bank0
Active
Column =A
Write
Column =B
Write
Burst Write Mode
BL = 4
Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
DQ
in B3
Address
in B1
in B2
BS
ACT
Row 0
Row 1
ACT
WRIT
Column A
in A0
in B0
Bank0
Active
Bank3
Active
Bank0
Write
Bank3
Write
WRIT
Column B
Burst Write Mode
BL = 4
WRITE to WRITE Command Interval (different bank)
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
31
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
DQ (output)
in B2
in B3
READ
WRIT
in B0
in B1
High-Z
DQ (input)
CL=2
CL=3
UDQM
LDQM
BL = 4
Burst write
READ to WRITE Command Interval (1)
CLK
Command
DQ
READ
WRIT
CL=2
CL=3
UDQM
LDQM
2 clock
out
out
out
out
out
in
in
in
in
in
in
in
in
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, UDQM and LDQM must be set High so
that the output buffer becomes High-Z before data input.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
32
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
DQ (input)
WRIT
READ
in A0
out B1
out B2
out B3
out B0
DQ (output)
Column = A
Write
Column = B
Read
Column = B
Dout
/CAS Latency
UDQM
LDQM
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (1)
CLK
Command
DQ (input)
WRIT
READ
in A0
out B1
out B2
out B3
out B0
DQ (output)
Column = A
Write
Column = B
Read
Column = B
Dout
/CAS Latency
in A1
UDQM
LDQM
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
33
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
DQ
READA
READ
out A0
out A1
out B0
out B1
CL= 3
BL = 4
bank0
Read A
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
CLK
Command
BS
DQ
WRITA
WRIT
in B1
in B2
in B3
in A0
in A1
in B0
BL= 4
bank0
Write A
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
34
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input. The
internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
DQ (output)
DQ (input)
CL = 2
CL = 3
READA
WRIT
in B0
in B1
in B2
in B3
BL = 4
bank0
ReadA
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
UDQM
LDQM
High-Z
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
CLK
Command
BS
DQ (output)
DQ (input)
WRITA
READ
out B0
out B1
out B2
out B3
CL = 3
BL = 4
bank0
WriteA
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
UDQM
LDQM
in A0
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
35
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as
an interval from the final data output to precharge command execution.
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=2
l
EP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=3
l
EP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
High-Z
l
HZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
Command
DQ
READ
PRE/PALL
out A0
l
HZP =3
High-Z
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
36
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of UDQM and LDQM for assurance of the clock defined by tDPL.
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
UDQM
LDQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
in A3
UDQM
LDQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
37
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
Bank 0
Active
ACT
ROW
ACT
ROW
Bank 0
Active
tRC
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
Bank 0
Active
Bank 3
Active
ACT
ROW:0
ACT
ROW:1
tRRD
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Command
Address
Mode
Register Set
Bank
Active
MRS
l
MRD
ACT
BS & ROW
OPCODE
Mode register set to Bank active command interval
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
38
DQM Control
The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and
LDQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low,
the output buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer
becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The
latency of UDQM and LDQM during reading is 2 clocks.
Writing
Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when
UDQM and LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency
of UDQM and LDQM during writing is 0 clock.
CLK
DQ
out 0
out 1
l
DOD = 2 Latency
out 3
UDQM
LDQM
High-Z
Reading
CLK
DQ
in 0
in 1
l
DID = 0 Latency
in 3
UDQM
LDQM
Writing
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
39
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-
refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a
self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or
within tREF (max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after
exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
40
Timing Waveforms
Read Cycle
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
CLK
CKE
/CS
tRAS
tRCD
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
/RAS
/CAS
/WE
BS
A10
Address
UDQM
LDQM
DQ (input)
DQ (output)
tHI
tSI
tCH t
tCK
tAC
tAC
CL
tAC
tOH
tOH
tOH
tOH
t
RP
t RC
/CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
= VOH or VOL
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
t
tLZ
VIH
tHZ
AC
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
41
Write Cycle
CLK
CKE
/CS
tRAS
tRCD
/RAS
/CAS
/WE
BS
A10
Address
DQ (input)
DQ (output)
tCH t
tCK
tHI
tHI
CL
t HI
tHI
tSI
tSI
tSI
tSI
tRP
tRC
tDPL
Bank 0
Write
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tHI
tSI
tSI
Bank 0
Active
Bank 0
Precharge
VIH
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
UDQM
LDQM
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
UDQM
LDQM
DQ (input)
DQ (output)
High-Z
b
b+3
b'
b'+1
b'+2
b'+3
l
MRD
valid
C: b'
code
l
RCD
l
RP
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
R: b
C: b
Output mask
VIH
l
RCD
= 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
42
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:b
C:b'
C:b"
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
UDQM, LDQM
DQ (output)
DQ (input)
CLK
BS
R:a
C:a
R:b
C:b
C:b'
C:b"
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3
Read
Bank 3
Read
Bank 3
Read
Bank 0
Precharge
Bank 3
Precharge
Bank 0
Active
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 3
Write
Bank 3
Write
Bank 0
Precharge
Bank 3
Precharge
CKE
/RAS
/CS
/CAS
/WE
Address
DQ (input)
DQ (output)
BS
High-Z
High-Z
VIH
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
VIH
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a'
R:a
C:a
C:a
a
a
a
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
R:b
Bank 3
Active
C:a
Bank 0
Read
a
a+1 a+2 a+3
Bank 0
Write
Bank 0
Write
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
DQ (input)
DQ (output)
CLK
BS
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
BS
C:b
b
c
a+1
a+3
a+1 a+2 a+3
C:c
VIH
VIH
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
DQ (input)
DQ (output)
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
43
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a'
R:a
C:a
C:a
a
a+1 a+2 a+3
a+1
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
R:b
Bank 3
Active
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
CLK
BS
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
BS
a+1 a+2 a+3
a
a+3
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
VIH
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
DQ (input)
DQ (output)
DQ (input)
DQ (output)
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
/CS
/CAS
/WE
BS
Address
UDQM
LDQM
DQ (input)
DQ (output)
High-Z
RP
Precharge
If needed
Auto Refresh
Active
Bank 0
t
RC
t
RC
t
Auto Refresh
Read
Bank 0
R:a
C:a
A10=1
/RAS
a
a+1
VIH
Refresh cycle and
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
44
Self Refresh Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
UDQM
LDQM
DQ (input)
DQ (output)
Precharge command
If needed
Self refresh entry
command
Auto
refresh
Self refresh exit
ignore command
or No operation
CKE Low
A10=1
RC
t
RP
t
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
BL = 4
= VIH or VIL
High-Z
Next
clock
enable
RC
t
Next
clock
enable
lSREX
Self refresh entry
command
Clock Suspend Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
a
a+1 a+2
a+3
b
b+1 b+2
R:a
C:a R:b
C:b
a
a+1 a+2
b
b+1 b+2 b+3
C:b
Bank0
Active
Active clock
suspend start
Active clock
supend end
Bank0
Read
Bank3
Active
Read suspend
start
Read suspend
end
Bank0
Precharge
Bank3
Read
Earliest Bank3
Precharge
Bank0
Write
Bank0
Active
Active clock
suspend start
Active clock
suspend end
Bank3
Active
Write suspend
start
Write suspend
end
Bank3
Write
Bank0
Precharge
Earliest Bank3
Precharge
b+3
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
CLK
BS
CKE
/RAS
/CS
/CAS
/WE
Address
UDQM, LDQM
BS
a+3
High-Z
High-Z
tHI
tSI
tSI
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
DQ (output)
DQ (input)
DQ (output)
DQ (input)
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
45
Power Down Mode
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
UDQM
LDQM
DQ (input)
DQ (output)
Precharge command
If needed
Power down entry
Active Bank 0
Power down
mode exit
CKE Low
R: a
A10=1
RP
t
High-Z
Power down cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Initialization Sequence
7
8
9
10
52
53
54
48
49
50
51
Auto Refresh
Bank active
If needed
RC
t
RC
t
Auto Refresh
Valid
0
1
2
3
4
5
6
CLK
CKE
/CS
/RAS
/CAS
/WE
Address
UDQM
LDQM
DQ
valid
l
MRD
tRP
All banks
Precharge
Mode register
Set
VIH
VIH
55
High-Z
code
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
46
Package Drawing
54-pin Plastic TSOP(ll)
Solder plating: Lead free (Sn-Bi)
Unit: mm
ECA-TS2-0168-01
0.16
M S
S
S
A
A
B
B
0.10
0.80
10.16
54
28
1
27
22.22 0.10*
1
1.0
0.05
1.2 max.
11.76
0.20
0.10
0 to 8
0.91 max.
0.09 to 0.21
0.25 to 0.45
0.40 to 0.75
0.80
Nom
0.25
+0.08
-
0.05
PIN#1 ID
Note: 1. This dimension does not include mold protrusions or gate burrs.
Mold protrusions and gate burrs shall not exceed 0.20mm per side.
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
47
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS1216AGTA.
Type of Surface Mount Device
EDS1216AGTA: 54-pin Plastic TSOP(ll) < Lead free (Sn-Bi) >
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
48
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
EDS1216AGTA
Preliminary Data Sheet E0847E20 (Ver. 2.0)
49
M01E0107
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