Document Outline
- COVER
- Description
- Features
- Pin Configurations
- Ordering Information
- Part Number
- Electrical Specifications
- Absolute Maximum Ratings
- Recommended DC Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- Test Conditions
- Relationship Between Frequency and Minimum Latency
- Block Diagram
- Pin Function
- Command Operation
- Truth Table
- Command Truth Table
- DQM Truth Table
- CKE Truth Table
- Function Truth Table
- Command Truth Table for CKE
- Simplified State Diagram
- Programming Mode Registers
- Mode Register
- Burst Length and Sequence
- Address Bits of Bank-Select and Precharge
- Power-up sequence
- Power-up sequence
- Initialization sequence
- Operation of the SDRAM
- Read/Write Operations
- Auto Precharge
- Command Intervals
- DQM Control
- Refresh
- Others
- Timing Waveforms
- Read Cycle
- Write Cycle
- Mode Register Set Cycle
- Read Cycle/Write Cycle
- Read/Single Write Cycle
- Read/Burst Write Cycle
- Auto Refresh Cycle
- Self Refresh Cycle
- Clock Suspend Mode
- Power Down Mode
- Initialization Sequence
- Package Drawing
- Recommended Soldering Conditions
Document No. E0350E20 (Ver. 2.0)
Date Published August 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2004
DATA SHEET
128M bits SDRAM
EDS1232AASE (4M words
32 bits)
Description
The EDS1232AA is a 128M bits SDRAM organized as
1,048,576 words
32 bits
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 90-ball FBGA (
BGA
).
Features
3.3V power supply
Clock frequency: 166MHz (max.)
Single pulsed /RAS
32 organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8 and full
page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
Refresh cycles: 4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
FBGA(
BGA) package
with lead free solder (Sn-Ag-Cu)
Pin Configurations
/xxx indicate active low signal.
DQ26
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
/RAS
(Top view)
DQM1
NC
NC
/CAS
/WE DQM0
VDDQ DQ8
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
DQ13 DQ15 VSS
VDD
DQ0
DQ2
90-ball FBGA (
BGA)
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
EDS1232AASE
Data Sheet E0350E20 (Ver. 2.0)
2
Ordering Information
Part number
Supply
voltage
Organization
(words
bits)
Internal Banks
Clock frequency
MHz (max.)
/CAS latency
Package
EDS1232AASE-60-E 3.3V
4M
32
4
166
133
3
2
90-ball FBGA
(
BGA)
EDS1232AASE-75-E
133
100
3
2
EDS1232AASE-60L-E
166
133
3
2
EDS1232AASE-75L-E
133
100
3
2
Part Number
Elpida Memory
Density / Bank
12: 128M/4-Bank
Bit Organization
32: x32
Voltage, Interface
A: 3.3V, LVTTL
Die Rev.
Package
SE: FBGA
(
BGA with back cover)
Speed
60: 166MHz/CL3
133MHz/CL2
75: 133MHz/CL3
100MHz/CL2
Spec. Detail
Blank: Normal
L: Low Power
Product Code
S: SDRAM
Type
D: Monolithic Device
E D S 12 32 A A SE - 60 L - E
Environment Code
Blank: Sn-Pb Solder
E: Lead Free
EDS1232AASE
Data Sheet E0350E20 (Ver. 2.0)
3
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram ...............................................................................................................................................9
Pin Function.................................................................................................................................................10
Command Operation ...................................................................................................................................11
Truth Table ..................................................................................................................................................15
Simplified State Diagram .............................................................................................................................21
Programming Mode Registers.....................................................................................................................22
Mode Register .............................................................................................................................................23
Power-up sequence.....................................................................................................................................26
Operation of the SDRAM.............................................................................................................................27
Timing Waveforms.......................................................................................................................................43
Package Drawing ........................................................................................................................................50
Recommended Soldering Conditions ..........................................................................................................51
EDS1232AASE
Data Sheet E0350E20 (Ver. 2.0)
4
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter Symbol
Rating
Unit
Note
Voltage on any pin relative to VSS
VT
0.5 to +4.6
V
Supply voltage relative to VSS
VDD, VDDQ
0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70
C)
Parameter Symbol
min.
typ.
max.
Unit
Notes
Supply
voltage
VDD,
VDDQ
3.0 3.3 3.6 V
VSS
0 0 0 V
Input high voltage
VIH
2.0
VDD
+
0.3*
1
V
Input low voltage
VIL
0.3*
2
0.8 V
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width
5ns).
2. VIL (min.) = 1.5V (pulse width
5ns).
EDS1232AASE
Data Sheet E0350E20 (Ver. 2.0)
5
DC Characteristics 1 (TA = 0 to +70
C, VDD, VDDQ = 3.3V
0.3V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
(CL = 2)
IDD1
-60
-75
120
105
mA 1
(CL = 3)
IDD1
-60
-75
120
105
mA
Burst length = 1
tRC
tRC (min.)
IO = 0mA
One bank active
Standby current in power down
IDD2P
1
mA
Standby current in power down
(input signal stable)
IDD2PS
1
mA
CKE
VIL (max.) tCK = 15ns
CKE
VIL (max.) tCK =
Standby current in non power
down
IDD2N
20
mA
CKE
VIH (min.) tCK = 15ns
CS
VIH (min.)
Input signals are changed one
time during 30ns
Standby current in non power
down
(input signal stable)
IDD2NS
8
mA CKE
VIH (min.) tCK =
Active standby current in power
down
IDD3P
5
mA CKE
VIL (max.) tCK = 15ns
Active standby current in power
down (input signal stable)
IDD3PS
4
mA CKE
VIL (max.), tCK =
Active standby current in non
power down
IDD3N
25
mA
CKE
VIH (min.), tCK = 15 ns,
/CS
VIH (min.),
Input signals are changed one
time during 30ns.
Active standby current in non
power down
(input signal stable)
IDD3NS
15
mA CKE
VIH (min.), tCK =
,
Burst operating current
IDD4
-60
-75
200
180
mA
tCK
tCK (min.),
IO = 0mA, All banks active
2
Refresh current
IDD5
-60
-75
240
210
mA tRC
tRC (min.)
3
Self refresh current
IDD6
2.0
mA
VIH
VDD
-
0.2V,
VIL
GND + 0.2V
Self refresh current
(L-version)
IDD6 -xxL
0.6
mA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK
(min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
DC Characteristics 2 (TA = 0 to +70
C, VDD, VDDQ = 3.3V
0.3V, VSS, VSSQ = 0V)
Parameter Symbol
min.
max.
Unit
Test
condition
Notes
Input leakage current
ILI
1.0
1.0
A
0 = VIN = VDDQ, VDDQ = VDD,
All other pins not under test = 0V
Output leakage current
ILO
1.5
1.5
A
0 = VIN = VDDQ DOUT is disabled
Output high voltage
VOH
2.4
--
V
IOH = 2 mA
Output low voltage
VOL
--
0.4
V
IOL = 2 mA
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