Document Outline
- COVER
- Description
- Features
- Pin Configurations
- Ordering Information
- Part Number
- Electrical Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- Test Conditions
- Relationship Between Frequency and Minimum Latency
- Block Diagram
- Pin Function
- Command Operation
- Truth Table
- Command Truth Table
- DQM Truth Table
- CKE Truth Table
- Function Truth Table
- Command Truth Table for CKE
- Simplified State Diagram
- Programming Mode Registers
- Mode Register
- Burst Length and Sequence
- Address Bits of Bank-Select and Precharge
- Power-up sequence
- Operation of the SDRAM
- Read/Write Operations
- Auto Precharge
- Command Intervals
- DQM Control
- Refresh
- Others
- Timing Waveforms
- Read Cycle
- Write Cycle
- Mode Register Set Cycle
- Read Cycle/Write Cycle
- Read/Single Write Cycle
- Read/Burst Write Cycle
- Auto Refresh Cycle
- Self Refresh Cycle
- Clock Suspend Mode
- Power Down Mode
- Initialization Sequence
- Package Drawing
- Recommended Soldering Conditions
Document No. E0305E30 (Ver. 3.0)
Date Published September 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002-2004
DATA SHEET
128M bits SDRAM
WTR (Wide Temperature Range)
EDS1232AATA-TI (4M words
32 bits)
Description
The EDS1232AA is a 128M bits SDRAM organized as
1,048,576 words
32 bits
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 86-pin plastic TSOP (II).
Features
3.3V power supply
Clock frequency: 166MHz (max.)
Single pulsed /RAS
32 organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8 and full
page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
Refresh cycles: 4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Ambient temperature range: 40 to +85
C
Pin Configurations
/xxx indicates active low signal.
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
A11
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
86-pin Plastic TSOP(II)
Address inputs
Bank select
Data input/output
Chip select
Row address strobe
Column address strobe
Write enable
A0 to A11,
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQ mask enable
Clock enable
Clock input
Supply voltage
Ground
Supply voltage
for DQ
Ground for DQ
No connection
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
2
Ordering Information
Part number
Supply
voltage
Organization
(words
bits)
Internal Banks
Clock frequency
MHz (max.)
/CAS latency
Package
EDS1232AATA-60TI 3.3V
4M
32
4
166
133
3
2
86-pin plastic
TSOP (II)
EDS1232AATA-75TI
133
100
3
2
Part Number
Elpida Memory
Density / Bank
12: 128M/4 Banks
Bit Organization
32: x32
Voltage, Interface
A: 3.3V, LVTTL
Die Rev.
Package
TA: TSOP (II)
Speed
60: 166MHz/CL3
133MHz/CL2
75: 133MHz/CL3
100MHz/CL2
Product Code
S: SDRAM
Type
D: Monolithic Device
E D S 12 32 A A TA - 60 TI
Spec. Detail
TI: WTR (
-
40 to +85
C)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
3
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram ...............................................................................................................................................9
Pin Function.................................................................................................................................................10
Command Operation ...................................................................................................................................11
Truth Table ..................................................................................................................................................15
Simplified State Diagram .............................................................................................................................21
Programming Mode Registers.....................................................................................................................22
Mode Register .............................................................................................................................................23
Power-up sequence.....................................................................................................................................26
Operation of the SDRAM.............................................................................................................................27
Timing Waveforms.......................................................................................................................................43
Package Drawing ........................................................................................................................................50
Recommended Soldering Conditions ..........................................................................................................51
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
4
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Parameter Symbol
Rating
Unit
Note
Voltage on any pin relative to VSS
VT
0.5 to +4.6
V
Supply voltage relative to VSS
VDD, VDDQ
0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 40 to +85
C)
Parameter Symbol
min.
typ.
max.
Unit
Notes
Supply
voltage
VDD,
VDDQ
3.0 3.3 3.6 V
VSS
0 0 0 V
Input high voltage
VIH
2.0
VDD
+
0.3*
1
V
Input low voltage
VIL
0.3*
2
0.8 V
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width
5ns).
2. VIL (min.) = 1.5V (pulse width
5ns).
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
5
DC Characteristics 1 (TA = 40 to +85
C, VDD, VDDQ = 3.3V
0.3V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
(CL = 2)
IDD1
-60
-75
120
105
mA 1
(CL = 3)
IDD1
-60
-75
120
105
mA
Burst length = 1
tRC
tRC (min.)
IO = 0mA
One bank active
Standby current in power down
IDD2P
1
mA
Standby current in power down
(input signal stable)
IDD2PS
1
mA
CKE
VIL (max.) tCK = 15ns
CKE
VIL (max.) tCK =
Standby current in non power
down
IDD2N
20
mA
CKE
VIH (min.) tCK = 15ns
CS
VIH (min.)
Input signals are changed one
time during 30ns
Standby current in non power
down
(input signal stable)
IDD2NS
8
mA CKE
VIH (min.) tCK =
Active standby current in power
down
IDD3P
5
mA CKE
VIL (max.) tCK = 15ns
Active standby current in power
down (input signal stable)
IDD3PS
4
mA CKE
VIL (max.), tCK =
Active standby current in non
power down
IDD3N
25
mA
CKE
VIH (min.), tCK = 15 ns,
/CS
VIH (min.),
Input signals are changed one
time during 30ns.
Active standby current in non
power down
(input signal stable)
IDD3NS
15
mA CKE
VIH (min.), tCK =
,
Burst operating current
IDD4
-60
-75
200
180
mA
tCK
tCK (min.),
IO = 0mA, All banks active
2
Refresh current
IDD5
-60
-75
240
210
mA tRC
tRC (min.)
3
Self refresh current
IDD6
2.0
mA
VIH
VDD
-
0.2V,
VIL
GND + 0.2V
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK
(min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
DC Characteristics 2 (TA = 40 to +85
C, VDD, VDDQ = 3.3V
0.3V, VSS, VSSQ = 0V)
Parameter Symbol
min.
max.
Unit
Test
condition
Note
Input leakage current
ILI
1.0
1.0
A
0
VIN
VDDQ, VDDQ = VDD, All
other pins not under test = 0V
Output leakage current
ILO
1.5
1.5
A
0
VOUT
VDDQ, DOUT is disabled
Output high voltage
VOH
2.4
--
V
IOH = 2 mA
Output low voltage
VOL
--
0.4
V
IOL = 2 mA
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
6
Pin Capacitance (TA = 25C, f = 1MHz)
Parameter Symbol
Pins
min.
typ.
max.
Unit
Note
Input
capacitance
CI1 Address
2.5 -- 4.0 pF
CI2
CLK, CKE, /CS, /RAS,
/CAS, /WE, DQM
2.5 -- 4.0 pF
Data
input/output
capacitance
CI/O
DQ
4.0 -- 6.5 pF
AC Characteristics (TA = 40 to +85
C, VDD, VDDQ = 3.3V
0.3V, VSS, VSSQ = 0V)
-60
-75
Parameter
Symbol
min. max. min. max. Unit
Note
System clock cycle time
(CL = 2)
tCK
7.5 -- 10 -- ns
(CL = 3)
tCK
6
--
7.5
--
ns
CLK high pulse width
tCH
2.5
--
2.5
--
ns
CLK low pulse width
tCL
2.5
--
2.5
--
ns
Access time from CLK
tAC
--
5.4
--
5.4
ns
Data-out
hold
time
tOH
2 -- 2 -- ns
CLK to Data-out low impedance
tLZ
0
--
0
--
ns
CLK to Data-out high impedance
tHZ
2
5.4
2
5.4
ns
Input
setup
time
tSI 1.5 -- 1.5 -- ns
Input
hold
time
tHI 0.8 -- 0.8 -- ns
CKE setup time (Power down exit)
tCKSP
1.5
--
1.5
--
ns
ACT to REF/ACT command period
(operation)
tRC 60
67.5
ns
(refresh) tRC
60
67.5
ns
Active to Precharge command period
tRAS
42
120000
45
120000
ns
Active command to column command
(same bank)
tRCD 15
20
ns
Precharge to active command period
tRP
15
20
ns
Write recovery or data-in to precharge
lead time
tDPL 12
15
ns
Last data into active latency
tDAL
2CLK +
15ns
2CLK +
20ns
Active (a) to Active (b) command period tRRD
12
15
ns
Mode register set cycle time
tRSC
2
2
CLK
Transition time (rise and fall)
tT
0.5
30
0.5
30
ns
Refresh period
(4096 refresh cycles)
tREF
-- 64 -- 64 ms
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
7
Test Conditions
AC high level input voltage / low level input voltage: 2.4V / 0.4V
Input timing measurement reference level: 1.4V
Transition time (Input rise and fall time): 1ns
Output timing measurement reference level: 1.4V
Termination voltage (Vtt): 1.4V
tCK
tCH
tCL
2.4V
1.4V
0.4V
CLK
2.4V
1.4V
0.4V
Input
tSETUP tHOLD
Output
tAC
tOH
Output
Z = 50
Vtt
30pF
50
Input Waveforms and Output Load
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
8
Relationship Between Frequency and Minimum Latency
Parameter
-60
-75
Frequency
(MHz)
166 133 133 100
tCK (ns)
Symbol
6
7.5
7.5
10
Unit
Notes
Active command to column command
(same bank)
l
RCD
3 2 3 2 tCK 1
Active command to active command
(same bank)
l
RC 10 8 9 7 tCK 1
Active command to precharge command
(same bank)
l
RAS
7 6 6 5 tCK 1
Precharge command to active command
(same bank)
l
RP 3 2 3 2 tCK 1
Write recovery or data-in to precharge
command (same bank)
l
DPL
2 2 2 2 tCK 1
Active command to active command
(different bank)
l
RRD
2 2 2 2 tCK 1
Self refresh exit time
l
SREX
1 1 1 1 tCK 2
Last data in to active command
(Auto precharge, same bank)
l
DAL
5 4 5 4 tCK =
[lDPL
+
lRP]
Self refresh exit to command input
l
SEC
10 8 9 7 tCK
= [lRC]
3
Precharge command to high impedance
(CL = 2)
l
HZP
2
2
tCK
(CL = 3)
l
HZP
3 3 3 3 tCK
Last data out to active command
(auto precharge) (same bank)
l
APR
1 1 1 1 tCK
Last data out to precharge
(early precharge)
(CL = 2)
l
EP
1
1
tCK
(CL = 3)
l
EP 2 2 2 2 tCK
Column command to column command
l
CCD
1 1 1 1 tCK
Write command to data in latency
l
WCD
0 0 0 0 tCK
DQM to data in
l
DID
0 0 0 0 tCK
DQM to data out
l
DOD
2 2 2 2 tCK
CKE to CLK disable
l
CLE
1 1 1 1 tCK
Register set to active command
l
MRD
2 2 2 2 tCK
/CS to command disable
l
CDD
0 0 0 0 tCK
Power down exit to command input
l
PEC
1 1 1 1 tCK
Notes: 1.
l
RCD to
l
RRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
9
Block Diagram
Clock
Generator
Mode
Register
Command Decoder
Control Logic
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Data Control Circuit
Latch Circuit
Input & Output
Buffer
DQ
DQM
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Bank 3
Bank 2
Bank 1
Sense Amplifier
Column Decoder &
Latch Circuit
Bank 0
Row Decoder
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
10
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to 7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM
high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In
write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
11
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Row
Row
(Bank select)
Row Address Strobe and Bank Activate Command
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
12
Precharge command (/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are
precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the Synchronous DRAM can't accept the activate command to the precharging bank during tRP
(precharge to activate command period). This command corresponds to a conventional DRAM's /RAS rising.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
(Precharge select)
Precharge Command
Write command (/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the burst start address given by the column
address to begin the burst write operation. The first write data in burst mode can input with this command with
subsequent data on following clocks.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Col.
Column Address and Write Command
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
13
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Col.
Column Address and and Read Command
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the Synchronous DRAM cannot accept any other command
Add
A10
BA0, BA1
/WE
/CAS
/RAS
/CS
CKE
CLK
H
(Bank select)
CBR (auto) Refresh Command
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
14
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the
Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control. Before executing self refresh, all banks must be
precharged.
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
(Bank select)
Self Refresh Entry Command
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
(Bank select)
H
Burst Stop Command in Full Page Mode
No operation (/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or terminate by this command.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
No Operation
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
15
Truth Table
Command Truth Table
CKE
BA0,
A9
-
A0,
Function
Symbol
n
1 n
/CS /RAS /CAS /WE BA1 A10 A11
Device deselect
DESL
H
H
No operation
NOP
H
L H H H
Burst stop
BST
H
L H H L
Read READ
H
L H L H V L V
Read with auto precharge
READA
H
L H L H V H V
Write WRIT
H
L H L L V L V
Write with auto precharge
WRITA
H
L H L L V H V
Bank activate
ACT
H
L L H H V V V
Precharge select bank
PRE
H
L L H L V L
Precharge all banks
PALL
H
L L H L
H
Mode register set
MRS
H
L L L L L L V
Remark: H: VIH. L: VIL.
: VIH or VIL, V = Valid data
DQM Truth Table
CKE
DQM
Function
Symbol
n 1
n
0 1 2 3
Data write / output enable
ENB
H
L L L L
Data mask / output disable
MASK
H
H H H H
DQ0 to DQ7 write enable/output enable
ENB0
H
L
DQ8 to DQ15 write enable/output enable
ENB1
H
L
DQ16 to DQ23 write enable/output enable
ENB2
H
L
DQ24 to DQ31 write enable/output enable
ENB3
H
L
DQ0 to DQ7 write inhibit/output disable
MASK0
H
H
DQ8 to DQ15 write inhibit/output disable
MASK 1
H
H
DQ16 to DQ23 write inhibit/output disable
MASK 2
H
H
DQ24 to DQ31 write inhibit/output disable
MASK 3
H
H
Remark: H: VIH. L: VIL.
: VIH or VIL
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
16
CKE Truth Table
CKE
Current state
Function
Symbol
n 1
n
/CS
/RAS
/CAS
/WE
Address
Activating
Clock suspend mode entry
H
L
Any Clock
suspend
mode
L
L
Clock suspend
Clock suspend mode exit
L
H
Idle
CBR
(auto)
refresh
command
REF H H L L L H
Idle
Self
refresh
entry
SELF
H L L L L H
Self refresh
Self refresh exit
L
H
L
H
H
H
L
H
H
Idle
Power
down
entry
H L L H H H
H
L
H
Power down
Power down exit
L
H
H
L H L H H H
Remark: H: VIH. L: VIL.
: VIH or VIL
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
17
Function Truth Table*
1
Current state
/CS /RAS /CAS /WE Address
Command
Operation
Notes
Idle H
DESL
Nop or power down
2
L
H
H
NOP or BST
Nop or power down
2
L H L H BA,
CA,
A10
READ/READA ILLEGAL 3
L H L L BA,
CA,
A10
WRIT/ WRITA ILLEGAL 3
L L H H BA,
RA
ACT
Row
activating
L L H L BA,
A10 PRE/PALL Nop
L L L H
REF/SELF
CBR (auto) refresh or self refresh
4
L L L L OPCODE MRS
Mode
register
accessing
Row active
H
DESL
Nop
L
H
H
NOP
or
BST
Nop
L H L H BA,
CA,
A10
READ/READA Begin read: Determine AP
5
L H L L BA,
CA,
A10
WRIT/ WRITA Begin write: Determine AP
5
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL Precharge
6
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Read H
DESL
Continue burst to end
Row active
L H H H
NOP
Continue burst to end
Row active
L H H L
BST
Burst
stop
Row active
L
H
L
H
BA, CA, A10 READ/READA Terminate burst, new read: Determine AP 7
L
H
L
L
BA, CA, A10 WRIT/WRITA
Terminate burst, begin write: Determine AP 7, 8
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL Terminate
burst,
Precharging
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Write H
DESL
Continue burst to end
Write recovering
L H H H
NOP
Continue burst to end
Write recovering
L H H L
BST
Burst
stop
Row active
L
H
L
H
BA, CA, A10 READ/READA Terminate burst, start read : Determine AP
7, 8
L H L L BA,
CA,
A10
WRIT/WRITA
Terminate
burst,
new
write
:
Determine
AP
7
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL Terminate
burst,
Precharging
9
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
18
Current state
/CS /RAS /CAS /WE Address
Command
Operation
Notes
Read with auto
H
DESL
Continue burst to end
Precharging
precharge
L H H H
NOP
Continue burst to end
Precharging
L H H L
BST
ILLEGAL
L H L H BA,
CA,
A10
READ/READA ILLEGAL 3
L H L L BA,
CA,
A10
WRIT/ WRITA ILLEGAL 3
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL ILLEGAL
3
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Write with auto
precharge
H
DESL
Continue burst to end
Write
recovering with auto precharge
L H H H
NOP
Continue burst to end
Write
recovering with auto precharge
L H H L
BST
ILLEGAL
L H L H BA,
CA,
A10
READ/READA ILLEGAL 3
L H L L BA,
CA,
A10
WRIT/ WRITA ILLEGAL 3
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL ILLEGAL
3
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Precharging H
DESL
Nop
Enter idle after tRP
L H H H
NOP
Nop
Enter idle after tRP
L H H L
BST
ILLEGAL
L H L H BA,
CA,
A10
READ/READA
ILLEGAL
3
L H L L BA,
CA,
A10
WRIT/WRITA
ILLEGAL
3
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL Nop
Enter idle after tRP
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Row activating
H
DESL
Nop
Enter bank active after tRCD
L H H H
NOP
Nop
Enter bank active after tRCD
L H H L
BST
ILLEGAL
L H L H BA,
CA,
A10
READ/READA
ILLEGAL
3
L H L L BA,
CA,
A10
WRIT/WRITA
ILLEGAL
3
L L H H BA,
RA
ACT
ILLEGAL
3,
10
L L H L BA,
A10 PRE/PALL ILLEGAL
3
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
19
Current state
/CS /RAS /CAS /WE Address
Command
Operation
Notes
Write recovering H
DESL
Nop
Enter row active after tDPL
L H H H
NOP
Nop
Enter row active after tDPL
L H H L
BST
Nop
Enter row active after tDPL
L H L H BA,
CA,
A10
READ/READA Start read, Determine AP
8
L H L L BA,
CA,
A10
WRIT/ WRITA New write, Determine AP
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL ILLEGAL
3
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Write recovering H
DESL
Nop
Enter precharge after tDPL
with
auto
L H H H
NOP
Nop
Enter precharge after tDPL
precharge
L H H L
BST
Nop
Enter row active after tDPL
L H L H BA,
CA,
A10
READ/READA
ILLEGAL
L H L L BA,
CA,
A10
WRIT/WRITA
ILLEGAL
3,
8
L L H H BA,
RA
ACT
ILLEGAL
3
L L H L BA,
A10 PRE/PALL ILLEGAL
3
L L L H
REF/SELF
ILLEGAL
L L L L OPCODE MRS
ILLEGAL
Refresh
H
DESL
Nop
Enter idle after tRC
L H H H
NOP/BST
Nop
Enter idle after tRC
L H H L
READ/READA
ILLEGAL
L H L H
ACT/PRE/PALL ILLEGAL
L H L L
REF/SELF/MRS ILLEGAL
Mode register
H
DESL
Nop
Enter idle after tRSC
accessing
L H H H
NOP
Nop
Enter idle after tRSC
L H H L
BST
ILLEGAL
L H L H
READ/READA
ILLEGAL
L L L L
ACT/PRE/PLL/
REF/SELF/MRS
ILLEGAL
Remark: H: VIH. L: VIL.
: VIH or VIL, V = Valid data
BA: Bank Address, CA: Column Address, RA: Row Address
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down
mode.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.
9. Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
20
Command Truth Table for CKE
CKE
Current State
n 1 n
/CS /RAS /CAS /WE Address
Operation
Notes
Self refresh
H
INVALID, CLK (n 1) would exit self refresh
L
H
H
Self refresh recovery
L
H
L
H
H
Self refresh recovery
L
H
L
H
L
ILLEGAL
L
H
L
L
ILLEGAL
L
L
Continue self refresh
Self refresh recovery H
H
H
Idle
after
tRC
H H L H H
Idle
after
tRC
H H L H L
ILLEGAL
H
H
L
L
ILLEGAL
H
L
H
ILLEGAL
H L L H H
ILLEGAL
H L L H L
ILLEGAL
H
L
L
L
ILLEGAL
Power down
H
INVALID, CLK (n 1) would exit power down
L
H
H
EXIT power down
L
H
L
H
H
H
EXIT power down
L
L
Continue power down mode
All banks idle
H
H
H
Refer to operations in Function Truth Table
H
H
L
H
Refer to operations in Function Truth Table
H
H
L
L
H
Refer to operations in Function Truth Table
H H L L L H
CBR
(auto)
Refresh
H
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
Begin power down next cycle
H
L
L
H
Refer to operations in Function Truth Table
H
L
L
L
H
Refer to operations in Function Truth Table
H L L L L H
Self
refresh
1
H
L
L
L
L
L
OPCODE Refer to operations in Function Truth Table
L
H
Exit power down next cycle
L
L
Power
down
1
Row active
H
Refer to operations in Function Truth Table
L
Clock
suspend
1
Any state other than H
H
Refer to operations in Function Truth Table
listed above
H
L
Begin clock suspend next cycle
2
L
H
Exit clock suspend next cycle
L
L
Maintain
clock
suspend
Remark: H = VIH, L = VIL,
= VIH or VIL
Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Function Truth Table.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
21
Simplified State Diagram
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
Precharge
Auto precharge
PRE
Read with
Auto precharge
Read
BST
BST
PRE (Precharge termination)
PRE (Precharge termination)
ACT
MRS
REF
CKE
CKE
SELF
SELF exit
IDLE
Mode
Register
Set
CBR(auto)
Refresh
ROW
ACTIVE
Self
Refresh
Power
Down
Active
Power
Down
Precharge
READ
READA
READ
SUSPEND
READA
SUSPEND
WRITE
WRITEA
WRITE
SUSPEND
WRITEA
SUSPEND
POWER
ON
Write
Read
Automatic sequence
Manual input
CKE
CKE
Read
Write
W
rite with
Write
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
22
Programming Mode Registers
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0 and
BA1 as data inputs. The registers retain data until it is re-programmed, or the device loses power.
The mode register has three fields;
Options
: A11 through A7, BA0, BA1
/CAS latency : A6 through A4
Wrap type
: A3
Burst length
: A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before
the data will be available. The value is determined by the frequency of the clock and the speed grade of the device.
"Relationship between Frequency and Latency" shows the relationship of /CAS latency to the clock period and the
speed grade of the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed.
This order is programmable as either
"Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing.
"Burst Length Sequence" shows the addressing sequence for each burst length using them. Both sequences
support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
23
Mode Register
WT = 1
1
2
4
8
R
R
R
R
1
0
0
0
0
JEDEC Standard Test Set (refresh counter test)
BL
WT
LTMODE
0
0
1
x
x
Burst Read and Single Write
(for Write Through Cache)
0
1
Use in future
V
V
V
V
V
V
1
V
1
x
x
x
Vender Specific
BL
WT
LTMODE
0
0
0
0
0
Mode Register Set
V = Valid
x = Don't care
WT = 0
1
2
4
8
R
R
R
Full page
Bits2-0
000
001
010
011
100
101
110
111
Burst length
Sequential
Interleave
0
1
Wrap type
/CAS latency
R
R
2
3
R
R
R
R
Bits6-4
000
001
010
011
100
101
110
111
Latency
mode
0
0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
BA0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
BA0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
BA0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
BA0
A0
A1
A2
A3
A4
A5
A7
A6
A8
A9
A10
A11
BA1
BA0
x
x
x
x
0
0
Remark R : Reserved
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A11,
BA0, BA1
Mode Register Set
Mode Register Set Timing
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
24
Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
[Burst of Four]
Starting address
(column address A1 to A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
[Burst of Eight]
Starting address
(column address A2 to A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
25
Address Bits of Bank-Select and Precharge
A11
A10
A9
A8
A7
A6
A4
A5
A3
A2
A1
A0
Row
(Activate command)
A11
A10
A9
A8
A7
A6
A4
A5
A3
A2
A1
A0
(Precharge command)
disables Auto-Precharge
(End of Burst)
0
enables Auto-Precharge
(End of Burst)
1
x
A10
A9
A8
A7
A6
A4
A5
A3
A2
A1
A0
Col.
(/CAS strobes)
x : Don't care
Select Bank 0
"Activate" command
0
Select Bank 1
"Activate" command
0
1
1
0
1
0
1
BA1
BA0
BA1
BA0
BA1
BA0
Result
Select Bank 2
"Activate" command
Select Bank 3
"Activate" command
enables Read/Write
commands for Bank 0
0
enables Read/Write
commands for Bank 1
0
1
1
0
1
0
1
Result
enables Read/Write
commands for Bank 2
enables Read/Write
commands for Bank 3
Result
Precharge Bank 0
Precharge Bank 1
Precharge Bank 2
Precharge Bank 3
Precharge All Banks
A10
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
BA1
BA0
BA1
BA0
BA1
BA0
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
26
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these
pins go high before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 s or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
VDD, VDDQ
Power up sequence
Initialization sequence
100
s
0 V
Low
Low
Low
CKE, DQM
CLK
/CS, DQ
200
s
Power stabilize
Power-up sequence and Initialization sequence
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
27
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
READ
CLK
Command
DQ
ACT
Row
Column
Address
CL = 2
CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
tRCD
CL = /CAS latency
Burst Length = 4
/CAS Latency
READ
CLK
Command
DQ
ACT
Row
Column
out 0
out 6
out 7
Address
out 0 out 1
out 4
out 5
out 0 out 1 out 2 out 3
BL = 1
out 0 out 1 out 2
out 3
BL = 2
BL = 4
BL = 8
tRCD
BL : Burst Length
/CAS Latency = 2
Burst Length
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
28
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
WRIT
CLK
Command
DQ
ACT
Row
Column
in 0
in 6
in 7
Address
in 1
in 4
in 5
in 3
BL = 1
BL = 2
BL = 4
BL = 8
tRCD
in 0
in 0
in 0
in 1
in 1
in 2
in 2
in 3
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CLK
Command
DQ
ACT
Row
Column
in 0
Address
tRCD
Single write
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
29
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by
l
APR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
l
APR
l
RAS
l
APR
CL=2 Command
CL=3 Command
DQ
DQ
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (
l
RAS) is required between previous active (ACT) command and internal precharge " ".
ACT
READA
ACT
out3
out2
out1
out0
l
RAS
ACT
READA
ACT
out3
out2
out1
out0
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of
l
DAL is
required between the final valid data input and input of next command.
CLK
Command
DQ
l
DAL
l
RAS
ACT
WRITA
in0
in1
in2
in3
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (
l
RAS) is required between previous active (ACT) command
and internal precharge " ".
Burst Write (BL = 4)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
30
CLK
Command
DQ
l
DAL
l
RAS
ACT
WRITA
in
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (
l
RAS) is required between previous active (ACT) command
and internal precharge " ".
Single Write
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
31
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
Command
DQ
(CL = 2)
DQ
(CL = 3)
READ
BST
out
out
out
out
out
out
High-Z
High-Z
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
Command
DQ
in
in
in
BST
WRITE
in
High-Z
Burst Stop at Write
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
32
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
DQ
out B3
Address
out B1 out B2
BS
ACT
Row
Column A
READ
READ
Column B
out A0 out B0
Bank0
Active
Column =A
Read
Column =B
Read
Column =A
Dout
Column =B
Dout
CL = 3
BL = 4
Bank 0
READ to READ Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
DQ
out B3
Address
out B1 out B2
BS
ACT
Row 0
Row 1
ACT
READ
Column A
out A0 out B0
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
READ
Column B
Bank0
Dout
Bank3
Dout
CL = 3
BL = 4
READ to READ Command Interval (different bank)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
33
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
DQ
in B3
Address
in B1
in B2
BS
ACT
Row
Column A
WRIT
WRIT
Column B
in A0
in B0
Bank0
Active
Column =A
Write
Column =B
Write
Burst Write Mode
BL = 4
Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
DQ
in B3
Address
in B1
in B2
BS
ACT
Row 0
Row 1
ACT
WRIT
Column A
in A0
in B0
Bank0
Active
Bank3
Active
Bank0
Write
Bank3
Write
WRIT
Column B
Burst Write Mode
BL = 4
WRITE to WRITE Command Interval (different bank)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
34
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
DQ (output)
in B2
in B3
READ
WRIT
in B0
in B1
High-Z
DQ (input)
CL=2
CL=3
DQM
BL = 4
Burst write
READ to WRITE Command Interval (1)
CLK
Command
DQ
READ
WRIT
CL=2
CL=3
DQM
2 clock
out
out
out
out
out
in
in
in
in
in
in
in
in
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
35
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
DQ (input)
WRIT
READ
in A0
out B1
out B2
out B3
out B0
DQ (output)
Column = A
Write
Column = B
Read
Column = B
Dout
/CAS Latency
DQM
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (1)
CLK
Command
DQ (input)
WRIT
READ
in A0
out B1
out B2
out B3
out B0
DQ (output)
Column = A
Write
Column = B
Read
Column = B
Dout
/CAS Latency
in A1
DQM
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
36
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
DQ
READA
READ
out A0
out A1
out B0
out B1
CL= 3
BL = 4
bank0
Read A
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
CLK
Command
BS
DQ
WRITA
WRIT
in B1
in B2
in B3
in A0
in A1
in B0
BL= 4
bank0
Write A
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
37
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-
precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
DQ (output)
DQ (input)
CL = 2
CL = 3
READA
WRIT
in B0
in B1
in B2
in B3
BL = 4
bank0
ReadA
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
DQM
High-Z
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
CLK
Command
BS
DQ (output)
DQ (input)
WRITA
READ
out B0
out B1
out B2
out B3
CL = 3
BL = 4
bank0
WriteA
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
DQM
in A0
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
38
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by
l
HZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by
l
EP must be assured as
an interval from the final data output to precharge command execution.
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=2
l
EP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=3
l
EP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
High-Z
l
HZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
Command
DQ
READ
PRE/PALL
out A0
l
HZP =3
High-Z
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
39
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
DQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
in A3
DQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
40
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
Bank 0
Active
ACT
ROW
ACT
ROW
Bank 0
Active
tRC
Bank Active to Bank Active for Same Bank
CLK
Command
Address
BS
Bank 0
Active
Bank 3
Active
ACT
ROW:0
ACT
ROW:1
tRRD
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than
l
MRD.
CLK
Command
Address
Mode
Register Set
Bank
Active
MRS
l
MRD
ACT
BS & ROW
OPCODE
Mode register set to Bank active command interval
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
41
DQM Control
The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively.
The timing of UDQM/LDQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes
Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding
data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.
Writing
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to
High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0
clock.
CLK
DQ
out 0
out 1
l
DOD = 2 Latency
out 3
DQM
High-Z
Reading
CLK
DQ
in 0
in 1
l
DID = 0 Latency
in 3
DQM
Writing
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
42
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-
refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a
self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or
within tREF (max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after
exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
43
Timing Waveforms
Read Cycle
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
CLK
CKE
/CS
tRAS
tRCD
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
/RAS
/CAS
/WE
BS
A10
Address
DQM
DQ (input)
DQ (output)
tHI
tSI
tCH t
tCK
tAC
tAC
CL
tAC
tOH
tOH
tOH
tOH
t
RP
t RC
/CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
= VOH or VOL
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
t
tLZ
VIH
tHZ
AC
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
44
Write Cycle
CLK
CKE
/CS
tRAS
tRCD
/RAS
/CAS
/WE
BS
A10
Address
DQ (input)
DQ (output)
tCH t
tCK
tHI
tHI
CL
t HI
tHI
tSI
tSI
tSI
tSI
tRP
tRC
tDPL
Bank 0
Write
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tHI
tSI
tSI
Bank 0
Active
Bank 0
Precharge
VIH
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
DQM
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
High-Z
b
b+3
b'
b'+1
b'+2
b'+3
l
MRD
valid
C: b'
code
l
RCD
l
RP
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
R: b
C: b
Output mask
VIH
l
RCD
= 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
45
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:b
C:b'
C:b"
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
DQ (output)
DQ (input)
CLK
BS
R:a
C:a
R:b
C:b
C:b'
C:b"
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3
Read
Bank 3
Read
Bank 3
Read
Bank 0
Precharge
Bank 3
Precharge
Bank 0
Active
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 3
Write
Bank 3
Write
Bank 0
Precharge
Bank 3
Precharge
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
DQ (input)
DQ (output)
BS
High-Z
High-Z
VIH
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
VIH
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
46
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a'
R:a
C:a
C:a
a
a
a
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
R:b
Bank 3
Active
C:a
Bank 0
Read
a
a+1 a+2 a+3
Bank 0
Write
Bank 0
Write
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
DQ (input)
DQ (output)
CLK
BS
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
BS
C:b
b
c
a+1
a+3
a+1 a+2 a+3
C:c
VIH
VIH
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
DQ (input)
DQ (output)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
47
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a'
R:a
C:a
C:a
a
a+1 a+2 a+3
a+1
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
R:b
Bank 3
Active
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
CLK
BS
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
BS
a+1 a+2 a+3
a
a+3
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
VIH
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
=
VIH or VIL
DQ (input)
DQ (output)
DQ (input)
DQ (output)
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
/CS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
High-Z
RP
Precharge
If needed
Auto Refresh
Active
Bank 0
t
RC
t
RC
t
Auto Refresh
Read
Bank 0
R:a
C:a
A10=1
/RAS
a
a+1
VIH
Refresh cycle and
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
48
Self Refresh Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
Precharge command
If needed
Self refresh entry
command
Auto
refresh
Self refresh exit
ignore command
or No operation
CKE Low
A10=1
RC
t
RP
t
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
BL = 4
= VIH or VIL
High-Z
Next
clock
enable
RC
t
Next
clock
enable
lSREX
Self refresh entry
command
Clock Suspend Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
a
a+1 a+2
a+3
b
b+1 b+2
R:a
C:a R:b
C:b
a
a+1 a+2
b
b+1 b+2 b+3
C:b
Bank0
Active
Active clock
suspend start
Active clock
supend end
Bank0
Read
Bank3
Active
Read suspend
start
Read suspend
end
Bank0
Precharge
Bank3
Read
Earliest Bank3
Precharge
Bank0
Write
Bank0
Active
Active clock
suspend start
Active clock
suspend end
Bank3
Active
Write suspend
start
Write suspend
end
Bank3
Write
Bank0
Precharge
Earliest Bank3
Precharge
b+3
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
CLK
BS
CKE
/RAS
/CS
/CAS
/WE
Address
DQM
BS
a+3
High-Z
High-Z
tHI
tSI
tSI
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
DQ (output)
DQ (input)
DQ (output)
DQ (input)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
49
Power Down Mode
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
Precharge command
If needed
Power down entry
Active Bank 0
Power down
mode exit
CKE Low
R: a
A10=1
RP
t
High-Z
Power down cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Initialization Sequence
7
8
9
10
52
53
54
48
49
50
51
Auto Refresh
Bank active
If needed
RC
t
RC
t
Auto Refresh
Valid
0
1
2
3
4
5
6
CLK
CKE
/CS
/RAS
/CAS
/WE
Address
DQM
DQ
valid
l
MRD
tRP
All banks
Precharge
Mode register
Set
VIH
VIH
55
High-Z
code
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
50
Package Drawing
86-pin Plastic TSOP (II)
0.50
1.2 max.
0.09 to 0.20
86
44
1
43
S
B
A
22.22
0.10
0.15 to 0.30
0.10
0.81 max.
0 to 8
PIN#1 ID
0.10
M S
S
A B
10.16
11.76
0.20
1.0
0.05
Unit: mm
ECA-TS2-0030-01
Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or
gate burrs shall not exceed 0.20mm per side.
0.10
0.60 0.15
0.80
Nom
0.25
+0.08
-
0.05
*
1
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
51
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS1232AATA.
Type of Surface Mount Device
EDS1232AATA: 86-pin Plastic TSOP (II)
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
52
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
EDS1232AATA-TI
Data Sheet E0305E30 (Ver. 3.0)
53
M01E0107
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
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compliance with the relevant laws and regulations.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
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