Document Outline
- COVER
- Description
- Features
- Pin Configurations
- Ordering Information
- Part Number
- Electrical Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics 1
- DC Characteristics 2
- Pin Capacitance
- AC Characteristics
- Test Conditions
- Relationship Between Frequency and Minimum Latency
- VIL/VIH Clamp
- IOL/IOH Characteristics
- Block Diagram
- Pin Function
- Command Operation
- Command Truth Table
- DQM Truth Table
- CKE Truth Table
- Function Truth Table
- Command Truth Table for CKE
- Simplified State Diagram
- Mode Register Configuration
- Power-up sequence
- Operation of the SDRAM
- Read/Write Operations
- Auto Precharge
- Burst Stop Command
- Command Intervals
- DQM Control
- Refresh
- Others
- Timing Waveforms
- Read Cycle
- Write Cycle
- Mode Register Set Cycle
- Read Cycle/Write Cycle
- Read/Single Write Cycle
- Read/Burst Write Cycle
- Auto Refresh Cycle
- Self Refresh Cycle
- Clock Suspend Mode
- Power Down Mode
- Initialization Sequence
- Package Drawing
- Recommended Soldering Conditions
Document No. E0248E10 (Ver. 1.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
PRELIMINARY DATA SHEET
256M bits SDRAM
WTR (Wide Temperature Range)
EDS2504APTA-TI (64M words
4 bits)
EDS2508APTA-TI (32M words
8 bits)
EDS2516APTA-TI (16M words
16 bits)
Description
The EDS2504AP is a 256M bits SDRAM organized as
16,777,216 words
4 bits
4 banks. The EDS2508
AP is a 256M bits SDRAM organized as 8,388,608
words
8 bits
4 banks. The EDS2516 AP is a 256M
bits SDRAM organized as 4194304 words
16 bits
4
banks. All inputs and outputs are referred to the rising
edge of the clock input. It is packaged in standard 54-
pin plastic TSOP (II).
Features
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, full page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
: DQM (EDS2504/08AP)
: UDQM, LDQM (EDS2516AP)
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Ambient temperature range: 40 to +85
C
Pin Configurations
/xxx indicates active low signal.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
54-pin TSOP
(Top view)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
X 8
X 16
X 4
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
A0 to A12,
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
EDS2504APTA/08APTA/16APTA-TI
Preliminary Data Sheet E0248E10 (Ver. 1.0)
2
Ordering Information
Part number
Mask
Version
Organization
(words
bits)
Internal Banks
Clock frequency
MHz (max.)
/CAS latency
Package
EDS2504APTA-7ATI
EDS2504APTA-75TI
P
64M
4
4
133
2, 3
3
54-pin Plastic
TSOP (II)
EDS2508APTA-7ATI
EDS2508APTA-75TI
32M
8
2, 3
3
EDS2516APTA-7ATI
EDS2516APTA-75TI
16M
16
2, 3
3
Part Number
Elpida Memory
Density & Bank
25: 256M/4 Banks
Bit Organization
04: x4
08: x8
16: x16
Interface
A: 3.3V, LVTTL
Mask Revision
Package
TA: TSOP (II)
Speed
7A: 133MHz/CL2, 3
75: 133MHz/CL3
100MHz/CL2
Function
S: SDRAM
Material Type
D: Mono
E D S 25 04 A P TA - 7A TI
Wide Temperature Range
TI:
-
40 to +85
C
EDS2504APTA/08APTA/16APTA-TI
Preliminary Data Sheet E0248E10 (Ver. 1.0)
3
CONTENTS
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................ 1
Pin Configurations ......................................................................................................................................... 1
Ordering Information ..................................................................................................................................... 2
Part Number .................................................................................................................................................. 2
Electrical Specifications................................................................................................................................. 4
Block Diagram ............................................................................................................................................... 8
Pin Function ................................................................................................................................................ 13
Command Operation ................................................................................................................................... 15
Simplified State Diagram............................................................................................................................. 23
Mode Register Configuration ...................................................................................................................... 24
Power-up sequence .................................................................................................................................... 25
Operation of the SDRAM ............................................................................................................................ 26
Timing Waveforms ...................................................................................................................................... 42
Package Drawing ........................................................................................................................................ 48
Recommended Soldering Conditions.......................................................................................................... 49
Revision History .......................................................................................................................................... 52
EDS2504APTA/08APTA/16APTA-TI
Preliminary Data Sheet E0248E10 (Ver. 1.0)
4
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 100
s and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Note
Voltage on any pin relative to VSS
VT
0.5 to VDD + 0.5 ( 4.6 (max.))
V
Supply voltage relative to VSS
VDD
0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating temperature
TA
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Notes: 1. Respect to VSS.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = 40 to +85
C)
Parameter
Symbol
min.
max.
Unit
Notes
Supply voltage
VDD, VDDQ
3.0
3.6
V
1, 2
VSS, VSSQ
0
0
V
3
Input high voltage
VIH
2.0
VDD + 0.3
V
1, 4
Input low voltage
VIL
0.3
0.8
V
1, 5
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VDD
and VDDQ pins must be on the same level.
3. The supply voltage with all VSS and VSSQ pins must be on the same level.
4. VIH (max.) = VDD + 2.0 V for pulse width 3ns at VDD.
5. VIL (min.) = VSS 2.0 V for pulse width 3ns at VSS.
EDS2504APTA/08APTA/16APTA-TI
Preliminary Data Sheet E0248E10 (Ver. 1.0)
5
DC Characteristics 1 (TA = 40 to +85
C, VDD, VDDQ = 3.3V 0.3V, VSS, VSSQ = 0V)
Parameter
max.
/CAS latency
Symbol
Grade
4
8
16
Unit
Test condition
Notes
Operating current
ICC1
-7A
130
130
135
mA
Burst length = 1
tRC = min.
1, 2, 3
ICC1
-75
110
110
115
mA
Burst length = 1
tRC = min.
Standby current in power
down
ICC2P
3
3
3
mA
CKE = VIL, tCK = min. 6
Standby current in power
down (input signal stable)
ICC2PS
2
2
2
mA
CKE = VIL, tCK =
7
Standby current in non
power down
ICC2N
20
20
20
mA
CKE, /CS = VIH,
tCK = min.
4
Standby current in non
power down (input signal
stable)
ICC2NS
9
9
9
mA
CKE = VIH, tCK =
,
/CS = VIH
8
Active standby current in
power down
ICC3P
4
4
4
mA
CKE = VIL, tCK = min. 1, 2, 6
Active standby current in
power down (input signal
stable)
ICC3PS
3
3
3
mA
CKE = VIL, tCK =
2, 7
Active standby current in
non power down
ICC3N
30
30
30
mA
CKE, /CS = VIH,
tCK = min.
1, 2, 4
Active standby current in
non power down (input
signal stable)
ICC3NS
15
15
15
mA
CKE = VIH, tCK =
,
/CS = VIH
2, 8
Burst operating current
ICC4
130
135
145
mA
tCK = min., BL = 4
1, 2, 5
Refresh current
ICC5
-7A
250
250
250
mA
tRC = min.
3
ICC5
-75
220
220
220
mA
tRC = min.
Self refresh current
ICC6
3
3
3
mA
VIH VDD 0.2V
VIL 0.2V
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
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