www.docs.chipfind.ru
Doc. No. E0643E30 (Ver. 3.0)
Date Published August 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
Overview
The EDX5116ABSE is a 512M bits XDR
TM
DRAM organized
as 32M words
16 bits. It is a general-purpose high-perfor-
mance memory device suitable for use in a broad range of
applications.
The use of Differential Rambus Signaling Level (DRSL) tech-
nology permits 4000/3200/2400 Mb/s transfer rates while
using conventional system and board design technologies.
XDR DRAM devices are capable of sustained data transfers of
8000/6400/4800 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device's
eight banks support up to four interleaved transactions.
It is packaged in 104-ball FBGA (
BGA
) compatible with
Rambus XDR DRAM pin configuration.
Features
Highest pin bandwidth available
4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
On-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
8000/6400/4800 MB/s sustained data rate
Eight banks: bank-interleaved transactions at full
bandwidth
Dynamic request scheduling
Early-read-after-write support for maximum efficiency
Zero overhead refresh
Dynamic width control
EDX5116ABSE supports
16,
8 and
4 mode
Low latency
2.0/2.5/3.33 ns request packets
Point-to-point data interconnect for fastest possible
flight time
Support for low-latency, fast-cycle cores
Low power
1.8V Vdd
Programmable small-swing I/O signaling (DRSL)
Low power PLL/DLL design
Powerdown self-refresh support
Per pin I/O powerdown for narrow-width operation
Pin Configuration
7
6
5
4
3
2
1
DQ7
DQN7
DQN5
DQ5
GND
VTERM
VDD
GND
DQ3
DQN3
DQN1
DQ1
GND
RQ11
RQ10
GND
VDD
RQ9
RQ8
VDD
GND
RQ7
RQ6
VDD
CFM
CFMN
RQ4
VREF
GND
RQ5
RQ2
GND
VDD
RQ3
RQ0
VDD
GND
RQ1
RST
GND
SD1
SCK
CMD
SD0
DG2
DQN2
DQN0
DQ0
GND
VTERM
VDD
GND
DQ6
DQN6
DQN4
DQ4
G
F
E
D
C
B
A
P
N
M
L
K
J
H
Column
Row
A8
A16
E
F
H
J
K
L
5
6
7
8
9
10
11
1
2
3
4
DQN9
DQ9
DQN5
DQ5
GND
VTERM
VDD
VDD
VDD
GND
VTERM
GND
RQ10
RQ11
GND
GND
VDD
RQ4
RQ3
VDD
VDD
SDI
GND
RQ0
GND
VTERM
DQN8
DQ8
DQN4
VDD
GND
VTERM
G
D
C
B
A
VDD
DQ4
Top view of package
CFM
CFMN
GND
VDD
VDD
GND
GND
RSRV
RSRV
VDD
GND
DQN2
DQ2
DQN14
VDD
GND
GND
DQ14
DQN3
DQ3
DQN15
VDD
GND
GND
DQ15
12
13
14
15
16
GND
DQN13
DQ13
DQN1
DQ1
VDD
CMD
SCK
GND
RQ9
RQ8
VDD
RQ1
RQ2
VDD
GND
VDD
GND
RST
SDO
GND
DQN12
DQ12
DQN0
DQ0
RQ7
RQ6
VDD
VREF
RQ5
VDD
DQN6
DQ6
DQN10
DQ10
VDD
DQN7
DQ7
DQN11
DQ11
GND
GND
GND
VDD
VDD
512M bits XDR
DRAM
EDX5116ABSE (32M words
16 bits)
PRELIMINARY DATA SHEET
Preliminary Data Sheet E0643E30 (Ver. 3.0)
2
EDX5116ABSE
Elpida Memory
Density
25: 256M (x 16bit)
Organization
16: x16bit
Power Supply, Interface
A: 1.8V, DRSL
Die Rev.
Package
SE: FBGA
(
BGA with back cover)
Product Family
X: XDR DRAM
Type
D: Monolithic Device
E D X 51 16 A B SE - 4C - E
Environment Code
E: Lead Free
Speed
4C: 4.0G (tRAC = 28, C Bin)
3C: 3.2G (tRAC = 35, C Bin)
3B: 3.2G (tRAC = 35, B Bin)
3A: 3.2G (tRAC = 27, A Bin)
2A: 2.4G (tRAC = 36, A Bin)
Ordering Information
Part Number
Part number
Organization
Bandwidth (1/tBIT)
Latency (tRAC)
Bin
Package
EDX5116ABSE-4C-E
EDX5116ABSE-3C-E
EDX5116ABSE-3B-E
EDX5116ABSE-3A-E
EDX5116ABSE-2A-E
4M
16
8 banks 4.0G
3.2G
3.2G
3.2G
2.4G
28
35
35
27
36
C
C
B
A
A
104-ball FBGA
(
BGA)
Preliminary Data Sheet E0643E30 (Ver. 3.0)
3
EDX5116ABSE
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device
write and read transactions. There are three sets of pins used
for normal memory access transactions: CFM/CFMN clock
pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.
The "N" appended to a signal name denotes the complemen-
tary signal of a differential pair.
A transaction is a collection of packets needed to complete a
memory access. A packet is a set of bit windows on the signals
of a bus. There are two buses that carry packets: the RQ bus
and DQ bus. Each packet on the RQ bus uses a set of 2 bit-
windows on each signal, while the DQ bus uses a set of 16 bit-
windows on each signal.
In the write transaction shown in Figure 1, a request packet (on
the RQ bus) at clock edge T
0
contains an activate (ACT) com-
mand. This causes row Ra of bank Ba in the memory compo-
nent to be loaded into the sense amp array for the bank. A
second request packet at clock edge T
1
contains a write (WR)
command. This causes the data packet D(a1) at edge T
4
to be
written to column Ca1 of the sense amp array for bank Ba. A
third request packet at clock edge T
3
contains another write
(WR) command. This causes the data packet D(a2) at edge T
6
to be also written to column Ca2. A final request packet at
clock edge T
14
contains a precharge (PRE) command.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: t
RCD -W
, t
CC
,
and t
WRP
. In addition, the spacing between the request packets
and data packets are constrained by the t
CWD
parameter. The
spacing of the CFM/CFMN clock edges is constrained by
t
CYCLE
.
Figure 1
XDR DRAM Device Write and Read Transactions
The read transaction shows a request packet at clock edge T
0
containing an ACT command. This causes row Ra of bank Ba
of the memory component to load into the sense amp array for
the bank. A second request packet at clock edge T
5
contains a
read (RD) command. This causes the data packet Q(a1) at edge
T
11
to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T
7
contains
another RD command. This causes the data packet Q(a2) at
edge T
13
to also be read from column Ca2. A final request
packet at clock edge T
10
contains a PRE command. The spac-
ings between the request packets are constrained by the follow-
ing timing parameters in the diagram: t
RCD -R
, t
CC
, and t
RDP
.
In addition, the spacing between the request and data packets
are constrained by the t
CAC
parameter.
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CWD
t
CYCLE
t
WRP
t
RCD-W
a1
WR
a2
WR
a3
PRE
a0
ACT
D(a2)
D(a1)
Write Transaction
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CAC
t
CYCLE
t
RDP
t
RCD-R
a1
RD
a2
RD
a3
PRE
a0
ACT
Q(a2)
Q(a1)
Read Transaction
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Preliminary Data Sheet E0643E30 (Ver. 3.0)
4
EDX5116ABSE
Table of Contents
Overview ....................................................................... 1
Features ........................................................................ 1
Pin Configuration ......................................................... 1
Ordering Information................................................... 2
Part Number .................................................................2
General Description ......................................................3
Table of Contents .........................................................4
Pin Description .............................................................7
Block Diagram ..............................................................8
Request Packets ......................................................... 10
Request Packet Formats ................................................. 10
Request Field Encoding .................................................. 12
Request Packet Interactions ........................................... 14
Request Interaction Cases .............................................. 15
Dynamic Request Scheduling ........................................ 20
Memory Operations .................................................... 22
Write Transactions .......................................................... 22
Read Transactions ........................................................... 24
Interleaved Transactions ................................................. 26
Read/Write Interaction .................................................. 28
Propagation Delay ........................................................... 28
Register Operations .................................................... 32
Serial Transactions ........................................................... 32
Serial Write Transaction ................................................. 32
Serial Read Transaction .................................................. 32
Register Summary ............................................................ 34
Maintenance Operations ............................................ 40
Refresh Transactions ....................................................... 40
Interleaved Refresh Transactions .................................. 40
Calibration Transactions ................................................. 42
Power State Management ............................................... 44
Initialization ...................................................................... 46
XDR DRAM Initialization Overview .......................... 47
XDR DRAM Pattern Load with WDSL Reg ............. 48
Special Feature Description ....................................... 50
Dynamic Width Control ................................................. 50
Write Masking .................................................................. 52
Multiple Bank Sets and the ERAW Feature ................ 54
Simultaneous Activation ................................................. 56
Simultaneous Precharge ................................................. 57
Operating Conditions ................................................ 58
Electrical Conditions ....................................................... 58
Timing Conditions .......................................................... 59
Operating Characteristics .......................................... 60
Electrical Characteristics ................................................ 60
Supply Current Profile .................................................... 61
Timing Characteristics .................................................... 62
Timing Parameters .......................................................... 62
Receive/Transmit Timing ......................................... 64
Clocking ............................................................................ 64
RSL RQ Receive Timing ................................................ 65
DRSL DQ Receive Timing ............................................ 66
DRSL DQ Transmit Timing ......................................... 68
Serial Interface Receive Timing ..................................... 70
Serial Interface Transmit Timing .................................. 71
Package Description .................................................. 72
Package Parasitic Summary ............................................ 72
Package Drawing ............................................................ 74
Package Pin Numbering ................................................. 75
Recommended Soldering Conditions ....................... 76
Preliminary Data Sheet E0643E30 (Ver. 3.0)
5
EDX5116ABSE
List of Tables
Pin Description .............................................................7
Request Field Description .......................................... 10
OP Field Encoding Summary .................................... 12
ROP Field Encoding Summary .................................. 12
POP Field Encoding Summary .................................. 13
XOP Field Encoding Summary .................................. 13
Packet Interaction Summary ...................................... 14
SCMD Field Encoding Summary ............................... 32
Initialization Timing Parameters ............................... 47
XDR DRAM WDSL-to-Core/DQ/SC Map (First Genera-
tion x16/x8/x4 XDR DRAM , BL=16) ...................... 48
Core Data Word-to-WDSL Format ............................ 49
Electrical Conditions .................................................. 58
Timing Conditions ..................................................... 59
Electrical Characteristics ........................................... 60
Supply Current Profile .................................................61
Timing Characteristics ............................................... 62
Timing Parameters .................................................... 62
Package Parasitic Summary ....................................... 72
Preliminary Data Sheet E0643E30 (Ver. 3.0)
6
EDX5116ABSE
List of Figures
XDR DRAM Device Write and Read Transactions .....3
512Mb (8x4Mx16) XDR DRAM Block Diagram ..........9
Request Packet Formats ..............................................11
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions . 16
ACT-, RD-, WR-, PRE-to-RD Packet Interactions ... 17
ACT-, RD-, WR-, PRE-to-WR Packet Interactions ... 18
ACT-, RD, WR-, PRE-to-PRE Packet Interactions .. 19
Request Scheduling Examples ................................... 21
Write Transactions ..................................................... 23
Read Transactions ...................................................... 25
Interleaved Transactions ............................................ 27
Write/Read Interaction .............................................. 29
Propagation Delay ...................................................... 31
Serial Write Transaction ............................................. 33
Serial Read Transaction -- Selected DRAM .............. 33
Serial Read Transaction -- Non-selected DRAM ..... 33
Serial Identification (SID) Register ............................ 34
Configuration (CFG) Register .................................... 35
Power Management (PM) Register ............................ 35
Write Data Serial Load (WDSL) Control Register ..... 35
RQ Scan High (RQH) Register ................................. 36
RQ Scan Low (RQL) Register .................................... 36
Refresh Bank (REFB) Control Register ..................... 36
Refresh High (REFH) Row Register ......................... 37
Refresh Middle (REFM) Row Register ..................... 37
Refresh Low (REFL) Row Register ........................... 37
IO Configuration (IOCFG) Register .......................... 37
Current Calibration 0 (CC0) Register ........................ 38
Current Calibration 1 (CC1) Register ......................... 38
Read Only Memory 0 (ROM0) Register .................... 38
Read Only Memory 1 (ROM1) Register .................... 38
TEST Register ............................................................ 39
Delay (DLY) Control Register ................................... 39
Refresh Transactions ..................................................41
Calibration Transactions ............................................ 43
Power State Management .......................................... 45
Serial Interface System Topology .............................. 46
Initialization Timing for XDR DRAM[k] Device .... 46
Multiplexers for Dynamic Width Control .................. 50
D-to-S and S-to-Q Mapping for Dynamic Width Control
51
Byte Mask Logic ........................................................ 52
Write-Masked (WRM) Transaction Example ........... 53
Write/Read Interaction -- No ERAW Feature ......... 54
Write/Read Interaction -- ERAW Feature ............... 54
XDR DRAM Block Diagram with Bank Sets .......... 55
Simultaneous Activation -- tRR-D Cases ................. 56
Simultaneous Precharge -- tPP-D Cases .................. 57
Clocking Waveforms .................................................. 64
RSL RQ Receive Waveforms ..................................... 65
DRSL DQ Receive Waveforms .................................. 67
DRSL DQ Transmit Waveforms ................................ 69
Serial Interface Receive Waveforms ........................... 70
Serial Interface Transmit Waveforms .........................71
Equivalent Circuits for Package Parasitic ................. 73
CSP x16 Package - Pin Numbering (top view) .......... 75
Preliminary Data Sheet E0643E30 (Ver. 3.0)
7
EDX5116ABSE
Pin Description
Table 1 summarizes the pin functionality of the XDR DRAM
device. The first group of pins provide the necessary supply
voltages. These include VDD and GND for the core and inter-
face logic, VREF for receiving input signals, and VTERM for
driving output signals.
The next group of pins are used for high bandwidth memory
accesses. These include DQ15..0 and DQN15..0 for carrying
read and write data signals, RQ11..0 for carrying request sig-
nals, and CFM and CFMN for carrying timing information
used by the DQ, DQN, and RQ signals.
The final set of pins comprise the serial interface that is used
for control register accesses. These include RST for initializing
the state of the device, CMD for carrying command signals,
SDI, and SDO for carrying register read data, and SCK for car-
rying the timing information used by the RST, SDI, SDO, and
CMD signals.
Table 1
Pin Description
Signal
I/O
Type
No. of pins
Description
VDD
-
-
22
Supply voltage for the core and interface logic of the device.
GND
-
-
24
Ground reference for the core and interface logic of the device.
VREF
-
-
1
Logic threshold reference voltage for RSL signals.
VTERM
-
-
4
Termination voltage for DRSL signals.
DQ15..0
I/O
DRSL
a
16
Positive data signals that carry write or read data to and from the device.
DQN15..0
I/O
DRSL
a
16
Negative data signals that carry write or read data to and from the device.
RQ11..0
I
RSL
a
12
Request signals that carry control and address information to the device.
CFM
I
DIFFCLK
a
1
Clock from master -- Positive interface clock used for receiving RSL signals, and
receiving and transmitting DRSL signals from the Channel.
CFMN
I
DIFFCLK
a
1
Clock from master -- Negative interface clock used for receiving RSL signals,
and receiving and transmitting DRSL signals from the Channel.
RST
I
RSL
a
1
Reset input -- This pin is used to initialize the device.
CMD
I
RSL
a
1
Command input -- This pin carries command, address, and control register write
data into the device.
SCK
I
RSL
a
1
Serial clock input -- Clock source used for reading from and writing to the con-
trol registers.
SDI
I
RSL
a
1
Serial data input -- This pin carries control register read data through the device.
This pin is also used to initialize the device.
SDO
O
CMOS
a
1
Serial data output -- This pin carries control register read data from the device.
This pin is also used to initialize the device.
RSRV
-
-
2
Reserved pins -- Follow Rambus XDR system design guidelines for connecting
RSRV pins
Total pin count per package
104
a. All DQ and CFM signals are high-true; low voltage is logic 0 and high voltage is logic 1.
All DQN, CFMN, RQ, RSL, and CMOS signals are low-true; high voltage is logic 0 and low voltage is logic 1.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
8
EDX5116ABSE
Block Diagram
A block diagram of the XDR DRAM device is shown in
Figure 2. It shows all interface pins and major internal blocks.
The CFM and CFMN clock signals are received and used by
the clock generation logic to produce three virtual clock sig-
nals: 1/t
CYCLE
, 2/t
CYCLE
, and 16/t
CC
. The frequency of these
signals are 1x, 2x, and 8x that of the CFM and CFMN signals.
These virtual signals show the effective data rate of the logic
blocks to which they connect; they are not necessarily present
in the actual memory component.
The RQ11..0 pins receive the request packet. Two 12-bit words
are received in one t
CYCLE
interval. This is indicated by the 2/
t
CYCLE
clocking signal connected to the 1:2 Demux Block that
assembles the 24-bit request packet. These 24 bits are loaded
into a register (clocked by the 1/t
CYCLE
clocking signal) and
decoded by the Decode Block. The VREF pin supplies a refer-
ence voltage used by the RQ receivers.
Three sets of control signals are produced by the Decode
Block. These include the bank (BA) and row (R) addresses for
an activate (ACT) command, the bank (BR) and row (REFr)
addresses for a refresh activate (REFA) command, the bank
(BP) address for a precharge (PRE) command, the bank (BR)
address for a refresh precharge (REFP) command, and the
bank (BC) and column (C and SC) addresses for a read (RD) or
write (WR or WRM) command. In addition, a mask (M) is used
for a masked write (WRM) command.
These commands can all be optionally delayed in increments of
t
CYCLE
under control of delay fields in the request. The control
signals of the commands are loaded into registers and pre-
sented to the memory core. These registers are clocked at max-
imum rates determined by core timing parameters, in this case
1/t
RR
, 1/t
PP
, and 1/t
CC
(1/4, 1/4, and 1/2 the frequency of
CFM in the -3200 component). These registers may be loaded
at any t
CYCLE
rising edge. Once loaded, they should not be
changed until a t
RR
, t
PP
, or t
CC
time later because timing paths
of the memory core need time to settle.
A bank address is decoded for an ACT command. The indi-
cated row of the selected bank is sensed and placed into the
associated sense amp array for the bank. Sensing a row is also
referred to as "opening a page" for the bank.
Another bank address is decoded for a PRE command. The
indicated bank and associated sense amp array are precharged
to a state in which a subsequent ACT command can be
applied. Precharging a bank is also called "closing the page" for
the bank.
After a bank is given an ACT command and before it is given a
PRE command, it may receive read (RD) and write (WR) col-
umn commands. These commands permit the data in the
bank's associated sense amp array to be accessed.
For a WR command, the bank address is decoded. The indi-
cated column of the associated sense amp array of the selected
bank is written with the data received from the DQ15..0 pins.
The bank address is decoded for a RD command. The indi-
cated column of the selected bank's associated sense amp array
is read. The data is transmitted onto the DQ15..0 pins.
The DQ15..0 pins receive the write data packet (D) for a write
transaction. 16 sixteen-bit words are received in one t
CC
inter-
val. This is indicated by the 16/t
CC
clocking signal connected
to the 1:16 Demux Block that assembles the 16x16-bit write
data packet. The write data is then driven to the selected Sense
Amp Array Bank.
16 sixteen-bit words are accessed in the selected Sense Amp
Array Bank for a read transaction. The DQ15..0 pins transmit
this read data packet (Q) in one t
CC
interval. This is indicated
by the 16/t
CC
clocking signal connected to the 16:1 Mux
Block. The VTERM pin supplies a termination voltage for the
DQ pins.
The RST, SCK, and CMD pins connect to the Control Register
block. These pins supply the data, address, and control needed
to write the control registers. The read data for the these regis-
ters is accessed through the SDO/SDI pins. These pins are
also used to initialize the device.
The control registers are used to transition between power
modes, and are also used for calibrating the high speed trans-
mit and receive circuits of the device. The control registers also
supply bank (REFB) and row (REFr) addresses for refresh
operations.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
9
EDX5116ABSE
Figure 2
512Mb (8x4Mx16) XDR DRAM Block Diagram
1
1:2 Demux
Decode
12
RQ11..0
1:16 Demux
16:1 Mux
16/t
CC
2/t
CYCLE
reg
12
12
CFM CFMN
1/t
CYCLE
1/t
CYCLE
12
12
4
RST,SCK,CMD,SDI
Control Registers
1
SDO
2/t
CYCLE
16/ t
CC
Bank 0
ACT delay
re
g
1/t
RR
ACT logic
...
...
{0..1}*t
CYCLE
de
code
Bank 0
1
ACT
ACT
ROW
1
1/t
PP
...
deco
de
1
PRE
PRE
PRE delay
PRE logic
{0..3}*t
CYCLE
ROW
...
Sense Amp 0
...
1
re
g
1/t
CC
...
deco
de
1
R/W
R/W
COL
COL
RD,WR
COL logic
...
...
re
g
7
BA,BR,REFB
R,REFr
BP,BR,REFB
BC
C
SC
M
...
Bank Array
Sense Amp Array
8
...
...
...
...
Dynamic Width Demux (WR)
re
g
termination
VTERM
2
1
VREF
REFB,REFr
WIDTH
{0..1}*t
CYCLE
delay
DQ15..0
DQN15..0
16
16
16
16
16/t
CC
16x16*2
6
16x16
16x16
16x16
16x16
4
3
3
3
3
3
6+4
12
(2
3
- 1)
Bank
(2
3
- 1)
Sense Amp
2
3
2
3
3
6
16x16*2
6
12
2
3
16x16*2
6
*2
12
16
D[15:0][15:0]
S[15:0][15:0]
16
16x16
16x16
16x16*2
6
WIDTH
Q[15:0][15:0]
Dynamic Width Mux (RD)
Byte Mask (WR)
Power Mode Logic
Calibration Logic
Refresh Logic
Initialization Logic
Preliminary Data Sheet E0643E30 (Ver. 3.0)
10
EDX5116ABSE
Request Packets
A request packet carries address and control information to
the memory device. This section contains tables and diagrams
for packet formats, field encodings and packet interactions.
Request Packet Formats
There are five types of request packets:
1. ROWA
--
specifies an ACT command
2. COL
--
specifies RD and WR commands
3. COLM
--
specifies a WRM command
4. ROWP
--
specifies PRE and REF commands
5. COLX
--
specifies the remaining commands
Table 2 describes fields within different request packet types.
Various request packet type formats are illustrated in Figure 3.
Each packet type consists of 24 bits sampled on the RQ11..0
pins on two successive edges of the CFM/CFMN clock. The
request packet formats are distinguished by the OP3..0 field.
This field also specifies the operation code of the desired com-
mand.
In the ROWA packet, a bank address (BA), row address (R),
and command delay (DELA) are specified for the activate
(ACT) command.
In the COL packet, a bank address (BC), column address (C),
sub-column address (SC), command delay (DELC), and sub-
opcode (WRX) are specified for the read (RD) and write (WR)
commands.
In the COLM packet, a bank address (BC), column address
(C), sub-column address (SC), and mask field (M) are specified
for the masked write (WRM) command.
In the ROWP packet, two independent commands may be
specified. A bank address (BP) and sub-opcode (POP) are
specified for the precharge (PRE) commands. An address field
(RA) and sub-opcode (ROP) are specified for the refresh
(REF) commands.
In the COLX packet, a sub-operation code field (XOP) is spec-
ified for the remaining commands.
Table 2
Request Field Description
Field
Packet Types
Description
OP3..0
ROWA/ROWP/COL/COLM/COLX
4-bit operation code that specifies packet format.
(Encoded commands are in Table 3 on page 12).
DELA
ROWA
Delay the associated row activate command by 0 or 1 t
CYCLE
.
BA2..0
ROWA
3-bit bank address for row activate command.
R11..0
ROWA
12-bit row address for row activate command.
WRX
COL
Specifies RD (=0) or WR (=1) command.
DELC
COL
Delay the column read or write command by 0 or 1 t
CYCLE
.
BC2..0
COL/COLM
3-bit bank address for column read or write command.
C9..4
COL/COLM
6-bit column address for column read or write command.
SC3..0
COL/COLM
4-bit sub-column address for dynamic width (see "Dynamic Width Control" on page 50).
M7..0
COLM
8-bit mask for masked-write command WRM.
POP2..0
ROWP
3-bit operation code that specifies row precharge command with a delay of 0 to 3 t
CYCLE
.
(Encoded commands are in Table 5 on page 13).
BP2..0
ROWP
3-bit bank address for row precharge command.
ROP2..0
ROWP
3-bit operation code that specifies refresh commands.
(Encoded commands are in Table 4 on page 12).
RA7..0
ROWP
8-bit refresh address field (specifies BR bank address, delay value, and REFr load value
XOP3..0
COLX
4-bit extended operation code that specifies calibration and powerdown commands.
(Encoded commands are in Table 6 on page 13).
Preliminary Data Sheet E0643E30 (Ver. 3.0)
11
EDX5116ABSE
Figure 3
Request Packet Formats
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
t
CYCLE
a3
PRE
a1
RD
a2
WRM
a0
ACT
RQ11
ROWA Packet
RQ10
RQ9
RQ8
RQ7
RQ6
RQ5
RQ4
RQ3
RQ2
RQ1
RQ0
CFM
CFMN
OP
DEL
OP
R
R
R
R
R
R
R
R
R
rsrv
rsrv
COL Packet
OP
DEL
OP
rsrv
OP
rsrv
WR
C
C
BC
BC
COLM Packet
OP
M
M
M
M
M
M
C
C
ROWP Packet
OP
POP
OP
ROP
OP
ROP
POP
RA
POP
RA
RA
RA
RA
RA
BP
RA
BP
RA
COLX Packet
OP
rsrv
OP
rsrv
OP
rsrv
OP
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
rsrv
XOP
rsrv
XOP
rsrv
XOP
rsrv
XOP
rsrv
-
PDN
t
CYCLE
t
CYCLE
t
CYCLE
t
CYCLE
t
CYCLE
2
2
C
A
3
2
3
2
0
X
7
0
1
2
3
4
5
6
7
8
3
3
1
0
7
6
4
7
6
3
2
0
1
0
7
6
6
3
2
1
0
0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
3
2
1
0
BA
1
BA
0
rsrv
OP
1
C
5
C
4
C
5
M
5
M
2
ROP
1
OP
1
BC
1
BC
0
C
4
0
1
0
1
2
3
4
5
1
0
9
R
10
R
11
R
rsrv
rsrv
2
BA
rsrv
rsrv
8
C
rsrv
2
BC
9
C
rsrv
1
SC
0
SC
3
SC
2
SC
8
C
rsrv
2
BC
9
C
rsrv
1
SC
0
SC
3
SC
2
SC
rsrv
2
BP
rsrv
rsrv
Preliminary Data Sheet E0643E30 (Ver. 3.0)
12
EDX5116ABSE
Request Field Encoding
Operation-code fields are encoded within different packet
types to specify commands. Table 3 through Table 6 provides
packet type and encoding summaries.
Table 3 shows the OP field encoding for the five packet types.
The COLM and ROWA packets each specify a single com-
mand: ACT and WRM. The COL, COLX, and ROWP packets
each use additional fields to specify multiple commands: WRX,
XOP, and POP/ROP, respectively. The COLM packet specifies
the masked write command WRM. This is like the WR
unmasked write command, except that a mask field M7..0 indi-
cates whether each byte of the write data packet is written or
not written. The ROWA packet specifies the row activate com-
mand ACT. The COL packet uses the WRX field to specify the
column read and column write (unmasked) commands.
Encoding of the ROP field in the ROWP packet is shown in
Table 4. The first encoding specifies a NOPR (no operation)
command. The REFP command uses the RA field to select a
bank to be precharged. The REFA and REFI commands use
the RA field and REFH/M/L registers to select a bank and
row to be activated for refresh. The REFI command also
increments the REFH/M/L register. The REFP, REFA, and
REFI commands may also be delayed by up to 3*t
CYCLE
using
the RA[7:6] field. The LRR0, LRR1, and LRR2 commands
load the REFH/M/L registers from the RA[7:0] field.
The REFH/M/L registers are also referred to as the REFr reg-
isters. Note that only the bits that are needed for specifying the
refresh row (12 bits in all) are implemented in the REFr regis-
ters
--
the rest are reserved. Note also that the RA2..0 field that
Table 3
OP Field Encoding Summary
OP [3:0]
Packet
Command
Description
0000
-
NOP
No operation.
0001
COL
RD
Column read (WRX=0). Column C9..4 of sense amp in bank BC2..0 is read to DQ bus after DELC*t
CYCLE
.
WR
Column write (WRX=1). Write DQ bus to column C9..4 of sense amp in bank BC2..0 after DELC*t
CYCLE
.
0010
COLX
CALy
XOP3..0 specifies a calibrate or powerdown command -- see Table 6 on page 13.
0011
ROWP
PREx
POP2..0 specifies a row precharge command -- see Table 5 on page 13.
REFy,LRRr
ROP2..0 specifies a row refresh command or load REFr register command -- see Table 4 on page 12.
01xx
ROWA
ACT
Row activate command. Row R11..0 of bank BA2..0 is placed into the sense amp of the bank after DELA*t
CYCLE
.
1xxx
COLM
WRM
Column write command (masked) -- mask M7..0 specifies which bytes are written.
Table 4
ROP Field Encoding Summary
ROP[2:0]
Command
Description
000
NOPR
No operation
001
REFP
Refresh precharge command. Bank RA2..0 is precharged.
This command is delayed by {0,1,2,3}*t
CYCLE
(the value is given by the expression (2*RA[7]+RA[6]).
010
REFA
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp.
This command is delayed by {0,1,2,3}*t
CYCLE
(the value is given by the expression (2*RA[7]+RA[6]).
011
REFI
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp.
This command is delayed by {0,1,2,3}*t
CYCLE
(the value is given by the expression (2*RA[7]+RA[6]).
R[11:0] field of REFH/M/L register is incremented after the activate command has completed.
100
LRR0
Load Refresh Low Row register (REFL). RA[7:0] is stored in R[7:0] field.
101
LRR1
Load Refresh Middle Row register (REFM). RA[3:0] is stored in R[11:8] field.
110
LRR2
Load Refresh High Row register -- not used with this device.
111
-
Reserved
Preliminary Data Sheet E0643E30 (Ver. 3.0)
13
EDX5116ABSE
specifies the refresh bank address is also referred to as BR2..0.
See "Refresh Transactions" on page 40.
Table 5 shows the POP field encoding in the ROWP packet.
The first encoding specifies a NOPP (no operation) command.
There are four variations of PRE (precharge) command. Each
uses the BP field to specify the bank to be precharged. Each
also specifies a different delay of up to 3*t
CYCLE
using the
POP[1:0] field. A precharge command may be specified in
addition to a refresh command using the ROP field.
Table 6 shows the XOP field encoding in the COLX packet.
This field encodes the remaining commands.
The CALC and CALE commands perform calibration opera-
tions to ensure signal integrity on the Channel. See "Calibra-
tion Transactions" on page 42.
The PDN command causes the device to enter a power-down
state. See "Power State Management" on page 44.
Table 5
POP Field Encoding Summary
POP
[2:0]
Command
Description
000
NOPP
No operation.
001
-
Reserved.
010
-
Reserved.
011
-
Reserved.
100
PRE0
Row precharge command -- Bank BP2..0 is precharged. This command is delayed by 0*t
CYCLE
.
101
PRE1
Row precharge command -- Bank BP2..0 is precharged. This command is delayed by 1*t
CYCLE
.
110
PRE2
Row precharge command -- Bank BP2..0 is precharged. This command is delayed by 2*t
CYCLE
.
111
PRE3
Row precharge command -- Bank BP2..0 is precharged. This command is delayed by 3*t
CYCLE
.
Table 6
XOP Field Encoding Summary
XOP
[3:0]
Command
Command and Description
XOP
[3:0]
Command
Command and Description
0000
-
Reserved.
1000
CALC
Current calibration command.
0001
-
Reserved.
1001
CALZ
Impedance calibration command.
0010
-
Reserved.
1010
CALE
End calibration command (CALC).
0011
-
Reserved.
1011
-
Reserved.
0100
-
Reserved.
1100
PDN
Enter powerdown power state.
0101
-
Reserved.
1101
-
Reserved.
0110
-
Reserved.
1110
-
Reserved.
0111
-
Reserved.
1111
-
Reserved.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
14
EDX5116ABSE
Request Packet Interactions
A summary of request packet interactions is shown in Table 7.
Each case is limited to request packets with commands that
perform memory operations (including refresh commands).
This includes all commands in ROWA, ROWP, COL, and
COLM packets. The commands in COLX packets are
described in later sections. See "Maintenance Operations" on
page 40.
Request packet/command "a" is followed by request packet/
command "b". The minimum possible spacing between these
two packet/commands is 0*t
CYCLE
. However, a larger time
interval may be needed because of a resource interaction
between the two packet/commands. If the minimum possible
spacing is 0*t
CYCLE
, then an entry of "No limit" is shown in
the table.
Note that the spacing values shown in the table are relative to
the effective beginning of a packet/command. The use of the
delay field with a command will delay the position of the effec-
tive packet/command from the position of the actual packet/
command. See "Dynamic Request Scheduling" on page 20.
Any of the packet/command encodings under one of the four
operation types is equivalent in terms of the resource con-
straints. Therefore, both the horizontal columns (packet "a")
and vertical rows (packet "b") of the interaction table are
divided into four major groups.
The four possible operation types for request packets a and b
include:
;
[A] Activate Row
ROWA/ACT
ROWP/REFA
ROWP/REFI
;
[R] Read Column
COL/RD
;
[W] Write Column
COL/WR
COLM/WRM
;
[P] Precharge Row
ROWP/PRE
ROWP/REFP
Table 7
Packet Interaction Summary
Second packet/command to bank Bb
Activate Row [A]
Read Column [R]
Write Column [W]
Precharge Row [P]
First packet/command to bank Ba
ROWA - ACT Bb
ROWP - REFA Bb
ROWP - REFI Bb
COL - RD Bb
COL - WR Bb
COLM - WRM Bb
ROWP - PRE Bb
ROWP - REFP Bb
Activate Row [A]
ROWA - ACT Ba
ROWP - REFA Ba
ROWP - REFI Ba
Ba,Bb different
Case AAd: t
RR
Case ARd: No limit
Case AWd: No limit
Case APd: No limit
Ba,Bb same
Case AAs: t
RC
Case ARs: t
RCD-R
Case AWs: t
RCD-W
Case APs: t
RAS
Read Column [R]
COL - RD Ba
Ba,Bb different
Case RAd: No limit
Case RRd: t
CC
Case RWd:
a
t
RW
Case RPd: No limit
Ba,Bb same
Case RAs:
b
t
RDP
+t
RP
Case RRs: t
CC
Case RWs:
a
t
RW
Case RPs: t
RDP
Write Column [W]
COL - WR Ba
COLM - WRM Ba
Ba,Bb different
Case WAd: No limit
Case WRd
c
t
WR
Case WWd: t
CC
Case WPd: No limit
Ba,Bb same
Case WAs
b
: t
WRP
+t
RP
Case
WRs:
c
t
WR
Case WWs: t
CC
Case WPs: t
WRP
Precharge Row [P]
ROWP - PRE Ba
ROWP - REFP Ba
Ba,Bb different
Case PAd: No limit
Case PRd: No limit
Case PWd: No limit
Case PPd: t
PP
Ba,Bb same
Case PAs: t
RP
Case PRs:
d
t
RP
+t
RCD-R
Case PWs:
d
t
RP
+t
RCD-W
Case PPs: t
RC
See Examples:
Figure 4
Figure 5
Figure 6
Figure 7
a. t
RW
is equal to t
CC
+ t
RW-BUB,XDRDRAM
+ t
CAC
- t
CWD
and is defined in Table 17. This also depends upon propagation delay - See "Propagation Delay"
on page 28.
b. A PRE command is needed between the RD and ACT/REFA commands or the WR/WRM and ACT/REFA commands.
c. t
WR
is defined in Table 17.
d. An ACT command is needed between the PRE/REFP and RD commands or the PRE/REFP and WR/WRM commands.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
15
EDX5116ABSE
The first request is shown along the vertical axis on the left of
the table. The second request is shown along the horizontal
axis at the top of the table. Each request includes a bank speci-
fication "Ba" and "Bb". The first and second banks may be the
same, or they may be different. These two subcases for each
interaction are shown along the vertical axis on the left.
There are 32 possible interaction cases altogether. The table
gives each case a label of the form "xyz", where "x" and "y"
are one of the four operation types ("A" for Activate, "R" for
Read, "W" for Write, or "P" for Precharge) for the first and
second request, respectively, and "z" indicates the same bank
("s") or different bank ("d").
Along the horizontal axis at the bottom of the table are cross
references to four figures (Figure 4 through Figure 7). Each
figure illustrates the eight cases in the corresponding vertical
column. Thus, Figure 4 shows the eight cases when the second
request is an activate operation ("A"). In the following discus-
sion of the cases, only those in which the interaction interval is
greater than t
CYCLE
will be described.
Request Interaction Cases
In Figure 4, the interaction interval for the AAd case is t
RR
.
This parameter is the row-to-row time and is the minimum
interval between activate commands to different banks of a
device.
The interaction interval for the AAs case is t
RC
. This is the
row cycle time parameter and is the minimum interval between
activate commands to same banks of a device. A precharge
operation must be inserted between the two activate opera-
tions.
The interaction interval for the RAs case is t
RDP
+ t
RP
. A pre-
charge operation must be inserted between the read and acti-
vate operation. The minimum interval between a read and a
precharge operation to a bank is t
RDP
. The minimum interval
between a precharge and an activate operation to a bank is t
RP
.
The interaction interval for the WAs case is t
WDP
+ t
RP
. A
precharge operation must be inserted between the read and the
activate operation.The minimum interval between a write and a
precharge operation to a bank is t
WDP
. The minimum interval
between a precharge and an activate operation to a bank is t
RP
.
The interaction interval for the PAs case is t
RP
. The minimum
interval between a precharge and an activate operation to a
bank is t
RP
.
In Figure 5, the interaction interval for the ARs case is t
RCD-R
.
This is the row-to-column-read time parameter and represents
the minimum interval between an activate operation and a read
operation to a bank.
The interaction interval for the RRd and RRs cases is t
CC
. This
is the column-to-column time parameter and represents the
minimum interval between two read operations.
The interaction interval for the WRd and WRs cases is t
WR
.
This is the write-to-read time parameter and represents the
minimum interval between a write and a read operation to any
banks. See "Read/Write Interaction" on page 28.
The interaction interval for the PRs case is t
RP
+ t
RCD-R
. An
activate operation must be inserted between the precharge and
the read operation. The minimum interval between a precharge
and an activate operation to a bank is t
RP
. The minimum inter-
val between an activate and read operation to a bank is t
RCD-R
.
In Figure 6, the interaction interval for the AWs case is t
RCD-W
.
This is the row-to-column-write timing parameter and repre-
sents the minimum interval between an activate operation and
a write operation to a bank.
The interaction interval for the RWd and RWs cases is t
RW
.
This is the read-to-write time parameter and represents the
minimum interval between a read and a write operation to any
banks. See "Read/Write Interaction" on page 28.
The interaction interval for the WWd and WWs cases is t
CC
.
This is the column-to-column time parameter and represents
the minimum interval between two write operations.
The interaction interval for the PWs case is t
RP
+ t
RCD-W
. An
activate operation must be inserted between the precharge and
the write operation. The minimum interval between a pre-
charge and an activate operation to a bank is t
RP
. The mini-
mum interval between an activate and a write operation to a
bank is t
RCD-W
.
In Figure 7, the interaction interval for the APs case is t
RAS
.
This parameter is the minimum activate-to-precharge time to a
bank.
The interaction intervals for the RPs and WPs cases are t
RDP
and t
WDP
, respectively. These are the read- or write-to-pre-
charge time parameters to a bank.
The interaction interval for the PPd case is t
PP
. This parameter
is the precharge-to-precharge time and the minimum interval
between precharge commands to different banks of a device.
The interaction interval for the PPs case is t
RC
. This is the row
cycle time parameter and the minimum interval between pre-
charge commands to same banks of a device. An activate oper-
ation must be inserted between the two activate operations.
This activate operation must be placed a time t
RP
after the first,
and a time t
RAS
before the second precharge.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
16
EDX5116ABSE
Figure 4
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
a: ROWA Packet with ACT,Ba,Ra
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
AAd Case (activate-activate-different bank)
AAs Case (activate-activate-same bank)
RAd Case (read-activate-different bank)
RAs Case (read-activate-same bank)
WAd Case (write-activate-different bank)
WAs Case (write-activate-same bank)
PAd Case (precharge-activate-different bank)
PAs Case (precharge-activate-same bank)
b: ROWA Packet with ACT,Bb,Rb
Ba Bb
a: ROWA Packet with ACT,Ba,Ra
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba Bb
a: COL Packet with RD,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba Bb
a: COL Packet with WR,Ba,Ca
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
a: ROWP Packet with PRE,Ba
b: ROWA Packet with ACT,Bb,Rb
Ba Bb
a: ROWP Packet with PRE,Ba
b: ROWA Packet with ACT,Bb,Rb
Ba = Bb
No limit
a
PRE
b
ACT
No limit
a
WR
b
ACT
No limit
a
RD
b
ACT
t
RR
b
ACT
t
RC
a
ACT
t
RAS
t
RP
a
ACT
b
ACT
a
PRE
t
RDP
+t
RP
t
RDP
t
RP
a
RD
b
ACT
a
PRE
t
WRP
+t
RP
t
WRP
t
RP
a
WR
b
ACT
a
PRE
t
RP
a
PRE
b
ACT
=/
=/
=/
=/
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Preliminary Data Sheet E0643E30 (Ver. 3.0)
17
EDX5116ABSE
Figure 5
ACT-, RD-, WR-, PRE-to-RD Packet Interactions
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
a: ROWA Packet with ACT,Ba,Ra
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
ARd Case (activate-read different bank)
ARs Case (activate-read same bank)
RRd Case (read-read different bank)
RRs Case (read-read same bank)
WRd Case (write-read different bank)
WRs Case (write-read same bank)
PRd Case (precharge-read different bank)
PRs Case (precharge-read same bank)
b: COL Packet with RD,Bb,Cb
Ba Bb
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with RD,Bb,Cb
Ba = Bb
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba Bb
a: COL Packet with RD,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba = Bb
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba Bb
a: COL Packet with WR,Ba,Ca
b: COL Packet with RD,Bb,Cb
Ba = Bb
a: ROWP Packet with PRE,Ba
b: COL Packet with RD,Bb,Cb
Ba Bb
a: ROWP Packet with PRE,Ba
b: COL Packet with RD,Bb,Cb
Ba = Bb
No limit
a
PRE
b
RD
No limit
a
ACT
b
RD
t
RP
+t
RCD-R
t
RP
t
RCD-R
a
PRE
b
RD
B
ACT
t
RCD-R
a
ACT
b
RD
t
CC
b
RD
a
RD
t
WR
b
RD
a
WR
t
WR
b
RD
a
WR
t
CC
b
RD
a
RD
=/
=/
=/
=/
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Preliminary Data Sheet E0643E30 (Ver. 3.0)
18
EDX5116ABSE
Figure 6
ACT-, RD-, WR-, PRE-to-WR Packet Interactions
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
a: ROWA Packet with ACT,Ba,Ra
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
AWd Case (activate-write different bank)
AWs Case (activate-write same bank)
RWd Case (read-write-different bank)
RWs Case (read-write-same bank)
WWd Case (write-write different bank)
WWs Case (write-write same bank)
PWd Case (precharge-write different bank)
PWs Case (precharge-write same bank)
b: COL Packet with WR,Bb,Cb
Ba Bb
a: ROWA Packet with ACT,Ba,Ra
b: COL Packet with WR,Bb,Cb
Ba = Bb
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba Bb
a: COL Packet with RD,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba = Bb
a: COL Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba Bb
a: COP Packet with WR,Ba,Ca
b: COL Packet with WR,Bb,Cb
Ba = Bb
a: ROWP Packet with PRR,Ba
b: COL Packet with WR,Bb,Cb
Ba Bb
a: ROWP Packet with PRE,Ba
b: COP Packet with WR,Bb,Cb
Ba = Bb
No limit
a
PRE
b
WR
No limit
a
ACT
b
WR
t
RP
+t
RCD-W
t
RP
a
PRE
b
WR
B
ACT
t
RCD-W
a
ACT
b
WR
t
RW
t
CC
b
WR
a
WR
t
CC
b
WR
a
WR
t
CAC
D(b)
Q(a)
t
CWD
t
CYCLE
a
RD
b
WR
t
RW
t
CAC
D(b)
Q(a)
t
CWD
t
CYCLE
a
RD
b
WR
=/
=/
=/
=/
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..D0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
CC
t
CC
t
RCD-W
Preliminary Data Sheet E0643E30 (Ver. 3.0)
19
EDX5116ABSE
Figure 7
ACT-, RD, WR-, PRE-to-PRE Packet Interactions
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
a: ROWA Packet with ACT,Ba,Ra
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
T
0
T
1
T
2
T
3
CFM
RQ11..0
DQ15..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
DQN15..0
APd Case (activate-precharge different bank)
APs Case (activate-precharge same bank)
RPd Case (read-precharge different bank)
RPs Case (read-precharge same bank)
WPd Case (write-precharge different bank)
WPs Case (write-precharge same bank)
PPd Case (precharge-precharge different bank)
PPs Case (precharge-precharge same bank)
b: ROWP Packet with PRE,Bb
Ba # Bb
a: ROWA Packet with ACT,Ba,Ra
b: ROWP Packet with PRR,Bb
Ba = Bb
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRE,Bb
Ba # Bb
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRR,Bb
Ba = Bb
a: COL Packet with WR,Ba,Ca
b: ROWP Packet with PRE,Bb
Ba # Bb
a: COL Packet with WR,Ba,Ca
b: ROWP Packet with PRE,Bb
Ba = Bb
a: ROWP Packet with PRE,Ba
b: ROWP Packet with PRE,Bb
Ba # Bb
a: ROWP Packet with PRE,Ba
b: ROWP Packet with PRE,Bb
Ba = Bb
No limit
a
WR
b
PRE
No limit
a
RD
b
PRE
t
RC
t
RP
t
RAS
a
PRE
b
PRE
b
ACT
No limit
a
ACT
b
PRE
t
PP
b
PRE
a
PRE
t
RAS
b
PRE
a
ACT
t
RDP
b
PRE
a
RD
t
WRP
b
PRE
a
WR
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Preliminary Data Sheet E0643E30 (Ver. 3.0)
20
EDX5116ABSE
Dynamic Request Scheduling
Delay fields are present in the ROWA, COL, and ROWP pack-
ets. They permit the associated command to optionally wait for
a time of one (or more) t
CYCLE
before taking effect. This
allows a memory controller more scheduling flexibility when
issuing request packets. Figure 8 illustrates the use of the delay
fields.
In the first timing diagram, a ROWA packet with an ACT com-
mand is present at cycle T
0
. The DELA field is set to "1". This
request packet will be equivalent to a ROWA packet with an
ACT command at cycle T
1
with the DELA field is set to "0".
This equivalence should be used when analyzing request packet
interactions.
In the second timing diagram, a COL packet with a RD com-
mand is present at cycle T
0
. The DELC field is set to "1". This
request packet will be equivalent to a COL packet with an RD
command at cycle T
1
with the DELC field is set to "0". This
equivalence should be used when analyzing request packet
interactions.
In a similar fashion, a COL packet with a WR command is
present at cycle T
12
. The DELC field is set to "1". This request
packet will be equivalent to a COL packet with a WR com-
mand at cycle T
13
with the DELC field is set to "0". This
equivalence should be used when analyzing request packet
interactions.
In the COL packet with a RD command example, the read data
delay T
CAC
is measured between the Q read data packet and
the virtual COL packet at cycle T
1
.
Likewise, for the example with the COL packet with a WR
command, the write data delay T
CWD
is measured between the
D write data packet and the virtual COL packet at cycle T
13
.
In the third timing diagram, a ROWP packet with a PRE com-
mand is present at cycle T
0
. The DEL field (POP[1:0]) is set to
"11". This request packet will be equivalent to a ROWP packet
with a PRE command at cycle T
1
with the DEL field is set to
"10", it will be equivalent to a ROWP packet with a PRE com-
mand at cycle T
2
with the DEL field is set to "01", and it will
be equivalent to a ROWP packet with a PRE command at cycle
T
3
with the DEL field is set to "00". This equivalence should
be used when analyzing request packet interactions.
In the fourth timing diagram, a ROWP packet with a REFP
command is present at cycle T
0
. The DEL field (RA[7:6]) is set
to "11". This request packet will be equivalent to a ROWP
packet with a REFP command at cycle T
1
with the DEL field
is set to "10", it will be equivalent to a ROWP packet with a
REFP command at cycle T
2
with the DEL field is set to "01",
and it will be equivalent to a ROWP packet with a REFP com-
mand at cycle T
3
with the DEL field is set to "00". This equiv-
alence should be used when analyzing request packet
interactions.
The two examples for the REFA and REFI commands are
identical to the example just described for the REFP com-
mand.
The ROWP packet allows two independent operations to be
specified. A PRE precharge command uses the POP and BP
fields, and the REFP, REFA, or REFI commands uses the
ROP and RA fields. Both operations have an optional delay
field (the POP field for the PRE command and the RA field
with the REFP, REFA, or REFI commands). The two delay
mechanisms are independent of one another. The POP field
does not affect the timing of the REFP, REFA, or REFI com-
mands, and the RA field does not affect the timing of the PRE
command.
When the interactions of a ROWP packet are analyzed, it must
be remembered that there are two independent commands
specified, both of which may affect how soon the next request
packet can be issued. The constraints from both commands in
a ROWP packet must be considered, and the one that requires
the longer time interval to the next request packet must be
used by the memory controller. Furthermore, the two com-
mands within a ROWP packet may not reference the same
bank in the BP and RA fields.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
21
EDX5116ABSE
Figure 8
Request Scheduling Examples
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
t
CAC
t
CYCLE
DEL0
ACT
Q
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
ROWA/ACT Command
COL/RD and COL/WR Commands
ROWP/PRE Command
DEL0
RD
t
CWD
D
DEL0
WR
DEL1
ACT
DEL1
RD
DEL1
WR
DEL2
PRE
DEL3
PRE
DEL0
PRE
DEL1
PRE
ACT w/DEL=1 at T
0
is equivalent
to ACT w/DEL=0 at T
1
RD w/DEL=1 at T
0
is equivalent
to RD w/DEL=0 at T
1
WR w/DEL=1 at T
12
is equivalent
to WR w/DEL=0 at T
13
PRE w/DEL=3 at T
0
is equivalent to PRE w/DEL
=2 at T
1
or PRE w/DEL=1 at T
2
or PRE w/DEL=0 at T
3
Note
DEL value is specified by {POP1, POP0} field.
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
ROWP/REFP,REFA,REFI Commands
DEL2
REFP
DEL3
REFP
DEL0
REFP
DEL1
REFP
REFP w/DEL=3 at T
0
is equivalent to REFP w/DEL=2
at T
1
or REFP w/DEL=1 at T
2
or REFP w/DEL=0 at T
3
Note
DEL value is specified by {RA7, RA6} field.
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DEL2
REFI
DEL3
REFI
DEL0
REFI
DEL1
REFI
REFI w/DEL=3 at T
13
is equivalent to REFI w/DEL=2
at T
14
or REFI w/DEL=1 at T
15
or REFI w/DEL=0 at T
16
DEL2
REFA
DEL3
REFA
DEL0
REFA
DEL1
REFA
at T
7
or REFA w/DEL=1 at T
8
or REFA w/DEL=0 at T
9
REFA w/DEL=3 at T
6
is equivalent to REFA w/DEL=2
Note
DEL value is specified by DELA field.
Note
DEL value is specified by DELC field.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
22
EDX5116ABSE
Memory Operations
Write Transactions
Figure 9 shows four examples of memory write transactions. A
transaction is one or more request packets (and the associated
data packets) needed to perform a memory access. The state of
the memory core and the address of the memory access deter-
mine how many request packets are needed to perform the
access.
The first timing diagram shows a page-hit write transaction. In
this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the
selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done
in the memory controller. In this example, the access is made
to row Ra of bank Ba.
In this case, write data may be directly written into the sense
amp array for the bank, and row operations (activate or pre-
charge) are not needed. A COL packet with WR command to
column Ca1 of bank Ba is presented on edge T
0
, and a second
COL packet with WR command to column Ca1 of bank Ba is
presented on edge T
2
. Two write data packets D(a1) and D(a2)
follow these COL packets after the write data delay t
CWD
. The
two COL packets are separated by the column-cycle time t
CC
.
This is also the length of each write data packet.
The second timing diagram shows an example of a page-miss
write transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank).
However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This
comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the
bank contains a row other than Ra.
In this case, write data may be not be directly written into the
sense amp array for the bank. It is necessary to close the
present row (precharge) and access the requested row (acti-
vate). A precharge command (PRE to bank Ba) is presented on
edge T
0
. An activate command (ACT to row Ra of bank Ba) is
presented on edge T
6
a time t
RP
later. A COL packet with WR
command to column Ca1 of bank Ba is presented on edge T
7
a
time t
RCD-W
later. A second COL packet with WR command
to column Ca2 of bank Ba is presented on edge T
9
. Two write
data packets D(a1) and D(a2) follow these COL packets after
the write data delay t
CWD
. The two COL packets are separated
by the column-cycle time t
CC
. This is also the length of each
write data packet.
The third timing diagram shows an example of a page-empty
write transaction. In this case, the selected bank is already
closed (no row is present in the sense amp array for the bank).
No row comparison is necessary for this case; however, the
memory controller must still remember that bank Ba has been
left closed. In this example, the access is made to row Ra of
bank Ba.
In this case, write data may be not be directly written into the
sense amp array for the bank. It is necessary to access the
requested row (activate). An activate command (ACT to row
Ra of bank Ba) is presented on edge T
0
. A COL packet with
WR command to column Ca1 of bank Ba is presented on edge
T
1
a time t
RCD-W
later. A second COL packet with WR com-
mand to column Ca2 of bank Ba is presented on edge T
3
. Two
write data packets D(a1) and D(a2) follow these COL packets
after the write data delay t
CWD
. The two COL packets are sepa-
rated by the column-cycle time t
CC
. This is also the length of
each write data packet. After the final write command, it may
be necessary to close the present row (precharge). A precharge
command (PRE to bank Ba) is presented on edge T
14
a time
t
WRP
after the last COL packet with a WR command. The
decision whether to close the bank or leave it open is made by
the memory controller and its page policy.
The fourth timing diagram shows another example of a page-
empty write transaction. This is similar to the previous example
except that only a single write command is presented, rather
than two write commands. This example shows that even with
a minimum length write transaction, the t
RAS
parameter will
not be a constraint. The t
RAS
measures the minimum time
between an activate command and a precharge command to a
bank. This time interval is also constrained by the sum t
RCD-
W
+t
WRP
which will be larger for a write transaction. These two
constraints ( t
RAS
and t
RCD-W
+t
WRP
) will be a function of the
memory device's speed bin and the data transfer length (the
number of write commands issued between the activate and
precharge commands), and the t
RAS
parameter could become a
constraint for write transactions for future speed bins. In this
example, the sum t
RCD-W
+t
WRP
is greater than t
RAS
by the
amount
t
RAS
.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
23
EDX5116ABSE
Figure 9
Write Transactions
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CC
t
CWD
t
CYCLE
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CWD
t
CYCLE
t
RP
t
RCD-W
a1
WR
a2
WR
a1
WR
a2
WR
a3
PRE
a0
ACT
D(a2)
D(a1)
D(a2)
D(a1)
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CWD
t
CYCLE
t
WRP
t
RCD-W
a1
WR
a2
WR
a3
PRE
a0
ACT
D(a2)
D(a1)
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CWD
t
CYCLE
t
RCD-W
a1
WR
a3
PRE
a0
ACT
D(a1)
t
RAS
Transaction b: WR
b0 = {Bb,Rb}
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
b3 = {Bb}
Bb = Ba
b0
ACT
t
RP
Page-hit Write Example
Page-miss Write Example
Page-empty Write Example
Page-empty Write Example - Core Limited
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
WRP
t
RAS
t
CWD
t
DP
Preliminary Data Sheet E0643E30 (Ver. 3.0)
24
EDX5116ABSE
Read Transactions
Figure 10 shows four examples of memory read transactions.
A transaction is one or more request packets (and the associ-
ated data packets) needed to perform a memory access. The
state of the memory core and the address of the memory
access determine how many request packets are needed to per-
form the access.
The first timing diagram shows a page-hit read transaction. In
this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the
selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done
in the memory controller. In this example, the access is made
to row Ra of bank Ba.
In this case, read data may be directly read from the sense amp
array for the bank, and no row operations (activate or pre-
charge) are needed. A COL packet with RD command to col-
umn Ca1 of bank Ba is presented on edge T
0
, and a second
COL packet with RD command to column Ca2 of bank Ba is
presented on edge T
2
. Two read data packets Q(a1) and Q(a2)
follow these COL packets after the read data delay t
CAC
. The
two COL packets are separated by the column-cycle time t
CC
.
This is also the length of each read data packet.
The second timing diagram shows an example of a page-miss
read transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank).
However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This
comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the
bank contains a row other than Ra.
In this case, read data may not be directly read from the sense
amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A pre-
charge command (PRE to bank Ba) is presented on edge T
0
.
An activate command (ACT to row Ra of bank Ba) is pre-
sented on edge T
6
a time t
RP
later. A COL packet with RD
command to column Ca1 of bank Ba is presented on edge T
11
a time t
RCD-R
later. A second COL packet with RD command
to column Ca2 of bank Ba is presented on edge T
13
. Two read
data packets Q(a1) and Q(a2) follow these COL packets after
the read data delay t
CAC
. The two COL packets are separated
by the column-cycle time t
CC
. This is also the length of each
read data packet.
The third timing diagram shows an example of a page-empty
write transaction. In this case, the selected bank is already
closed (no row is present in the sense amp array for the bank).
No row comparison is necessary for this case; however, the
memory controller must still remember that bank Ba has been
left closed. In this example, the access is made to row Ra of
bank Ba.
In this case, read data may not be directly read from the sense
amp array for the bank. It is necessary to access the requested
row (activate). An activate command (ACT to row Ra of bank
Ba) is presented on edge T
0
. A COL packet with RD com-
mand to column Ca1 of bank Ba is presented on edge T
5
a
time t
RCD-R
later. A second COL packet with RD command to
column Ca2 of bank Ba is presented on edge T
7
. Two read data
packets Q(a1) and Q(a2) follow these COL packets after the
read data delay t
CAC
. The two COL packets are separated by
the column-cycle time t
CC
. This is also the length of each read
data packet. After the final read command, it may be necessary
to close the present row (precharge). A precharge command --
PRE to bank Ba -- is presented on edge T
10
a time t
RDP
after
the last COL packet with a RD command. Whether the bank
is closed or left open depends on the memory controller and
its page policy.
The fourth timing diagram shows another example of a page-
empty read transaction. This is similar to the previous example
except that it uses one read command instead of two read com-
mands. In this case, the core parameter t
RAS
may also be a con-
straint upon when the precharge command may be issued.
The t
RAS
measures the minimum time between an activate
command and a precharge command to a bank. This time
interval is also constrained by the sum t
RCD-R
+ t
RDP
and must
be set to whichever is larger. These two constraints (t
RAS
and
t
RCD-R
+ t
RDP
) will be a function of the memory device's speed
bin and the data transfer length (the number of read com-
mands issued between the activate and precharge commands).
In this example, the t
RAS
is greater than the sum t
RCD-R
+ t
RDP
by the amount
t
RDP
.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
25
EDX5116ABSE
Figure 10
Read Transactions
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CAC
t
CYCLE
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CAC
t
CYCLE
t
RP
t
RCD-R
a1
RD
a2
RD
a1
RD
a2
RD
a3
PRE
a0
ACT
Q(a2)
Q(a1)
Q(a2)
Q(a1)
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CC
t
CAC
t
CYCLE
t
RDP
t
RCD-R
a1
RD
a2
RD
a3
PRE
a0
ACT
Q(a2)
Q(a1)
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
t
CAC
t
CYCLE
t
RCD-R
a1
RD
a3
PRE
a0
ACT
Q(a1)
t
RAS
Transaction b: RD
b0 = {Bb,Rb}
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
b3 = {Bb}
Bb = Ba
b0
ACT
t
RP
Page-hit Read Example
Page-miss Read Example
Page-empty Read Example
Page-empty Read Example - Core Limited
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
RDP
t
RDP
Preliminary Data Sheet E0643E30 (Ver. 3.0)
26
EDX5116ABSE
Interleaved Transactions
Figure 11 shows two examples of interleaved transactions.
Interleaved transactions are overlapped with one another; a
transaction is started before an earlier one is completed.
The timing diagram at the top of the figure shows interleaved
write transactions. Each transaction assumes a page-empty
access; that is, a bank is in a closed state prior to an access, and
is precharged after the access. With this assumption, each
transaction requires the same number of request packets at the
same relative positions. If banks were allowed to be in an open
state, then each transaction would require a different number
of request packets depending upon whether the transaction
was page-empty, page-hit, or page-miss. This situation is more
complicated for the memory controller, and will not be ana-
lyzed in this document.
In the interleaved page-empty write example, there are four
sets of request pins RQ11..0 shown along the left side of the
timing diagram. The first three show the timing slots used by
each of the three request packet types (ACT, COL, and PRE),
and the fourth set (ALL) shows the previous three merged
together. This allows the pattern used for allocating request
slots for the different packets to be seen more clearly.
The slots at {T
0
, T
4
, T
8
, T
12
, ...} are used for ROWA packets
with ACT commands. This spacing is determined by the t
RR
parameter. There should not be interference between the inter-
leaved transactions due to resource conflicts because each bank
address -- Ba, Bb, Bc, Bd, and Be -- is assumed to be differ-
ent from another. If two of the bank addresses are the same,
the later transaction would need to wait until the earlier trans-
action had completed its precharge operation. Five different
banks are needed because the effective t
RC
(t
RC
+
t
RC
) is
20*t
CYCLE
.
The slots at {T
1
, T
3
, T
5
, T
7
, T
9
, T
11
, ...} are used for COL
packets with WR commands. This frequency of the COL
packet spacing is determined by the t
CC
parameter and by the
fact that there are two column accesses per row access. The
phasing of the COL packet spacing is determined by the t
RCD-
W
parameter. If the value of t
RCD-W
required the COL packets
to occupy the same request slots as the ROWA packets (this
case is not shown), the DELC field in the COL packet could
be used to place the COL packet one t
CYCLE
earlier.
The DQ bus slots at {T
7
, T
9
, T
11
, T
13
, ...} carry the write data
packets {D(a1), D(a2), D(b1), D(b2), ....}. Two write data pack-
ets are written to a bank in each transaction. The DQ bus is
completely filled with write data; no idle cycles need to be
introduced because there are no resource conflicts in this
example.
The slots at {T
14
, T
18
, T
22
, ...} are used for ROWP packets
with PRE commands. This frequency of ROWP packet spac-
ing is determined by the t
PP
parameter. The phasing of the
ROWP packet spacing is determined by the t
WRP
parameter. If
the value of t
WRP
required the ROWP packets to occupy the
same request slots as the ROWA or COL packets already
assigned (this case is not shown), the delay field in the ROWP
packet could be used to place the ROWP packet one or more
t
CYCLE
s earlier.
There is an example of an interleaved page-empty read at the
bottom of the figure. As before, there are four sets of request
pins RQ11..0 shown along the left side of the timing diagram,
allowing the pattern used for allocating request slots for the
different packets to be seen more clearly.
The slots at {T
0
, T
4
, T
8
, T
12
, ...} are used for ROWA packets
with ACT commands. This spacing is determined by the t
RR
parameter. There should not be interference between the inter-
leaved transactions due to resource conflicts because each bank
address -- Ba, Bb, Bc, and Bd -- is assumed to be different
from another. Four different banks are needed because the
effective t
RC
is 16*t
CYCLE
.
The slots at {T
5
, T
7
, T
9
, T
11
, ...} are used for COL packets
with RD commands. This frequency of the COL packet spac-
ing is determined by the t
CC
parameter and by the fact that
there are two column accesses per row access. The phasing of
the COL packet spacing is determined by the t
RCD-R
parame-
ter. If the value of t
RCD-R
required the COL packets to occupy
the same request slots as the ROWA packets (this case is not
shown), the DELC field in the COL packet could be used to
place the packet one t
CYCLE
earlier.
The DQ bus slots at {T
11
, T
13
, T
15
, T
17
, ...} carry the read data
packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}. Two read data pack-
ets are read from a bank in each transaction. The DQ bus is
completely filled with read data -- that is, no idle cycles need
to be introduced because there are no resource conflicts in this
example.
The slots at {T
10
, T
14
, T
18
, T
22
, ...} are used for ROWP pack-
ets with PRE commands. This frequency of the ROWP packet
spacing is determined by the t
PP
parameter. The phasing of the
ROWP packet spacing is determined by the t
RDP
parameter. If
the value of t
RDP
required the ROWP packets to occupy the
same request slots as the ROWA or COL packets already
assigned (this case is not shown), the delay field in the ROWP
packet could be used to place the ROWP packet one or more
t
CYCLE
s earlier.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
27
EDX5116ABSE
Figure 11
Interleaved Transactions
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Transaction b: WR
b0 = {Bb,Rb}
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
b3 = {Bb}
Transaction c: WR
c0 = {Bc,Rc}
c1 = {Bc,Cc1}
c2 = {Bc,Cc2}
c3 = {Bc}
Transaction d: WR
d0 = {Bd,Rd}
d1 = {Bd,Cd1}
d2 = {Bd,Cd2}
d3 = {Bd}
Transaction e: WR
e0 = {Be,Re}
e1 = {Be,Ce1}
e2 = {Be,Ce2}
e3 = {Be}
Bf = Ba
are different
Ba,Bb,Bc,Bd,Be
D(a2)
D(a1)
D(b2)
D(b1)
D(c2)
Transaction a: RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Transaction b: RD
b0 = {Bb,Rb}
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
b3 = {Bb}
Transaction c: RD
c0 = {Bc,Rc}
c1 = {Bc,Cc1}
c2 = {Bc,Cc2}
c3 = {Bc}
Transaction d: RD
d0 = {Bd,Rd}
d1 = {Bd,Cd1}
d2 = {Bd,Cd2}
d3 = {Bd}
Transaction e: RD
e0 = {Be,Re}
e1 = {Be,Ce1}
e2 = {Be,Ce2}
e3 = {Be}
Be = Ba
different banks.
Ba,Bb,Bc,Bd are
Interleaved Page-empty Write Example
Interleaved Page-empty Read Example
Transaction f: WR
f0 = {Bf,Rf}
f1 = {Bf,Cf1}
f2 = {Bf,Cf2}
f3 = {Bf}
banks.
c0
ACT
d0
ACT
a0
ACT
b0
ACT
e0
ACT
b1
WR
b2
WR
c1
WR
c2
WR
d1
WR
d2
WR
e1
WR
e2
WR
t
RC
t
RCD-W
a1
WR
b1
WR
b2
WR
c1
WR
c2
WR
c0
ACT
d1
WR
d2
WR
d0
ACT
e1
WR
e2
WR
a2
WR
a3
PRE
a0
ACT
b3
PRE
b0
ACT
c3
PRE
e0
ACT
f0
ACT
b3
PRE
c3
PRE
t
CC
t
WRP
t
CWD
a1
WR
a2
WR
a3
PRE
t
RP
t
RR
D(c1)
t
RC
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
c0
ACT
d0
ACT
a0
ACT
b0
ACT
e0
ACT
f0
ACT
b1
RD
b2
RD
c1
RD
c2
RD
d1
RD
d2
RD
e1
RD
e2
RD
t
RC
t
RCD-R
a1
RD
b1
RD
b2
RD
c1
RD
c2
RD
c0
ACT
d1
RD
d2
RD
d0
ACT
e1
RD
e2
RD
a2
RD
a3
PRE
a0
ACT
b3
PRE
b0
ACT
d3
PRE
e0
ACT
f0
ACT
t
CC
t
RDP
t
CAC
a1
RD
a2
RD
t
RP
t
RR
c3
PRE
t
CYCLE
t
CYCLE
The effective t
RC
time is increased by 4 t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
(ACT)
RQ11..0
(COL)
RQ11..0
(PRE)
RQ11..0
(ALL)
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
(ACT)
RQ11..0
(COL)
RQ11..0
(PRE)
RQ11..0
(ALL)
Q(a2)
Q(a1)
Q(b2)
Q(b1)
Q(c2)
Q(c1)
D(d2)
D(e1)
f1
WR
f2
WR
D(d1)
f0
ACT
f1
WR
f2
WR
a3
PRE
b3
PRE
d3
PRE
c3
PRE
D(e1)
t
WRP
Preliminary Data Sheet E0643E30 (Ver. 3.0)
28
EDX5116ABSE
Read/Write Interaction
The previous section described overlapped read transactions
and overlapped write transactions in isolation. This section will
describe the interaction of read and write transactions and the
spacing required to avoid channel and core resource conflicts.
Figure 12 shows a timing diagram (top) for the first case, a
write transaction followed by a read transaction. Two COL
packets with WR commands are presented on cycles T
0
and
T
2
. The write data packets are presented a time t
CWD
later on
cycles T
4
and T
6
. The device requires a time t
WR
after the sec-
ond COL packet with a WR command before a COL packet
with a RD command may be presented. Two COL packets
with RD commands are presented on cycles T
11
and T
13
. The
read data packets are returned a time t
CAC
later on cycles T
17
and T
19
. The time t
WR
is required for turning around internal
bidirectional interconnections (inside the device). This time
must be observed regardless of whether the write and read
commands are directed to the same bank or different banks. A
gap t
WR-BUB,XDRDRAM
will appear on the DQ bus between the
end of the D(a2) packet and the beginning of the Q(b1) packet
(measured at the appropriate packet reference points). The size
of this gap can be evaluated by calculating the difference
between cycles T
2
and T
17
using the two timing paths:
t
WR-BUB,XDRDRAM
t
WR
+ t
CAC
- t
CWD
- t
CC
In this example, the value of t
WR-BUB,XDRDRAM
is greater than
its minimum value of t
WR-BUB,XDRDRAM,MIN
. The values of
t
RW
and
t
CAC
are equal to their minimum values.
In the second case, the timing diagram displayed at the bottom
of Figure 12 illustrates a read transaction followed by a write
transaction. Two COL packets with RD commands are pre-
sented on cycles T
0
and T
2
. The read data packets are returned
a time t
CAC
later on cycles T
6
and T
8
. The device requires a
time t
RW
after the second COL packet with a RD command
before a COL packet with a WR command may be presented.
Two COL packets with WR commands are presented on cycles
T
10
and T
12
. The write data packets are presented a time t
CWD
later on cycles T
13
and T
15
. The time t
RW
is required for turn-
ing around the external DQ bidirectional interconnections
(outside the device). This time must be observed regardless
whether the read and write commands are directed to the same
bank or different banks. The time t
RW
depends upon four
timing parameters, and may be evaluated by calculating the dif-
ference between cycles T
2
and T
13
using the two timing paths:
t
RW
+ t
CWD
= t
CAC
+ t
CC
+ t
RW-BUB,XDRDRAM
or
t
RW
= (t
CAC
- t
CWD
)+ t
CC
+ t
RW-BUB,XDRDRAM
In this example, the values of t
RW
, t
CAC
,
t
CWD
, t
CC
, and
t
RW-
BUB,XDRDRAM
are equal to their minimum values.
Propagation Delay
Figure 13 shows two timing diagrams that display the system-
level timing relationships between the memory component and
the memory controller.
The timing diagram at the top of the figure shows the case of a
write-read-write command and data at the memory compo-
nent. In this case, the timing will be identical to what has
already been shown in the previous sections; i.e. with all timing
measured at the pins of the memory component. This timing
diagram was produced by merging portions of the top and bot-
tom timing diagrams in Figure 12.
The example shown is that of a single COL packet with a write
command, followed by a single COL packet with a read com-
mand, followed by a second COL packet with a write com-
mand. These accesses all assume a page-hit to an open bank.
A timing interval t
WR
is required between the first WR com-
mand and the RD command, and a timing interval t
RW
is
required between the RD command and the second WR com-
mand. There is a write data delay t
CWD
between each WR com-
mand and the associated write data packet D. There is a read
data delay t
CAC
between the RD command and the associated
read data packet Q. In this example, all timing parameters have
assumed their minimum values except t
WR-BUB,XDRDRAM
.
The lower timing diagram in the figure shows the case where
timing skew is present between the memory controller and the
memory component. This skew is the result of the propagation
delay of signal wavefronts on the wires carrying the signals.
The example in the lower diagram assumes that there is a prop-
agation delay of t
PD-RQ
along both the RQ wires and the
CFM/CFMN clock wires between the memory controller and
the memory component (the value of t
PD-RQ
used here is
1*t
CYCLE
). Note that in an actual system the t
PD-RQ
value will
be different for each memory component connected to the RQ
wires.
In addition, it is assumed that there is a propagation delay t
PD-
D
along the DQ/DQN wires between the memory controller
and the memory component (the direction in which write data
travels, and it is assumed that there is the same propagation
delay t
PD-Q
along the DQ/DQN wires between the memory
component and the memory controller (the direction in which
read data travels). The sum of these two propagation delays is
also denoted by the timing parameter t
PD,CYC
= t
PD-D
+t
PD-Q
.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
29
EDX5116ABSE
Figure 12
Write/Read Interaction
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
Transaction a: WR
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
Transaction b: RD
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
b2
RD
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
b2
WR
D(b2)
t
CWD
Q(b2)
Q(b1)
t
CAC
a1
WR
t
CAC
a1
RD
t
CWD
b1
WR
D(b1)
t
RW
D(a2)
Q(a2)
a2
RD
D(a1)
Q(a1)
Write/Read Turnaround Example
Read/Write Turnaround Example
t
CYCLE
t
CYCLE
b1
RD
a2
WR
t
WR
DQ15..0
DQN15..0
DQ15..0
DQN15..0
t
RW-BUB,XDRDRAM
t
CC
t
CC
t
WR-BUB,XDRDRAM
t
CWD
t
DR
Transaction a: WR
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
Transaction b: RD
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
Preliminary Data Sheet E0643E30 (Ver. 3.0)
30
EDX5116ABSE
As a result of these propagation delays, the position of packets
will have timing skews that depend upon whether they are
measured at the pins of the memory controller or the pins of
the memory component. For example, the CFM/CFMN sig-
nals at the pins of the memory component are t
PD-RQ
later
than at the pins of the memory controller. This is shown by the
cycle numbering of the CFM/CFMN signals at the two loca-
tions
--
in this example cycle T
1
at the memory controller
aligns with cycle T
0
at the memory component.
All the request packets on the RQ wires will have a t
PD-RQ
skew at the memory component relative to the memory con-
troller in this example. Because the t
PD-D
propagation delay of
write data matches the t
PD-RQ
propagation delay of the write
command, the controller may issue the write data packet D(a0)
relative to the COL packet with the first write command "WR
a0" with the normal write data delay t
CWD
. If the propagation
delays between the memory controller and memory compo-
nent were different for the RQ and DQ buses (not shown in
this example), the write data delay at the memory controller
would need to be adjusted.
A propagation delay is seen by the read command -- that is,
the read command will be delayed by a t
PD-RQ
skew at the
memory component relative to the memory controller. The
memory component will return the read data packet Q(b0) rel-
ative to this read command with the normal read data delay
t
CAC
(at the pins of the memory component).
The read data packet will be skewed by an additional propaga-
tion delay of t
PD-Q
as it travels from the memory component
back to the memory controller. The effective read data delay
measured between the read command and the read data at the
memory controller will be t
CAC
+t
PD-RQ
+t
PD-Q
.
The t
PD-RQ
factor is caused by the propagation delay of the
request packets as they travel from memory controller to mem-
ory component. The t
PD-Q
factor is caused by the propagation
delay of the read data packets as they travel from memory com-
ponent to memory controller.
All timing parameters will be equal to their minimum values
except t
WR-BUB,XDRDRAM
(as in the top diagram), and the tim-
ing parameters t
RW-BUB,XDRDRAM
and t
RW
. These will be
larger than their minimum values by the amount (t
PD,CYC
-
t
PD,CYC,MIN
), where t
PD,CYC
= t
PD-D
+t
PD-Q
. This may be seen
by evaluating the two timing paths between cycle T
9
at the
Controller and cycle T
21
at the XDR DRAM:
t
RW
+ t
PD-RQ
+ t
CWD
=
t
PD-RQ
+ t
CAC
+ t
CC
+ t
RW-BUB,XDRDRAM
or
t
RW
= (t
CAC
- t
CWD
)+ t
CC
+ t
RW-BUB,XDRDRAM
The following relationship was shown for Figure 12
t
RW ,MIN
= (t
CAC
- t
CWD
)+ t
CC
+ t
RW-BUB,XDRDRAM,MIN
or
(t
RW
- t
RW ,MIN
)=
(t
RW-BUB,XDRDRAM
- t
RWBUB,XDRDRAM,MIN
)
In other words, the two timing parameters t
RW-BUB,XDRDRAM
and t
RW
will change together. The relationship of this change
to the propagation delay t
PD,CYC
(= t
PD-D
+t
PD-Q
) can be
derived by looking at the two timing paths from T15 to T21 at
the XDR DRAM:
t
PD-Q
+ t
CC
+ t
RW-BUB,XIO
+ t
PD-D
=
t
CC
+ t
RW-BUB,XDRDRAM
or
t
RW-BUB,XDRDRAM
= t
RW-BUB,XIO
+ t
PD-D
+ t
PD-Q
or
t
RW-BUB,XDRDRAM
= t
RW-BUB,XIO
+ t
PD,CYC
in a system with minimum propagation delays:
t
RW-BUB,XDRDRAM,MIN
= t
RW-BUB,XIO
+ t
PD,CYC,MIN
and since t
RW-BUB,XIO
is equal to t
RW-BUB,XIO,MIN
in both
cases, the following is true:
(t
PD,CYC
- t
PD,CYC,MIN
) =
(t
RW-BUB,XDRDRAM
- t
RW-BUB,XDRDRAM,MIN
) =
(t
RW
- t
RW ,MIN
)=
In other words, the values of the t
RW-BUB,XDRDRAM,MIN
and
t
RW ,MIN
timing parameters correspond to the value of
t
PD,CYC,MIN
for the system (this is equal to one t
CYCLE
). As
t
PD,CYC
is increased from this minimum value, t
RW-
BUB,XDRDRAM
and t
RW
increase from their minimum values
by an equivalent amount.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
31
EDX5116ABSE
Figure 13
Propagation Delay
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
8
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: WR
a0 = {Ba,Ca0}
Transaction c: WR
c0 = {Bc,Cc0}
Transaction b: RD
b0 = {Bb,Cb0}
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Write-Read-Write at
XDR DRAM
Write-Read-Write at Controller and
XDR DRAM
t
PD-RQ
a0
WR
a0
WR
t
PD-Q
t
PD-D
D(a0)
D(a0)
c0
WR
t
CYCLE
t
CYCLE
t
CYCLE
t
RW
t
WR
b0
RD
c0
WR
a0
WR
t
WR
b0
RD
t
PD-RQ
b0
RD
t
PD-D
t
CWD
t
CAC
D(a0)
Q(b0)
t
CWD
D(c0)
t
CWD
t
CAC
t
CWD
c0
WR
t
PD-RQ
Q(b0)
Q(b0)
D(c0)
D(c0)
Transaction a: WR
a0 = {Ba,Ca0}
Transaction c: WR
c0 = {Bc,Cc0}
Transaction b: RD
b0 = {Bb,Cb0}
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
XDR DRAM
Controller
XDR DRAM
T
-1
...
...
Controller
RQ
DQ
t
PD-RQ
t
PD-D
t
PD-Q
t
RW-BUB,XIO
t
CC
t
RW-BUB,XDRDRAM
t
CC
t
RW
w/ t
PD-RQ
= t
PD-Q
= t
PD-D
= 1*t
CYCLE
t
RW-BUB,XDRDRAM
t
WR-BUB,XDRDRAM
t
CC
(portions of top and bottom timing diagrams of Figure 12 merged)
t
CC
RQ
DQ
XDR DRAM
Preliminary Data Sheet E0643E30 (Ver. 3.0)
32
EDX5116ABSE
Register Operations
Serial Transactions
The serial interface consists of five pins. This includes RST,
SCK, CMD, SDI, and SDO. SDO uses CMOS signaling levels.
The other four pins use RSL signaling levels. RST, CMD, SDI,
and SDO use a timing window which surrounds the falling
edge of SCK). The RST pin is used for initialization.
Figure 14 and Figure 15 show examples of a serial write trans-
action and a serial read transaction. Each transaction starts on
cycle S
4
and requires 32 SCK edges. The next serial transaction
can begin on cycle S
36
. SCK does not need to be asserted if
there is no transaction.
Serial Write Transaction
The serial device write transaction in Figure 14 begins with the
Start[3:0] field. This consists of bits "1100" on the CMD pin.
This indicates to the XDR DRAM that the remaining 28 bits
constitute a serial transaction.
The next two bits are the SCMD[1:0] field. This field contains
the serial command, the bits 00 in the case of a serial device
write transaction.
The next eight bits are "00" and the SID[5:0] field. This field
contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field. This field contains
the serial address of the control register being accessed.
A single bit "0" follows next. This bit allows one cycle for the
access time to the control register.
The next eight bits on the CMD pin is the SWD[7:0] field. This
is the write data that is placed into the selected control register.
A final bit "0" is driven on the CMD pin to finish the serial
write transaction.
A serial broadcast write is identical except that the contents of
the SID[5:0] field in the transaction is ignored and all devices
preform the register write. The SDI and SDO pins are not
used during either serial write transaction.
Serial Read Transaction
The serial device read transaction in Figure 15 begins with the
Start[3:0] field. This consists of bits "1100" on the CMD pin.
This indicates that the remaining 28 bits constitute a serial
transaction.
The next two bits are the SCMD[1:0] field. This field contains
the serial command, and the bits "10" in the case of a serial
device read transaction.
The next eight bits are "00" and the SID[5:0] field. This field
contains the serial identification of the device being accessed.
The next eight bits are the SADR[7:0] field and contain the
serial address of the control register being accessed.
A single bit "0" follows next. This bit allows one cycle for the
access time to the control register and time to turn on the SDO
output driver.
The next eight bits on the CMD pin are the sequence
"00000000". At the same time, the eight bits on the SDO pin
are the SRD[7:0] field. This is the read data that is accessed
from the selected control register. Note the output timing con-
vention here: bit SRD[7] is driven from a time t
Q,SI,MAX
after
edge S
26
to a time t
Q,SI,MIN
after edge S
27
. The bit is sampled
in the controller by the edge S
27
A final bit "0" is driven on the CMD pin to finish the serial
read transaction.
A serial forced read is identical except that the contents of the
SID[5:0] field in the transaction is ignored and all devices pre-
form the register read. This is used for device testing.
Figure 16 shows the response of a DRAM to a serial device
read transaction when its internal SID[5:0] register field doesn't
match the SID[5:0] field of the transaction. Instead of driving
read data from an internal register for cycle edges S
27
through
S
34
on the SDO output pin, it passes the input data from the
SDI input pin to the SDO output pin during this same period.
Table 8
SCMD Field Encoding Summary
SCMD
[1:0]
Command
Description
00
SDW
Serial device write -- one device is written, the one whose SID[5:0] register matches the SID[5:0] field of the transaction.
01
SBW
Serial broadcast write -- all devices are written, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
10
SDR
Serial device read -- one device is read, the one whose SID[5:0] register matches the SID[5:0] field of the transaction.
11
SFR
Serial forced read -- all devices are read, regardless of the contents of the SID[5:0] register and the SID[5:0] transaction field
Preliminary Data Sheet E0643E30 (Ver. 3.0)
33
EDX5116ABSE
Figure 14
Serial Write Transaction
Figure 15
Serial Read Transaction -- Selected DRAM
Figure 16
Serial Read Transaction -- Non-selected DRAM
S
0
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
18
S
20
S
22
S
24
S
26
S
28
S
30
S
32
S
34
S
36
S
38
S
40
S
42
S
44
S
46
S
16
S
48
2
4 3
5
0
1
`0'
`0'
2'h0,SID[5:0]
`0' `0'
SCMD
transaction
t
CYC,SCK
`1' `1' `0' `0'
Start
2
4 3
5
0
1
6
7
SWD[7:0]
`0'
`0'
RST
SDI
(input)
SCK
CMD
SDO
(output)
2
4 3
5
0
1
6
7
SADR[7:0]
S
0
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
18
S
20
S
22
S
24
S
26
S
28
S
30
S
32
S
34
S
36
S
38
S
40
S
42
S
44
S
46
S
16
S
48
2
4 3
5
0
1
`0'
`0'
2'h0,SID[5:0]
`1' `0'
SCMD
transaction
t
CYC,SCK
'0'
`0' `0'
`0'
`0'
`0'
`0'
`0'
8'h00
`1' `1' `0' `0'
Start
`0'
`0'
RST
SDI
(input)
SCK
CMD
SDO
(output)
2
4 3
5
0
1
6
7
SADR[7:0]
2
4 3
5
0
1
6
7
SRD[7:0]
S
0
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
18
S
20
S
22
S
24
S
26
S
28
S
30
S
32
S
34
S
36
S
38
S
40
S
42
S
44
S
46
S
16
S
48
2
4 3
5
0
1
`0'
`0'
2'h0,SID[5:0]
`1' `0'
SCMD
transaction
t
CYC,SCK
'0'
`0' `0'
`0'
`0'
`0'
`0'
`0'
8'h00
`1' `1' `0' `0'
Start
`0'
`0'
RST
SDI
(input)
SCK
CMD
SDO
(output)
2
4 3
5
0
1
6
7
SADR[7:0]
2
4 3
5
0
1
6
7
SRD[7:0]
2
4 3
5
0
1
6
7
SRD[7:0]
SDI
SDO
t
P,SI
S
28
combinational
propagation
from SDI to SDO
Preliminary Data Sheet E0643E30 (Ver. 3.0)
34
EDX5116ABSE
Register Summary
Figure 17 through Figure 33 show the control registers in the
memory component. The control registers are responsible for
configuring the component's operating mode, for managing
power state transitions, for managing refresh, and for manag-
ing calibration operations.
A control register may contain up to eight bits. Each figure
shows defined bits in white and reserved bits in gray. Reserved
bits must be written as 0 and must be ignored when read.
Write-only fields must be ignored when read
Each figure displays the following register information:
1. register name
2. register mnemonic
3. register address (SADR[7:0] value needed to access it)
4. read-only, write-only or read-write
5. initialization state
6. description of each defined register field
Figure 17 shows the Serial Identification register. This register
contains the SID[5:0] (serial identification field). This field
contains the serial identification value for the device. The value
is compared to the SID[5:0] field of a serial transaction to
determine if the serial transaction is directed to this device. The
serial identification value is set during the initialization
sequence.
Figure 18 shows the Configuration Register. It contains three
fields. The first is the WIDTH field. This field allows the num-
ber of DQ/DQN pins used for memory read and write
accesses to be adjusted. The SLE field enables data to be writ-
ten into the memory through the serial interface using the
WDSL register.
Figure 19 shows the Power Management Register. It contains
two fields. The first is the PX field. When this field is written
with a 1, the memory component transitions from powerdown
to active state. It is usually unnecessary to write a 0 into this
field; this is done automatically by the PDN command in a
COLX packet. The PST field indicates the current power state
of the memory component.
Figure 20 shows the Write Data Serial Load Register. It permits
data to be written into memory via the Serial Interface.
Figure 23 shows the Refresh Bank Control Register. It contains
two fields: BANK and MBR. The BANK field is read-write
and contains the bank address used by self-refresh during the
powerdown state. The MBR field controls how many banks are
refreshed during each refresh operation. Figure 24, Figure 25,
and Figure 26 show different fields of the Refresh Row Regis-
ter (high, middle, and low). This read-write field contains the
row address used by self- and auto-refresh. See "Refresh Trans-
actions" on page 40 for more details.
Figure 28 and Figure 29 show the Current Calibration 0 and 1
registers. They contain the CCVALUE0 and CCVALUE1
fields, respectively. These are read-write fields which control
the amount of IOL current driven by the DQ and DQN pins
during a read transaction. The Current Calibration 0 Register
controls the even-numbered DQ and DQN pins, and the Cur-
rent Calibration 1 controls the odd-numbered DQ and DQN
pins.
Figure 32 shows the test registers. It is used during device test-
ing. It is not to be read or written during normal operation.
Figure 33 shows the DLY register. This is used to set the value
of t
CAC
and t
CWD
used by the component. See "Timing
Parameters" on page 62
Figure 17
Serial Identification (SID) Register
7
6
5
4
3
2
1
0
Read-only register
SID[7:0] resets to 00000000
2
SID[5:0]
reserved
SID[5:0] - Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID[5:0] field of a serial transaction
to determine if the serial transaction is directed to this device.
The serial identification value is set during the initialization
sequence.
Serial Identification Register
SADR[7:0]: 00000001
2
Preliminary Data Sheet E0643E30 (Ver. 3.0)
35
EDX5116ABSE
Figure 18
Configuration (CFG) Register
Figure 19
Power Management (PM) Register
Figure 20
Write Data Serial Load (WDSL) Control Register
7
6
5
4
3
2
1
0
Read/write register
CFG[7:0] resets to 00000100
2
WIDTH[2:0]
rsrv
WIDTH[2:0] - Device interface width field.
000
2
- Reserved.
001
2
- Reserved
010
2
- x4 device width
011
2
- x8 device width
100
2
- x16 device width
101
2
, 110
2
, 111
2
- Reserved
SLE - Serial Load enable field.
0
2
- WDSL-path-to-memory disabled
1
2
- WDSL-path-to-memory enabled
Configuration Register
SADR[7:0]: 00000010
2
rsrv
SLE
rsrv
7
6
5
4
3
2
1
0
Read/write register
PM[7:0] resets to 00000000
2
PX
reserved
PX - Powerdown exit field.(write-one-only, read=zero)
0
2
- Powerdown entry - do not write zero - use PDN command
1
2
- Powerdown exit - write one to exit
PST[1:0]
PST[1:0] - Power state field (read-only).
00
2
- Powerdown (with self-refresh)
01
2
- Active/active-idle
10
2
- reserved
11
2
- reserved
Power Management Register
SADR[7:0]: 00000011
2
7
6
5
4
3
2
1
0
Read/write register
WDSL[7:0] resets to 00000000
2
WDSD[7:0] - Writing to this register places eight bits of data into
the serial-to-parallel conversion logic (the "Demux" block of
Figure 2). Writing to this register "2x16" times accumulates a full
"t
CC
" worth of write data. A subsequent WR command (with
SLE=1 in CFG register in Figure 32) will write this data (rather
than DQ data) to the sense amps of a memory bank. The shifting
order of the write data is shown in Table 10.
Write Data Serial Load Control Register
SADR[7:0]: 00000100
2
WDSD[7:0]
Preliminary Data Sheet E0643E30 (Ver. 3.0)
36
EDX5116ABSE
Figure 21
RQ Scan High (RQH) Register
Figure 22
RQ Scan Low (RQL) Register
Figure 23
Refresh Bank (REFB) Control Register
7
6
5
4
3
2
1
0
Read/write register
RQH[7:0] resets to 00000000
2
RQH[3:0] - Latched value of RQ[11:8] in RQ wire test mode.
RQ Scan High Register
SADR[7:0]: 00000110
2
RQH[3:0]
reserved
7
6
5
4
3
2
1
0
Read/write register
RQL[7:0] resets to 00000000
2
RQL[7:0] - Latched value of RQ[7:0] in RQ wire test mode.
RQ Scan Low Register
SADR[7:0]: 00000111
2
RQL[7:0]
7
6
5
4
3
2
1
0
Read/write register
REFB[7:0] resets to 00000000
2
reserved
BANK[2:0] - Refresh bank field.
This field returns the bank address for the next self-refresh oper-
ation when in Powerdown power state.
MBR[1:0] - Multi-bank and multi-row refresh control field.
00
2
- Single-bank refresh. 10
2
- Reserved
01
2
- Reserved 11
2
- Reserved
Refresh Bank Control Register
SADR[7:0]: 00001000
2
BANK[2:0]
MBR[1:0]
Preliminary Data Sheet E0643E30 (Ver. 3.0)
37
EDX5116ABSE
Figure 24
Refresh High (REFH) Row Register
Figure 25
Refresh Middle (REFM) Row Register
Figure 26
Refresh Low (REFL) Row Register
Figure 27
IO Configuration (IOCFG) Register
7
6
5
4
3
2
1
0
Read/write register
REFH[7:0] resets to 00000000
2
R[18:16]
reserved
reserved - Refresh row field.
This field contains the high-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the max-
imum bank address for self-refresh.
Refresh High Row Register
SADR[7:0]: 00001001
2
7
6
5
4
3
2
1
0
Read/write register
REFM[7:0] resets to 00000000
2
R[11:8] - Refresh row field.
This field contains the middle-order bits of the row address that
will be refreshed during the next refresh interval. This row
address will be incremented after a REFI command for auto-
refresh, or when the BANK[2:0] field for the REFB register
equals the maximum bank address for self-refresh.
Refresh Middle Row Register
SADR[7:0]: 00001010
2
R[11:8]
reserved
7
6
5
4
3
2
1
0
Read/write register
REFL[7:0] resets to 00000000
2
R[7:0]
R[7:0] - Refresh row field.
This field contains the low-order bits of the row address that will
be refreshed during the next refresh interval. This row address
will be incremented after a REFI command for auto-refresh, or
when the BANK[2:0] field for the REFB register equals the max-
imum bank address for self-refresh.
Refresh Low Row Register
SADR[7:0]: 00001011
2
7
6
5
4
3
2
1
0
Read/write register
IOCFG[7:0] resets to 00000000
2
ODF[1:0]
ODF[1:0] - Overdrive Function field.
00 - Nominal V
OSW,DQ
range
01 - reserved
10 - reserved
11 - reserved
IO Configuration Register
SADR[7:0]: 00001111
2
reserved
Preliminary Data Sheet E0643E30 (Ver. 3.0)
38
EDX5116ABSE
Figure 28
Current Calibration 0 (CC0) Register
Figure 29
Current Calibration 1 (CC1) Register
Figure 30
Read Only Memory 0 (ROM0) Register
Figure 31
Read Only Memory 1 (ROM1) Register
7
6
5
4
3
2
1
0
Read/write register
CC0[7:0] resets to 00001111
2
CCVALUE0[5:0]
reserved
CCVALUE0[5:0] - Current calibration value field.
This field controls the amount of current drive for the even-num-
bered DQ and DQN pins.
Current Calibration 0 Register
SADR[7:0]: 00010000
2
7
6
5
4
3
2
1
0
Read/write register
CC1[7:0] resets to 00001111
2
CCVALUE1[5:0]
reserved
CCVALUE1[5:0] - Current calibration value field.
This field controls the amount of current drive for the odd-num-
bered DQ and DQN pins.
Current Calibration 1 Register
SADR[7:0]: 00010001
2
7
6
5
4
3
2
1
0
Read-only register
ROM0[7:0] resets to 0010mmmm
MASK[3:0] - Version number of mask (0001
2
is first version).
VENDOR[3:0] - Vendor number for component:
0010 - Elpida
Read Only Memory 0 Register
SADR[7:0]: 00010110
2
MASK[3:0]
reserved
VENDOR[3:0]
7
6
5
4
3
2
1
0
Read-only register
ROM0[7:0] resets to bbrrrccc
CB[2:0] - Column address bits: #bits = 6 +CB[2:0]
RB[2:0] - Row address bits: #bits = 10 +RB[2:0]
BB[1:0] - Bank address bits: #bits = 2 +BB[1:0]
These three fields indicate how many column, row, and bank
address bits are present. An offset of {6,10,2} is added to the
field value to give the number of address bits.
Read Only Memory 1 Register
SADR[7:0]: 00010111
2
CB[2:0]
RB[2:0]
BB[1:0]
Preliminary Data Sheet E0643E30 (Ver. 3.0)
39
EDX5116ABSE
Figure 32
TEST Register
Figure 33
Delay (DLY) Control Register
7
6
5
4
3
2
1
0
Read/write register
TEST[7:0] resets to 00000000
2
WTE - Wire Test Enable
WTL - Wire Test Latch
TEST Register
SADR[7:0]: 00011000
2
reserved
WTE
WTL
7
6
5
4
3
2
1
0
Read/write register
DLY[7:0] resets to 00110110
2
CAC[3:0] - Programmed value of t
CAC
timing parameter:
0110
2
- t
CAC
= 6*t
CYCLE
1000
2
- t
CAC
= 8*t
CYCLE
0111
2
- t
CAC
= 7*t
CYCLE
others - Reserved.
CWD[3:0]
DLY Register
SADR[7:0]: 00011111
2
CAC[3:0]
CWD[3:0] - Programmed value of t
CWD
timing parameter:
0011
2
- t
CWD
= 3*t
CYCLE
0100
2
- t
CWD
= 4*t
CYCLE
others - Reserved.
Following SADR [7:0] registers are reserved:
00010010
2
, 00010011
2
, 00010100
2
, 00010101
2
, 00011001
2
, 00011010
2
, 00011011
2
, 00011100
2
, 00011101
2
,
10000000
2
-
10001111
2
.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
40
EDX5116ABSE
Maintenance Operations
Refresh Transactions
Figure 34 contains two timing diagrams showing examples of
refresh transactions. The top timing diagram shows a single
refresh operation. Bank Ba is assumed to be closed (in a pre-
charged state) when a REFA command is received in a ROWP
packet on clock edge T
0
. The REFA command causes the row
addressed by the REFr register (REFH/REFM/REFL) to be
opened (sensed) and placed in the sense amp array for the
bank.
Note that the REFA and REFI commands are similar to the
ACT command functionally; both specify a bank address and
delay value, and both cause the selected bank to open (to
become sensed.) The difference is that the ACT command is
accompanied by a row address in the ROWA packet, while the
REFA and REFI commands use a row address in the REFr
register (REFH/REFM/REFL).
After a time t
RAS
, a ROWP packet with REFP command to
bank Ba is presented. This causes the bank to be closed (pre-
charged), leaving the bank in the same state as when the refresh
transaction began.
Note that the REFP command is equivalent to the PRE com-
mand functionally; both specify a bank address and delay value,
and both cause the selected bank to close (to become pre-
charged).
After a time t
RP
, another ROWP packet with REFA command
to bank Bb is presented (banks Ba and Bb are the same in this
example). This starts a second refresh cycle. Each refresh
transaction requires a total time t
RC
= t
RAS
+ t
RP
, but refresh
transactions to different banks may be interleaved like normal
read and write transactions.
Each row of each bank must be refreshed once in every t
REF
interval. This is shown with the fourth ROWP packet with a
REFA command in the top timing diagram.
Interleaved Refresh Transactions
The lower timing diagram in Figure 34 represents one way a
memory controller might handle refresh maintenance in a real
system.
A series of eight ROWP packets with REFA commands
(except for the last which is a REFI command) are presented
starting at edge T
0
. The packets are spaced with intervals of
t
RR
. Each REFA or REFI command is addressed to a different
bank (Ba through Bh) but uses the same row address from the
REFr (REFH/REFM/REFL) register. The eighth REFI com-
mand uses this address and then increments it so the next set
of eight REFA/REFI commands will refresh the next set of
rows in each bank.
A series of eight ROWP packets with REFP commands are
presented effectively at edge T
10
(a time t
RAS
after the first
ROWP packet with a REFA command). The packets are
spaced with intervals of t
PP
. Like the REFA/REFI commands,
each REFP command is addressed to a different bank (Ba
through Bh).
This burst of eight refresh transactions fully utilizes the mem-
ory component. However, other read and write transactions
may be interleaved with the refresh transactions before and
after the burst to prevent any loss of bus efficiency. In other
words, a ROWA packet with ACT command for a read or write
could have been presented at edge T
-4
(a time t
RR
before the
first refresh transaction starts at edge T
0
). Also, a ROWA
packet with ACT command for a read or write could have been
presented at edge T
36
(a time t
RR
after the last refresh transac-
tion starts at edge T
32
). In both cases, the other request packets
for the interleaved read or write accesses (the precharge com-
mands and the read or write commands) could be slotted in
among the request packets for the refresh transactions.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
41
EDX5116ABSE
Figure 34
Refresh Transactions
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
Transaction a: REF
a0 = {Ba,REFR}
a1 = {Ba}
t
CYCLE
T
24
T
25
T
26
T
27
T
28
T
29
T
30
T
31
T
33
T
34
T
35
T
36
T
37
T
38
T
39
T
40
T
41
T
42
T
43
T
44
T
45
T
46
T
47
T
32
Refresh Transaction
Interleaved Refresh Example
b0
REFA
t
RR
a1
REFP
a0
REFA
Transaction b: REF
a0 = {Ba,REFR}
b1 = {Bb}
Bb = Ba
t
RC
c0
REFA
d0
REFA
e0
REFA
t
CYCLE
a1
REFP
b1
REFP
c1
REFP
d1
REFP
f0
REFA
g0
REFA
h0
REFI
e1
REFP
f1
REFP
g1
REFP
h1
REFP
g0
REFA
h0
REFA
a0
REFA
b0
REFA
c0
REFA
d0
REFA
e0
REFA
f0
REFA
a0
REFA
b0
REFA
t
REF
t
RP
t
RAS
c0
REFA
Transaction c: REF
c0 = {Bc,REFR}
c1 = {Bc}
Bc/Rc = Ba/Ra
Transaction a: REF
a0 = {Ba,REFR}
a1 = {Ba}
Transaction b: REF
b0 = {Bb,REFR}
b1 = {Bb}
Transaction c: REF
c0 = {Bc,REFR}
c1 = {Bc}
Transaction d: REF
d0 = {Bd,REFR}
d1 = {Bd}
Transaction e: REF
e0 = {Be,REFR}
e1 = {Be}
Ba,Bb,Bc,Bd,
Transaction f: REF
f0 = {Bc,REFR}
f1 = {Bf}
Transaction g: REF
g0 = {Bd,REFR}
g1 = {Bg}
Transaction h: REF
h0 = {Be,REFR}
h1 = {Bh}
different banks.
Bh are
Be,Bf,Bg and
i0
REFA
Transaction i: REF
i0 = {Ba,REFR+1}
i1 = {Bi}
Bi = Ba
This REFI increments REFR
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
(ACT)
RQ11..0
(PRE)
RQ11..0
(ALL)
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
(ACT)
RQ11..0
(PRE)
RQ11..0
(ALL)
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
e1
REFP
f1
REFP
g1
REFP
h1
REFP
a1
REFP
b1
REFP
c1
REFP
d1
REFP
i0
REFA
Preliminary Data Sheet E0643E30 (Ver. 3.0)
42
EDX5116ABSE
Calibration Transactions
Figure 35 shows the calibration transaction diagrams for the
XDR DRAM device. There is one calibration operation sup-
ported: calibration of the output current level I
OL
for each
DQi and DQNi pin.
The output current calibration sequence is shown in the upper
diagram. It begins when a period of t
CMD-CALC
is observed
after the last RQ packet (with command "CMD a" in this
example). No request packets should be issued in this period.
A COLX packet with a"CALC b" command is then issued to
start the current calibration sequence. A period of t
CALCE
is
observed after this packet. No request packets should be issued
during this period.
A COLX packet with a "CALE c" command is then issued to
end the current calibration sequence. A period of t
CALE-CMD
is
observed after this packet. No request packets should be issued
during this period. The first request packet may then be issued
(with command "CMD d" in this example).
A second current calibration sequence must be started within
an interval of t
CALC
. In this example, the next COLX packet
with a "CALC e" command starts a subsequent sequence.
The dynamic termination calibration sequence is shown in the
lower diagram. Note that this memory component does not
use this sequence; termination calibration is performed during
the manufacturing process. However, the termination sequence
shown will be issued by the controller for those memory com-
ponents which do use a periodic calibration mechanism.
It begins when a period of t
CMD-CALZ
is observed after the
packet at edge T
0
(with command CMDa in this example). No
request packets should be issued in this period.
A COLX packet with a CALZ command is then issued at edge
T
3
to start the termination calibration sequence. A second
period of t
CALZE
is observed after this packet. No request
packets should be issued during this period.
A COLX packet with a CALE command is then issued at edge
T
6
to end the termination calibration sequence. A third period
of t
CALE-CMD
is observed after this packet. No request packets
should be issued during this period. The first request packet
may be issued at edge T
12
(with command CMDd in this exam-
ple).
A second termination calibration sequence must be started
within an interval of t
CALZ
. In this example, the next COLX
packet with a CALZ command occurs at edge T
20
.
Note that the labels for the CFM clock edges (of the form T
i
)
are not to scale, and are used to identify events in the diagrams.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
43
EDX5116ABSE
Figure 35
Calibration Transactions
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
Packet a: Any CMD
t
CYCLE
Current Calibration Transaction
Packet b: CALC
t
CALC
Termination Calibration Transaction
a
t
CALE-CMD,
Packet d: Any CMD
c
CALE
e
CALC
a
CMD
d
CMD
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
t
CYCLE
t
CALZ
t
CALE-CMD,
c
CALE
e
CALZ
a
CMD
d
CMD
DQ15..0
DQN15..0
DQ15..0
DQN15..0
RQ11..0
CFM
CFMN
CFM
CFMN
RQ11..0
t
CALCE,
Packet e: CALC
Packet c: CALE
t
CMD-CALC
b
CALC
t
CMD-CALZ
b
CALZ
Packet a: Any CMD
Packet b: CALZ
Packet d: Any CMD
Packet e: CALZ
Packet c: CALE
t
CALZE,
a) EDX5116ABSE does not use Termination Calibration Transaction sequence.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
44
EDX5116ABSE
Power State Management
Figure 36 shows power state transition diagrams for the XDR
DRAM device. There are two power states in the XDR
DRAM: Powerdown and Active. Powerdown state is to be used
in applications in which it is necessary to shut down the CFM/
CFMN clock signals. In this state, the contents of the storage
cells of the XDR DRAM will be retained by an internal state
machine which performs periodic refresh operations using the
REFB and REFr control registers.
The upper diagram shows the sequence needed for Power-
down entry. Prior to starting the sequence, all banks of the
XDR DRAM must be precharged so they are left in a closed
state. Also, all 2
3
banks must be refreshed using the current
value of the REFr registers, and the REFr registers must NOT be
incremented with the REFI command at the end of this special set of
refresh transactions. This ensures that no matter what value has
been left in the REFB register, no row of any bank will be
skipped when automatic refresh is first started in Powerdown.
There may be some banks at the current row value in the REFr
registers that are refreshed twice during the Powerdown entry
process.
After the last request packet (with the command CMDa in the
upper diagram of the figure), an interval of t
CMD-PDN
is
observed. No request packets should be issued during this
period.
A COLX packet with the PDN command is issued after this
interval, causing the XDR DRAM to enter Powerdown state
after an interval of t
PDN-ENTRY
has elapsed (this is the parame-
ter that should be used for calculating the power dissipation of
the XDR DRAM). The CFM/CFMN clock signals may be
removed a time t
PDN-CFM
after the COLX packet with the
PDN command. Also, the termination voltage supply may be
removed (set to the ground reference) from the VTERM pins a
time t
PDN-CFM
after the COLX packet with the PDN com-
mand. The voltage on the DQ/DQN pins will follow the volt-
age on the VTERM pins during Powerdown entry.
When the XDR DRAM is in Powerdown, an internal fre-
quency source and state machine will automatically generate
internal refresh transactions. It will cycle through all 2
3
state
combinations of the REFB register. When the largest value is
reached and the REFB value wraps around, the REFr register
is incremented to the next value. The REFB and REFr values
select which bank and which row are refreshed during the next
automatic refresh transaction.
The lower diagram shows the sequence needed for Powerdown
exit. The sequence is started with a serial broadcast write (SBW
command) transaction using the serial bus of the XDR
DRAM. This transaction writes the value "00000001" to the
Power Management (PM) register (SADR="00000011") of all
XDR DRAMs connected to the serial bus. This sets the PX bit
of the PM register, causing the XDR DRAMs to return to
Active power state.
The CFM/CFMN clock signals must be stable a time t
CFM-
PDN
before the end of the SBW transaction. Also, the termina-
tion voltage supply must be restored to its normal operating
point (V
TERM,DRSL
) on the VTERM pins a time t
CFM-PDN
before the end of the SBW transaction. The voltage on the
DQ/DQN pins will follow the voltage on the VTERM pins
during Powerdown exit.
The XDR DRAM will enter Active state after an interval of
t
PDN-EXIT
has elapsed from the end of the SBW transaction
(this is the parameter that should be used for calculating the
power dissipation of the XDR DRAM).
The first request packet may be issued after an interval of
t
PDN-CMD
has elapsed from the end of the SBW transaction,
and must contain a "REFA" command in a ROWP packet. In this
example, this packet is denoted with the command "REFA 1".
No other request packets should be issued during this t
PDN-
CMD
interval.
All "n" banks (in the example, n=2
3
)
must be refreshed using
the current value of the REFr registers. The "nth" refresh
transaction will use a "REFI" command to increment the
REFr register (instead of a "REFR" command). This ensures
that no matter what value has been left in the REFB register,
no row of any bank will be skipped when normal refresh is
restarted in Active state. There may be some banks at the cur-
rent row value in the REFr registers that are refreshed twice
during the Powerdown exit process.
Note that during the Powerdown state an internal time source
keeps the device refreshed. However, during the t
PDN-CMD
interval, no internal refresh operations are performed. As a
result, an additional burst of refresh transactions must be
issued after the burst of "n" transactions described above.
This second burst consists of "m" refresh transactions:
m = ceiling[2
3
*2
12
*t
PDN-CMD
/t
REF
]
Where "2
12
" is the number of rows per bank, and "2
3
" is the
number of banks. Every "nth" refresh transaction (where
n=2
3
) will use a "REFI" command (to increment the REFr
register) instead of a "REFA" command.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
45
EDX5116ABSE
Figure 36
Power State Management
Transaction a: Last precharge command
t
CYCLE
Powerdown Entry
CMD
Transaction b: PDN
t
CMD-PDN
Transaction 1: REFA
t
CYCLE
Powerdown Exit
Transaction 2: REFA
S
0
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
18
S
20
S
22
S
24
S
26
S
28
S
30
S
32
S
34
S
16
`0' `0'
SCMD
Power-up transaction
t
CYC,SCK
a
PDN
t
PDN-ENTRY
Powerdown State...
t
CYCLE
1
REFA
n
REFP
`1' `1' `0' `0'
Start
t
PDN-EXIT
t
PDN-CMD
2
REFA
Transaction n: REFI
n-1
REFP
t
PDN-CFM
No signal
No signal
t
CFM-PDN
....Powerdown State
RST
SCK
CMD
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
a
PDN
b
2
4 3
5
0
1
`0'
`0'
2'h0,SID[5:0]
2
4 3
5
0
1
6
7
SWD[7:0]
`0'
`0'
SDI
(input)
SDO
(output)
2
4 3
5
0
1
6
7
SADR[7:0]
n-2
REFP
n
REFI
The final REFA/REFI command increments the REFr register
Transaction n-1: REFA
t
PDN-CMD
Preliminary Data Sheet E0643E30 (Ver. 3.0)
46
EDX5116ABSE
Initialization
Figure 37 shows the topology of the serial interface signals of a
XDR DRAM system. The three signals RST, CMD, and SCK
are transmitted by the controller and are received by each XDR
DRAM device along the bus. The signals are terminated to the
VTERM supply through termination components at the end
farthest from the controller. The SDI input of the XDR
DRAM device furthest from the controller is also terminated
to VTERM. The SDO output of each XDR DRAM device is
transmitted to the SDI input of the next XDR DRAM device
(in the direction of the controller). This SDO/SDI daisy-chain
topology continues to the controller, where it ends at the SRD
input of the controller. All the serial interface signals are low-
true. All the signals use RSL signaling circuits, except for the
SDO output which uses CMOS signaling circuits.
Figure 37
Serial Interface System Topology
Figure 38 shows the initialization timing of the serial interface
for the XDR DRAM[k] device in the system shown above.
Prior to initialization, the RST is held at zero. The CMD input
is not used here, and should also be held at zero. Note that the
inputs are all sampled by the negative edge of the SCK clock
input. The SDI input for the XDR DRAM[0] device is zero,
and is unknown for the remaining devices.
On negative SCK edge S
8
the RST input is sampled one. It is
sampled one on the next four edges, and is sampled zero on
edge S
12
a time t
RST-10
after it was first sampled one. The state
of the control registers in the XDR DRAM device are set to
their reset values after the first edge (S
8
) in which RST is sam-
pled one.
Figure 38
Initialization Timing for XDR DRAM[k] Device
The SDI inputs will be sampled one within a time t
RST-SDO,11
after RST is first sampled one in all the XDR DRAMs except
for XDR DRAM[0]. XDR DRAM[0]'s SDI input will always
be sampled zero.
XDR DRAM[k] will see its RST input sampled zero at S
12
, and
will then see its SDI input sampled zero at S
16
(after SDI had
XDR DRAM
RST CMD SCK
SDO
SDI
XDR DRAM
RST CMD SCK
SDO
SDI
XDR DRAM
RST CMD SCK
SDO
SDI
Controller
RST CMD SCK
SRD
...
...
VTERM
S
0
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
18
S
20
S
22
S
24
S
26
S
28
S
30
S
32
S
34
S
36
S
38
S
Poweron
S
16
t
CYC,SCK
RST
SDI
(input)
SCK
CMD
SDO
(output)
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`1'
`1'
`1'
`1'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`x'
`x'
`x'
`x'
`1'
`1'
`x'
`1'
`1'
`1'
`1'
`1'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`x'
`x'
`x'
`x'
`1'
`1'
`x'
`1'
`1'
`1'
`1'
`1'
`0'
`0'
`1'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
`0'
t
RST-SDI,00
t
RST-SDO,11
t
SDI-SDO,00
t
RST-10
= k * t
CYC,SCK
t
COREINIT
0
1
0
1
0
1
0
1
0
1
t
RST-SCK
Preliminary Data Sheet E0643E30 (Ver. 3.0)
47
EDX5116ABSE
previously been sampled one). This interval (measured in
t
CYC,SCK
units) will be equal to the index [k] of the XDR
DRAM device along the serial interface bus. In this example, k
is equal to 4.
This is because each XDR DRAM device will drive its SDO
output zero around the SCK edge a time t
SDI-SDO,00
after its
SDI input is sampled zero.
In other words, the XDR DRAM[0] device will see RST and
SDI both sampled zero on the same edge S
12
(t
RST-SDI,00
will
be 0*t
CYC,SCK
units), and will drive its SDO to zero around the
subsequent edge (S
13
).
The XDR DRAM[1] device will see SDI sampled zero on edge
S
13
(t
RST-SDI,00
will be 1*t
CYC,SCK
units), and will drive its
SDO to zero around the subsequent edge (S
14
).
The XDR DRAM[2] device will see SDI sampled zero on edge
S
14
(t
RST-SDI,00
will be 2*t
CYC,SCK
units), and will drive its
SDO to zero around the subsequent edge (S
15
).
This continues until the last XDR DRAM device drives the
SRD input of the controller. Each XDR DRAM device con-
tains a state machine which measures the interval t
RST-SDI,00
between the edges in which RST and SDI are both sampled
zero, and uses this value to set the SID[5:0] field of the SID
(Serial Identification) register. This value allows directed read
and write transactions to be made to the individual XDR
DRAM devices. Table 9 summarizes the range of the timing
parameters used for initialization by the serial interface bus.
XDR DRAM Initialization Overview
[1] Apply voltage toVDD, VTERM, and VREF pins. VTERM
and VREF voltages must be less or equal to VDD voltage at all
times. Wait a time interval t
COREINIT
.
[2] Assert RST, SCK, SDI, and CMD to logical zero. Then:
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR
DRAM into low-power state (identical to power-on reset).
- Perform remaining initialization sequence in Figure 38.
[3] XDR DRAM has valid Serial ID and all registers have
default values that are defined in Figure 17 through Figure 33.
[4] Perform broadcast or directed register writes to adjust regis-
ters which need a value different from their default value.
[5] Perform Powerdown Exit sequence shown in Figure 36.
This includes the activity from SCK cycle S
0
through the final
REFP command.
[6] Perform termination/current calibration. The CALZ/
CALE sequence shown in Figure 35 is issued 128 times, then
the CALC/CALE sequence is issued 128 times. After this, each
sequence is issued once every t
CALZ
or t
CALC
interval.
[7] Condition the XDR DRAM banks by performing a REFA/
REFI activate and REFP precharge operation to each bank
eight times. This can be interleaved to save time. The row
address for the activate operation will step through eight suc-
cessive values of the REFr registers. The sequence between
cycles T
0
and T
32
in the Interleaved Refresh Example in
Figure 34 could be performed eight times to satisfy this condi-
tioning requirement.
Table 9
Initialization Timing Parameters
Symbol Parameter
Minimum
Maximum
Units
Figure(s)
t
RST,10
Number of cycles between RST being sampled one and RST being
sampled zero.
2
-
t
CYC,SCK
-
t
RST-SDO,11
Number of cycles between RST being sampled one and SDO being
driven to one.
1
1
t
CYC,SCK
-
t
RST-SDI,00
Number of cycles between RST being sampled zero (after being sam-
pled one for t
RST,10,MIN
or more cycles) and SDI being sampled zero.
This will be equal to the index [k] of the XDR DRAM device along
the serial interface bus.
0
63
t
CYC,SCK
-
t
SDI-SDO,00
Number of cycles between SDI being sampled one (after RST has
been sampled one for t
RST,10,MIN
or more cycles and is then sampled
zero) and SDO being driven to one.
1
1
t
CYC,SCK
-
t
RST-SCK
The number of SCK falling edges after the first SCK falling edge in
which RST is sampled one.
20
-
t
CYC,SCK
-
Preliminary Data Sheet E0643E30 (Ver. 3.0)
48
EDX5116ABSE
XDR DRAM Pattern Load with WDSL Reg
The XDR memory system requires a method of deterministi-
cally loading pattern data to XDR DRAMs before beginning
Receive Timing Calibration (RX TCAL). The method
employed by the XDR DRAMs to achieve this is called Write
Data Serial Load (WDSL). A WDSL packet sends one-byte of
serial data which is serially shifted into a holding register within
the XDR DRAM. Initialization software sends a sequence of
WDSL packets, each of which shifts the new byte in and
advances the shifter by 8 positions. In this way, XDR DRAMs
of varying widths can be loaded with a single command type.
Each sequence of WDSL packets will load one full column of
data to the internal holding register of the target XDR DRAM.
Depending upon the ratio of native device width to pro-
grammed width, there may be more than one sub-column per
column. After loading a full column, a series of WR com-
mands will be issued to sequentially transfer each sub-column
of the column to the XDR DRAM core(s), based upon the
SC[3:0] bits.
.
Table 10
XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4 XDR DRAM , BL=16)
DQ Pins Used
Core Word
WDSL Core Word
Load Order
x16
x8
x4
x4
x8
x16
WD[n][15:0]
SC[3:2]
=xx
SC[3:2]
= 0x
SC[3:2]
= 1x
SC[3:2]
= 00
SC[3:2]
= 01
SC[3:2]
= 10
SC[3:2]
= 11
LOGICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
DQ0
DQ0
DQ0
WD[0][15:0]
WDSL Word 8
1
1
0
1
0
0
0
DQ1
DQ1
DQ1
WD[1][15:0]
WDSL Word 7
1
1
0
1
0
0
0
DQ2
DQ2
DQ2
WD[2][15:0]
WDSL Word 12
1
1
0
1
0
0
0
DQ3
DQ3
DQ3
WD[3][15:0]
WDSL Word 3
1
1
0
1
0
0
0
DQ0
DQ4
DQ4
WD[4][15:0]
WDSL Word 10
1
1
0
0
1
0
0
DQ1
DQ5
DQ5
WD[5][15:0]
WDSL Word 5
1
1
0
0
1
0
0
DQ2
DQ6
DQ6
WD[6][15:0]
WDSL Word 14
1
1
0
0
1
0
0
DQ3
DQ7
DQ7
WD[7][15:0]
WDSL Word 1
1
1
0
0
1
0
0
DQ0
DQ0
DQ8
WD[8][15:0]
WDSL Word 9
1
0
1
0
0
1
0
DQ1
DQ1
DQ9
WD[9][15:0]
WDSL Word 6
1
0
1
0
0
1
0
DQ2
DQ2
DQ10 WD[10][15:0]
WDSL Word 13
1
0
1
0
0
1
0
DQ3
DQ3
DQ11 WD[11][15:0]
WDSL Word 2
1
0
1
0
0
1
0
DQ0
DQ4
DQ12 WD[12][15:0]
WDSL Word 11
1
0
1
0
0
0
1
DQ1
DQ5
DQ13 WD[13][15:0]
WDSL Word 4
1
0
1
0
0
0
1
DQ2
DQ6
DQ14 WD[14][15:0]
WDSL Word 15
1
0
1
0
0
0
1
DQ3
DQ7
DQ15 WD[15][15:0]
WDSL Word 0
1
0
1
0
0
0
1
PHYSICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
DQ2
DQ6
DQ14 WD[14][15:0]
WDSL Word 15
1
0
1
0
0
0
1
DQ6
WD[6][15:0]
WDSL Word 14
1
1
0
0
1
0
0
DQ2
DQ10 WD[10][15:0]
WDSL Word 13
1
0
1
0
0
1
0
DQ2
WD[2][15:0]
WDSL Word 12
1
1
0
1
0
0
0
DQ0
DQ4
DQ12 WD[12][15:0]
WDSL Word 11
1
0
1
0
0
0
1
DQ4
WD[4][15:0]
WDSL Word 10
1
1
0
0
1
0
0
DQ0
DQ8
WD[8][15:0]
WDSL Word 9
1
0
1
0
0
1
0
DQ0
WD[0][15:0]
WDSL Word 8
1
1
0
1
0
0
0
Preliminary Data Sheet E0643E30 (Ver. 3.0)
49
EDX5116ABSE
.
DQ1
DQ1
DQ1
WD[1][15:0]
WDSL Word 7
1
1
0
1
0
0
0
DQ9
WD[9][15:0]
WDSL Word 6
1
0
1
0
0
1
0
DQ5
DQ5
WD[5][15:0]
WDSL Word 5
1
1
0
0
1
0
0
DQ13 WD[13][15:0]
WDSL Word 4
1
0
1
0
0
0
1
DQ3
DQ3
DQ3
WD[3][15:0]
WDSL Word 3
1
1
0
1
0
0
0
DQ11 WD[11][15:0]
WDSL Word 2
1
0
1
0
0
1
0
DQ7
DQ7
WD[7][15:0]
WDSL Word 1
1
1
0
0
1
0
0
DQ15 WD[15][15:0]
WDSL Word 0
1
0
1
0
0
0
1
Table 10
XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4 XDR DRAM , BL=16)
DQ Pins Used
Core Word
WDSL Core Word
Load Order
x16
x8
x4
x4
x8
x16
WD[n][15:0]
SC[3:2]
=xx
SC[3:2]
= 0x
SC[3:2]
= 1x
SC[3:2]
= 00
SC[3:2]
= 01
SC[3:2]
= 10
SC[3:2]
= 11
Table 11
Core Data Word-to-WDSL Format
a
DQ Serialization Order
CFM/PCLK Cycle
Cycle 0
Cycle 1
Symbol (Bit) Time
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Bit Transmitted on DQ pins
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
WDSL Byte/Bit Transfer Order
Core Word
Core Word WD[n][15:0]
WDSL Byte Order
WDSL Byte 0
WDSL Byte 1
SWD Field of Serial Packet
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit Transmitted on CMD pin
D15
D11
D7
D3
D14
D10
D6
D2
D13
D9
D5
D1
D12
D8
D4
D0
a. Applies for first generation x16/x8/x4 XDR DRAM with BL=16.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
50
EDX5116ABSE
Special Feature Description
Dynamic Width Control
This XDR DRAM device includes a feature called dynamic
width control. This permits the device to be configured so that
read and write data can be accessed through differing widths of
DQ pins. Figure 39 shows a diagram of the logic in the path of
the read data (Q) and write data (D) that accomplishes this.
The read path is on the right of the figure. There are 16 sets of
S signals (the internal data bus connecting to the sense amps of
the memory core), with 16 signals in each set. When the XDR
DRAM device is configured for maximum width operation
(using the WIDTH[2:0] field in the CFG register), each set of
16 S signals goes to one of the 16 DQ pins (via the
Q[15:0][15:0] read bus) and are driven out in the 16 time slots
for a read data packet.
When the XDR DRAM device is configured for a width that
is less than the maximum, some of the DQ pins are used and
the rest are not used. The SC[3:0] field of the COL request
packets select which S[15:0][15:0] signals are passed to the
Q[15:0][15:0] read bus and driven as read data.
Figure 40 shows the mapping from the S bus to the Q bus as a
function of the WIDTH[2:0] register field and the SC[3:0] field
of the COL request packet. There is a separate table for each
valid value of WIDTH[2:0]. In each table, there is an entry in
the left column for each valid value of SC[3:0]. This field
should be treated as an extension of the C[9:4] column address
field. The right hand column shows which set of S[15:0][15:0]
signals are mapped to the Q read data bus for a particular value
of SC[3:0].
For example, assume that the WIDTH[2:0] value is "010", indi-
cating a device width of x4. Looking at the appropriate table in
Figure 40, it may be seen that in the SC[3:0] field, the SC[1:0]
sub-column address bits are not used. The remaining SC[3:0]
address bit(s) selects one of the 64-bit blocks of S bus signals,
causing them to be driven onto the Q[3:0][15:0] read data bus,
which in turn is driven to the DQ3..0/DQN3..0 data pins. The
Q[15:4][15:0] signals and DQ15..4/DQN15..4 data pins are
not used for a device width of x4.
The write path is shown on the left side of Figure 39. As
before, there are 16 sets of S signals (the internal data bus con-
necting to the sense amps of the memory core), with 16 signals
in each set. When the XDR DRAM device is configured for
maximum width operation (using the WIDTH[2:0] field in the
CFG register), each set of 16 S signals is driven from one of the
16 DQ pins (via the D[15:0][15:0] write bus) from each of the
16 time slots for a write data packet.
Figure 40 also shows the mapping from the D bus to the S bus
as a function of the WIDTH[2:0] register field and the SC[3:0]
field of the COL request packet. There is a separate table for
each valid value of WIDTH[2:0]. In each table, there is an entry
in the left column for each valid value of SC[3:0]. This field
should be treated as an extension of the C[9:4] column address
field. The right hand column shows which set of S[15:0][15:0]
signals are mapped from the D read data bus for a particular
value of SC[3:0].
Figure 39
Multiplexers for Dynamic Width Control
Dynamic Width Demux (WR)
16x16
16x16
Dynamic Width Mux (RD)
16x16
S[15:0][15:0]
16x16
D[15:0][15:0]
WIDTH[2:0]
SC[3:0]
WIDTH[2:0]
SC[3:0]
4+3
4+3
Q[15:0][15:0]
Byte Mask (WR)
D1[15:0][15:0]
16x16
M[7:0]
8
Preliminary Data Sheet E0643E30 (Ver. 3.0)
51
EDX5116ABSE
The block diagram in Figure 39 indicates that the Dynamic
Width logic is positioned after the serial-to-parallel conversion
(demux block) in the data receiver block and before the paral-
lel-to-serial conversion (mux block) in the data transmitter
block (see also the block diagram in Figure 2). The block dia-
gram is shown in this manner so the functionality of the logic
can be made as clear as possible. Some implementations may
place this logic in the data receiver and transmitter blocks, per-
forming the mapping in Figure 40 on the serial data rather than
the parallel data. However, this design choice will not affect the
functionality of the Dynamic Width logic; it is strictly an imple-
mentation decision.
Figure 40
D-to-S and S-to-Q Mapping for Dynamic Width Control
A8
WIDTH[2:0]=000 (x1 device width)
000
S[0][15:0]
001
S[1][15:0]
010
S[2][15:0]
011
S[3][15:0]
100
S[4][15:0]
101
S[5][15:0]
110
S[6][15:0]
111
S[7][15:0]
SC[2:0]
D[0][15:0]
Q[0][15:0]
WIDTH[2:0]=001 (x2 device width)
00x
S[4,0][15:0]
01x
S[5,1][15:0]
10x
S[6,2][15:0]
11x
S[7,3][15:0]
SC[2:0]
D[1:0][15:0]
Q[1:0][15:0]
WIDTH[2:0]=010 (x4 device width)
0xx
S[6,2,4,0][15:0]
1xx
S[7,3,5,1][15:0]
SC[2:0]
D[3:0][15:0]
Q[3:0][15:0]
WIDTH[2:0]=011 (x8 device width)
xxx
S[7:0][15:0]
SC[2:0]
D[7:0][15:0]
Q[7:0][15:0]
WIDTH[2:0]=000 (x1 device width)
0000
S[0][15:0]
0001
S[1][15:0]
0010
S[2][15:0]
0011
S[3][15:0]
0100
S[4][15:0]
0101
S[5][15:0]
0110
S[6][15:0]
0111
S[7][15:0]
1000
S[8][15:0]
1001
S[9][15:0]
1010
S[10][15:0]
1011
S[11][15:0]
1100
S[12][15:0]
1101
S[13][15:0]
1110
S[14][15:0]
1111
S[15][15:0]
SC[3:0]
D[0][15:0]
Q[0][15:0]
A16
WIDTH[2:0]=001 (x2 device width)
000x
S[1:0][15:0]
001x
S[3:2][15:0]
010x
S[5:4][15:0]
011x
S[7:6][15:0]
100x
S[9:8][15:0]
101x
S[11:10][15:0]
110x
S[13:12][15:0]
111x
S[15:14][15:0]
SC[3:0]
D[1:0][15:0]
Q[1:0][15:0]
WIDTH[2:0]=010 (x4 device width)
00xx
S[3:0][15:0]
01xx
S[7:4][15:0]
10xx
S[11:8][15:0]
11xx
S[15:12][15:0]
SC[3:0]
D[3:0][15:0]
Q[3:0][15:0]
WIDTH[2:0]=011 (x8 device width)
0xxx
S[7:0][15:0]
1xxx
S[15:8][15:0]
SC[3:0]
D[7:0][15:0]
Q[7:0][15:0]
WIDTH[2:0]=100 (x16 device width)
xxxx
S[15:0][15:0]
SC[3:0]
D[15:0][15:0]
Q[15:0][15:0]
a
a
a) EDX5116ABSE does not support
1 and
2 device width.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
52
EDX5116ABSE
Write Masking
Figure 41 shows the logic used by the XDR DRAM device
when a write-masked command (WRM) is specified in a
COLM packet. This masking logic permits individual bytes of a
write data packet to be written or not written according to the
value of an eight bit write mask M[7:0].
In Figure 41, there are 16 sets of 16 bit signals forming the
D1[15:0][15:0] input bus for the Byte Mask block. These are
treated as 2x16 8-bit bytes:
D1[15][15:8]
D1[15][7:0]
...
D1[1][15:8]
D1[1][7:0]
D1[0][15:8]
D1[0][7:0]
The eight bits of each byte is compared to the value in the byte
mask field (M[7:0]). If they are not equal (NE), then the corre-
sponding write enable signal (WE) is asserted and the byte is
written into the sense amplifier. If they are equal, then the cor-
responding write enable signal (WE) is deasserted and the byte
is not written into the sense amplifier.
In the example of Figure 41, a WRM command performs a
masked write of a 64 byte data packet to all the memory
devices connected to the RQ bus (and receiving the com-
mand). It is the job of the memory controller to search the 64
bytes to find an eight bit data value that is not used and place it
into the M[7:0] field. This will always be possible because there
are 256 possible 8-bit values and there are only 64 possible val-
ues used in the bytes in the data packet.
Figure 41
Byte Mask Logic
Note that other systems might use a data transfer size that is
different than the 64 bytes per t
CC
interval per RQ bus that is
used in the example in Figure 41.
Figure 42 shows the timing of two successive WRM com-
mands in COLM packets. The timing is identical to that of two
successive WR commands in COL packets. The one difference
Byte Mask (WR)
S[0][7:0]
8
D1[0][7:0]
8
M[7:0]
Compare
NE
Dynamic Width Demux (WR)
16x16
16x16
Dynamic Width Mux (RD)
16x16
S[15:0][15:0]
16x16
D[15:0][15:0]
WIDTH[2:0]
SC[3:0]
WIDTH[2:0]
SC[3:0]
4+3
4+3
Q[15:0][15:0]
D1[15:0][15:0]
16x16
M[7:0]
8
1
8
8
D1[0][7:0]
8
S[0][15:8]
8
D1[0][15:8]
8
Compare
NE
1
8
8
D1[0][15:8]
8
8
8
Compare
NE
1
8
8
D1[15][7:0]
8
8
8
Compare
NE
1
8
8
D1[15][15:8]
8
S[15][15:8]
WE-MSB
[15]
S[15][7:0]
D1[15][15:8]
D1[15][7:0]
WE-LSB
[15]
WE-MSB
[0]
WE-LSB
[0]
Preliminary Data Sheet E0643E30 (Ver. 3.0)
53
EDX5116ABSE
is that the COLM packet includes a M[7:0] field that indicates
the reserved bit pattern (for the eight bits of each byte) that
indicates that the byte is not to be written. This requires that
the alignment of bytes within the data packet be defined, and
also that the bit numbering within each byte be defined (note
that this was not necessary for the unmasked WR command).
In the figure, bytes are contained within a single DQ/DQN
pin pair
--
this is necessary so the dynamic width feature can be
supported. Thus, each pin pair carries two bytes of each data
packet. Byte[0] is transferred earlier than byte[1], and bit [0] of
each byte (corresponding to M[0]) is transferred first, followed
by the remaining bits in succession).
Figure 42
Write-Masked (WRM) Transaction Example
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CC
t
CWD
t
CYCLE
a1
WRM
a2
WRM
D(a2)
D(a1)
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14] [15]
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14] [15]
DQ0
DQN0
DQ15
DQN15
...
...
t
CAC
a1
RD
Q(a1)
Byte [0]
Bit- and Byte-number-
ing convention for write
and read data packets.
Byte [15]
Byte [16+15]
[1]
[0]
[2]
[4]
[3]
[5]
[7]
[6]
[8]
[10]
[9]
[11]
[13]
[12]
[14] [15]
DQ1
DQN1
Byte [1]
Byte [16+0]
Byte [16+1]
Preliminary Data Sheet E0643E30 (Ver. 3.0)
54
EDX5116ABSE
Multiple Bank Sets and the ERAW Feature
Figure 45 shows a block diagram of a XDR DRAM in which
the banks are divided into two sets (called the even bank set
and the odd bank set) according to the least-significant bit of
the bank address field. This XDR DRAM supports a feature
called "Early Read After Write" (hereafter called "ERAW").
The logic that accepts commands on the RQ11..0 signals is
capable of operating these two bank sets independently. In
addition, each bank set connects to its own internal "S" data
bus (called S0 and S1). The receive interface is able to drive
write data onto either of these internal data buses, and the
transmit interface is able to sample read data from either of
these internal data buses. These capabilities will permit the
delay between a write column operation and a read column
operation to be reduced, thereby improving performance.
Figure 43 shows the timing previously presented in Figure 12,
but with the activity on the internal S data bus included. The
write-to-read parameter t
WR
ensures that there is adequate
turnaround time on the S bus between D(a2) and Q(c1).
When ERAW is supported with odd and even bank sets, the
t
WR,MIN
parameter must be obeyed when the write and read
column operations are to the same bank set, but a second
parameter t
WR-D
permits earlier column operations to the
opposite bank set. Figure 44 shows how this is possible
because there are two internal data buses S0 and S1. In this
example, the four column read operations are made to the
same bank Bb, but they could use different banks as long as
they all belonged to the bank set that was different from the
bank set containing Ba (for the column write operations).
Figure 43
Write/Read Interaction -- No ERAW Feature
Figure 44
Write/Read Interaction -- ERAW Feature
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
Transaction a: WR
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
Transaction c: RD
c1 = {Bc,Cc1}
c2 = {Bc,Cc2}
c2
RD
t
CWD
Q(c2)
Q(c1)
t
CAC
a1
WR
D(a2)
D(a1)
t
CYCLE
c1
RD
a2
WR
t
WR
DQ15..0
DQN15..0
t
CC
t
WR-BUB,XDRDRAM
S[15:0]
[15:0]
t
CC
D(a1)
D(a2)
Q(c1)
Q(c2)
turnaround
T
0
T
1
T
2
T
3
CFM
RQ11..0
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
CFMN
Transaction a: WR
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
Transaction b: RD
b1 = {Bb,Cb1}
b2 = {Bb,Cb2}
b3 = {Bb,Cb3}
c1
RD
t
CWD
Q(c1)
Q(b4)
t
CAC
a1
WR
D(a2)
D(a1)
t
CYCLE
b4
RD
a2
WR
t
WR-D
DQ15..0
DQN15..0
t
CC
S0[15:0]
[15:0]
t
CC
D(a1)
D(a2)
Q(b4)
Q(c1)
S1[15:0]
[15:0]
Q(b1)
Q(b2)
Transaction c: RD
c1 = {Bc,Cc1}
b1
RD
b3
RD
b2
RD
Q(b2)
Q(b1)
Q(b3)
Q(b3)
t
WR-BUB,XDRDRAM
turnaround
Bb is in different bank set than Ba
Bc is in same bank set as Ba
Bank Restrictions
b4 = {Bb,Cb4}
Preliminary Data Sheet E0643E30 (Ver. 3.0)
55
EDX5116ABSE
Figure 45
XDR DRAM Block Diagram with Bank Sets
1
1:2 Demux
Reg
12
RQ11..0
1:16 Demux
16:1 Mux
16/t
CC
Bank 0
ACT
...
Bank 0
1
ACT
ACT
ROW
1
1
PRE
PRE
PRE
ROW
Sense Amp 0
...
1
1
R/W
R/W
COL
COL
COL
...
...
...
Bank Array
Sense Amp Array
...
Dynamic Width Demux (WR)
DQ15..0
DQN15..0
16
16
16
16
16/t
CC
16x16*2
6
16x16
16x16
16x16
16x16
3
3
3
6
12
(2
3
-2)
Bank
(2
3
-2)
Sense Amp
6
16x16*2
6
12
16x16*2
6
*2
12
16
D[15:0][15:0]
S0[15:0][15:0]
16
16x16
16x16
16x16*2
6
Q[15:0][15:0]
Dynamic Width Mux (RD)
Byte Mask (WR)
12
6
...
...
1
Bank 0
...
Bank 1
1
ACT
ACT
ROW
1
1
PRE
PRE
ROW
Sense Amp 1
1
1
R/W
R/W
COL
COL
...
...
...
Bank Array
Sense Amp Array
16x16*2
6
16x16
16x16
(2
3
-1)
Bank
(2
3
-1)
Sense Amp
6
16x16*2
6
12
16x16*2
6
*2
12
S1[15:0][15:0]
16x16*2
6
12
6
Odd
Even
ACT logic
PRE logic
COL logic
decode
decode
decode
...
...
...
...
...
...
WR even
WR odd
RD odd
RD even
...
...
...
...
Preliminary Data Sheet E0643E30 (Ver. 3.0)
56
EDX5116ABSE
Simultaneous Activation
When the XDR DRAM supports multiple bank sets as in
Figure 45, another feature may be supported, in addition to
ERAW. This feature is simultaneous activation, and the timing
of several cases is shown in Figure 46.
The t
RR
parameter specifies the minimum spacing between
packets with activation commands in XDR DRAMs with a sin-
gle bank set, or between packets to the same bank set in a XDR
DRAM with multiple bank sets. The t
RR-D
parameter specifies
the minimum spacing between packets with activation com-
mands to different bank sets in a XDR DRAM with multiple
bank sets.
In Figure 46, Case 4 shows an example when both t
RR
and t
RR-
D
must be at least 4*t
CYCLE
. In such a case, activation com-
mands to different bank sets satisfy the same constraint as acti-
vation commands to the same bank set.
In Figure 46, Case 2 shows an example when t
RR
must be at
least 4*t
CYCLE
and t
RR-D
must be at least 2*t
CYCLE
. In such a
case, an activation command to one bank set may be inserted
between two activation commands to a different bank set.
In Figure 46, Case 1 shows an example when t
RR
must be at
least 4*t
CYCLE
and t
RR-D
must be at least 1*t
CYCLE
. As in the
previous case, an activation command to one bank set may be
inserted between two activation commands to a different bank
set. In this case, the middle activation command will not be
symmetrically placed relative to the two outer activation com-
mands.
In Figure 46, Case 0 shows an example when t
RR
must be at
least 4*t
CYCLE
and t
RR-D
must be at least 0*t
CYCLE
. This
means that two activation commands may be issued on the
same CFM clock edge. This is only possible by using the delay
mechanism in one of the two commands. See "Dynamic
Request Scheduling" on page 20. In the example shown, the
packet with the REFA command is received one cycle before
the command with the ACT command, and the REFA com-
mand includes a one cycle delay. Both activation commands
will be issued internally to different bank sets on the same
CFM clock edge.
Figure 46
Simultaneous Activation -- t
RR-D
Cases
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
RR-D
ACT
REFA
ACT
t
RR-D
Case 4: t
RR-D
= 4*t
CYCLE
REFA & ACT have same t
RR
t
RR
ACT
REFA
ACT
Case 2: t
RR-D
= 2*t
CYCLE
REFA fits between two ACT
t
RR-D
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Case 1: t
RR-D
= 1*t
CYCLE
REFA fits between two ACT
t
RR
ACT
REFA
ACT
Case 0: t
RR-D
= 0*t
CYCLE
REFA simultaneous with ACT
t
RR-D
t
RR
ACT
REFA
ACT
t
RR-D
(REFA uses delay=1*t
CYCLE
)
set different from two ACT
note - REFA is directed to bank
set different from two ACT
note - REFA is directed to bank
set different from ACT at T
12
note - REFA is directed to bank
a
a
a
a) EDX5116ABSE does not support these cases.
The minimum value of t
RR-D
is 4.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
57
EDX5116ABSE
Simultaneous Precharge
When the XDR DRAM supports multiple bank sets as in
Figure 45, another feature may be supported, in addition to
ERAW and simultaneous activation. This feature is simulta-
neous precharge, and the timing of several cases is shown in
Figure 47.
The t
PP
parameter specifies the minimum spacing between
packets with precharge commands in XDR DRAMs with a sin-
gle bank set, or between packets to the same bank set in a XDR
DRAM with multiple bank sets. The t
PP-D
parameter specifies
the minimum spacing between packets with precharge com-
mands to different bank sets in a XDR DRAM with multiple
bank sets.
In Figure 46, Case 4 shows an example when both t
PP
and t
PP-
D
must be at least 4*t
CYCLE
. In such a case, precharge com-
mands to different bank sets satisfy the same constraint as pre-
charge commands to the same bank set.
In Figure 46, Case 2 shows an example when t
PP
must be at
least 4*t
CYCLE
and t
PP-D
must be at least 2*t
CYCLE
. In such a
case, a precharge command to one bank set may be inserted
between two precharge commands to a different bank set.
In Figure 46, Case 1 shows an example when t
PP
must be at
least 4*t
CYCLE
and t
PP-D
must be at least 1*t
CYCLE
. As in the
previous case, a precharge command to one bank set may be
inserted between two precharge commands to a different bank
set. In this case, the middle precharge command will not be
symmetrically placed relative to the two outer precharge com-
mands.
In Figure 46, Case 0 shows an example when t
PP
must be at
least 4*t
CYCLE
and t
PP-D
must be at least 0*t
CYCLE
. This
means that two activation commands may be issued on the
same CFM clock edge. This is possible by using the delay
mechanism in one of the two commands. See "Dynamic
Request Scheduling" on page 20. It is also possible by taking
advantage of the fact that two independent precharge com-
mands may be encoded within a single ROWP packet. In the
example shown, the ROWP packet contains both a REFA
command and a PRE command. Both precharge commands
will be issued internally to different bank sets on the same
CFM clock edge.
Figure 47
Simultaneous Precharge -- t
PP-D
Cases
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
t
PP-D
PRE
REFP
PRE
t
PP-D
Case 4: t
PP-D
= 4*t
CYCLE
REFP & PRE have same t
RR
t
PP
PRE
REFP
PRE
Case 2: t
PP-D
= 2*t
CYCLE
REFP fits between two PRE
t
PP-D
T
0
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
T
8
t
CYCLE
DQ15..0
DQN15..0
CFM
CFMN
RQ11..0
Case 1: t
PP-D
= 1*t
CYCLE
REFP fits between two PRE
t
PP
PRE
PRE
Case 0: t
PP-D
= 0*t
CYCLE
REFP simultaneous with PRE
t
PP-D
t
PP
PRE
REFP
PRE
t
PP-D
set different from two PRE
note - REFP is directed to bank
set different from two PRE
note - REFP is directed to bank
set different from PRE at T
12
note - REFP is directed to bank
REFP
a
a) EDX5116ABSE does not support case0.
The minimum value of t
PP-D
is 1.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
58
EDX5116ABSE
Operating Conditions
Electrical Conditions
Table 12 summarizes all electrical conditions (temperature and
voltage conditions) that may be applied to the memory compo-
nent. The first section of parameters is concerned with abso-
lute voltages, storage, and operating temperatures, and the
power supply, reference, and termination voltages.
The second section of parameters determines the input voltage
levels for the RSL RQ signals. The high and low voltages must
satisfy a symmetry parameter with respect to the
V
REF,RSL
.
The third section of parameters determines the input voltage
levels for the RSL SI (serial interface) signals. The high and low
voltages must satisfy a symmetry parameter with respect to the
V
REF,RSL
.
The fourth section of parameters determines the input voltage
levels for the CFM clock signals. The high and low voltages are
specified by a common-mode value and a swing value.
The fifth section of parameters determines the input voltage
levels for the write data signals on the DRSL DQ pins. The
high and low voltage are specified by a common-mode value
and a swing value.
Table 12
Electrical Conditions
Symbol Parameter
Minimum
Maximum
Unit
V
IN,ABS
Voltage applied to any pin (except VDD) with respect to GND
- 0.300
1.500
V
V
DD,ABS
Voltage on VDD with respect to GND
- 0.500
2.300
V
T
STORE
Storage temperature
- 50
100
C
T
J
Junction temperature under bias during normal operation
0
100
C
V
DD
Supply voltage applied to VDD pins during normal operation
1.800 - 0.090
1.800 + 0.090
V
V
REF,RSL
RSL - Reference voltage applied to VREF pin
a
V
TERM,RSL
- 0.450 - 0.025
V
TERM,RSL
- 0.450 + 0.025
V
V
TERM,DRSL
DRSL - Termination voltage applied to VTERM pins
1.200 - 0.060
1.200 + 0.060
V
V
IL,RQ
RSL RQ inputs -low voltage
V
REF,RSL
- 0.450
V
REF,RSL
- 0.150
V
V
IH,RQ
b
RSL RQ inputs -high voltage
V
REF,RSL
+ 0.150
V
REF,RSL
+ 0.450
V
R
A,RQ
RSL RQ inputs - data asymmetry:
R
A,RQ
= (V
IH,RQ
-V
REF,RSL
)/(V
REF,RSL
-V
IL,RQ
)
0.8
1.2
V
V
IL,SI
RSL Serial Interface inputs -low voltage
V
REF,RSL
- 0.450
V
REF,RSL
- 0.200
V
V
IH,SI
b
RSL Serial Interface inputs -high voltage
V
REF,RSL
+ 0.200
V
REF,RSL
+ 0.450
V
R
A,SI
RSL Serial Interface inputs - data asymmetry:
R
A,SI
= (V
IH,SI
-V
REF,RSL
)/(V
REF,RSL
-V
IL,SI
)
0.8
1.2
V
V
ICM,CFM
CFM/CFMN input - common mode: V
ICM,CFM
= (V
IH,CFM
b
+V
IL,CFM)
/2
V
TERM,DRSL
- 0.150
V
TERM,DRSL
- 0.075
V
V
ISW,CFM
CFM/CFMN input - high-low swing: V
ISW,CFM
= (V
IH,CFM
b
- V
IL,CFM
)
0.150
0.300
V
V
ICM,DQ
DRSL DQ inputs - common mode: V
ICM,DQ
= (V
IH,DQ
b
+V
IL,DQ)
/2
V
TERM,DRSL
-0.150
V
TERM,DRSL
-0.025
V
V
ISW,DQ
DRSL DQ inputs - high-low swing: V
ISW,DQ
= (V
IH,DQ
b
- V
IL,DQ
)
0.050
0.300
V
a. V
TERM,RSL
is typically 1.200V0.060V. It connects to the RSL termination components, not to this DRAM component.
b. V
IH
is typically equal to V
TERM,RSL
or V
TERM,DRSL
(whichever is appropriate) under DC conditions in a system.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
59
EDX5116ABSE
Timing Conditions
Table 13 summarizes all timing conditions that may be applied
to the memory component. The first section of parameters is
concerned with parameters for the clock signals. The second
section of parameters is concerned with parameters for the
request signals. The third section of parameters is concerned
with parameters for the write data signals. The fourth section
of parameters is concerned with parameters for the serial inter-
face signals. The fifth section is concerned with all other
parameters, including those for refresh, calibration, power state
transitions, and initialization.
Table 13
Timing Conditions
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
t
CYCLE
or t
CYC,CFM
CFM RSL clock - cycle time -4000
-3200
-2400
2.000
2.500
3.333
3.830
3.830
3.830
ns
ns
ns
Figure 48
t
R,CFM
, t
F,CFM
CFM/CFMN input - rise and fall time - use minimum for test.
0.080
0.200
t
CYCLE
Figure 48
t
H,CFM
, t
L,CFM
CFM/CFMN input - high and low times
40%
60%
t
CYCLE
Figure 48
t
R,RQ
, t
F,RQ
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
0.080
0.260
t
CYCLE
Figure 49
t
S,RQ
, t
H,RQ
RSL RQ input to sample points @ 2.500 ns
>
t
CYCLE
2.000 ns
(set/hold) @ 3.333 ns
>
t
CYCLE
2.500 ns
@ 3.830 ns
t
CYCLE
3.333 ns
0.170
0.200
0.275
-
-
-
ns
ns
ns
Figure 49
t
IR,DQ
, t
IF,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
0.020
0.074
t
CYCLE
Figure 50
t
S,DQ
, t
H,DQ
DRSL DQ input to sample points @ 2.500 ns
>
t
CYCLE
2.000 ns
(set/hold) @ 3.333 ns
>
t
CYCLE
2.500 ns
@ 3.830 ns
t
CYCLE
3.333 ns
0.052
0.065
0.080
-
-
-
ns
ns
ns
Figure 50
t
DOFF,DQ
DRSL DQ input delay offset (fixed) to sample points
-0.080
+0.080
t
CYCLE
Figure 50
t
CYC,SCK
Serial Interface SCK input - cycle time
20
-
ns
Figure 52
t
R,SCK,
t
F,SCK
Serial Interface SCK input - rise and fall times
-
5.0
ns
Figure 52
t
H,SCK
, t
L,SCK
Serial Interface SCK input - high and low times
40%
60%
t
CYC,SCK
Figure 52
t
IR,SI,
t
IF,SI
Serial Interface CMD,RST,SDI input - rise and fall times
-
5.0
ns
Figure 52
t
S,SI
,t
H,SI
Serial Interface CMD,SDI input to SCK clock edge - set/hold time
5
-
ns
Figure 52
t
DLY,SI-RQ
Delay from last SCK clock edge for register operation to first CFM edge with
RQ packet. Also, delay from first CFM edge with RQ packet to the first SCK
clock edge for register operation.
10
-
t
CYC,SCK
-
t
REF
Refresh interval. Every row of every bank must be accessed at least once in this
interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
-
16
ms
Figure 34
t
REFA-REFA,AVG
Average refresh command interval. ROWP-REFA or ROWP-REFI commands
must be issued at this average rate. This depends upon t
REF
and the number of
banks and rows: t
REFA-REFA,AVG
= t
REF
/(N
B
*N
R
) = t
REF
/(2
3
*2
12
).
t
REFA-REFA,AVG
= 488
ns
-
N
REFA,BURST
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands
which can be issued consecutively at the minimum command spacing.
-
128
commands
-
t
BURST-REFA
Refresh burst interval. The interval between a burst of N
REFA,BURST,MAX
ROWP-REFA or ROWP-REFI commands and the next ROWP-REFA or
ROWP-REFI command.
40
-
t
CYCLE
-
t
COREINIT
Interval needed for core initialialization after power is applied.
-
1.500
ms
-
t
CALC,
t
CALZ
Current calibration interval
-
100
ms
Figure 35
t
CMD-CALC
, t
CMD-CALZ
,
Delay between packet with any command w/ PRE or REFP command
and CALC/CALZ packet w/ any other command
4
16
-
-
t
CYCLE
Figure 35
t
CALCE
, t
CALZE
Delay between CALC/CALZ packet and CALE packet
12
-
t
CYCLE
Figure 35
Preliminary Data Sheet E0643E30 (Ver. 3.0)
60
EDX5116ABSE
Operating Characteristics
Electrical Characteristics
Table 14 summarizes all electrical parameters (temperature,
current, and voltage) that characterize this memory compo-
nent. The only exception is the supply current values (I
DD
)
under different operating conditions covered in the Supply Cur-
rent Profile section.
The first section of parameters is concerned with the thermal
characteristics of the memory component.
The second section of parameters is concerned with the cur-
rent needed by the RQ pins and VREF pin.
The third section of parameters is concerned with the current
needed by the DQ pins and voltage levels produced by the DQ
pins when driving read data. This section is also concerned
with the current needed by the VTERM pin, and with the
resistance levels produced for the internal termination compo-
nents that attach to the DQ pins.
The fourth section of parameters determines the output volt-
age levels and the current needed for the serial interface signals.
t
CALE-CMD
Delay between CALE packet and packet with any command
24
-
t
CYCLE
Figure 35
t
CMD-PDN
Last command before PDN entry
16
-
t
CYCLE
Figure 36
t
PDN-CFM
RSL CFM/CFMN and VTERM stable after PDN entry
16
-
t
CYCLE
Figure 36
t
CFM-PDN
RSL CFM/CFMN and VTERM stable before PDN exit
16
-
t
CYCLE
Figure 36
t
PDN-CMD
First command after PDN exit (includes lock time for CFM/CFMN)
4096
-
t
CYCLE
Figure 36
Table 13
Timing Conditions (Continued)
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
Table 14
Electrical Characteristics
Symbol Parameter
Minimum
Maximum
Units
JC
Junction-to-case thermal resistance
a
-
0.5
C/Watt
I
I,RSL
RSL RQ or Serial Interface input current @ (V
IN
=
V
IH,RQ,MAX
)
-10
10
A
I
REF,RSL
V
REF,RSL
current @ V
REF,RSL,MAX
flowing into VREF pin
-10
10
A
V
OSW,DQ
DRSL DQ outputs - high-low swing:
V
OSW,DQ
= (V
IH,DQ
-V
IL,DQN
) or (V
IH,DQN
-V
IL,DQ
)
0.200
0.400
V
R
TERM,DQ
DRSL DQ outputs - termination resistance
40.0
60.0
V
OL,SI
RSL serial interface SDO output - low voltage
0.0
0.250
V
V
OH,SI
RSL serial interface SDO output - high voltage
V
TERM,RSL
- 0.250
V
TERM,RSL
V
a. The package is mounted on a thermal test board which is defined JEDEC Standard JESD 51-9.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
61
EDX5116ABSE
Supply Current Profile
In this section, Table 15 summarizes the supply currents (I
DD
and I
TERM,DRSL
) that characterize this memory component.
These parameters are shown under different operating condi-
tions.
Table 15
Supply Current Profile
Symbol
Power State and Steady State Transaction
Rates
Maximum
@t
CYCLE
= 2.000 ns
@ x16/x8/x4 width
Maximum
@t
CYCLE
= 2.500 ns
@ x16/x8/x4 width
Maximum
@t
CYCLE
= 3.333 ns
@ x16/x8/x4 width
Units
I
DD,PDN
Device in PDN, self-refresh enabled.
a
TBD
25/25/25
TBD
mA
I
DD,STBY
Device in STBY. This is for a device in STBY
with no packets on the Channel
a
TBD
270/270/270
TBD
mA
I
DD,ROW
ACT command every t
RR
,
PRE command every t
PP
a
TBD
600/600/600
TBD
mA
I
DD,WR
ACT command every t
RR
,
PRE command every t
PP
,
WR command every t
CC.
a
TBD
1200/1000/900
TBD
mA
I
DD,RD
ACT command every t
RR
,
PRE command every t
PP
,
RD command every t
CC
a
TBD
1300/1200/1100
TBD
mA
I
TERM,DRSL,WR
WR command every t
CC.
b, c
TBD
150/90/60
TBD
mA
I
TERM,DRSL,RD
RD command every t
CC.
b
TBD
290/150/90
TBD
mA
a. I
DD
current @ V
DD,MAX
flowing into VDD pins
b. I
TERM,DRSL
current @ V
TERM,DQ,MAX
flowing into VTERM pins
c. Mesurement condition: DQ/DQN input swing level is 300mV.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
62
EDX5116ABSE
Timing Characteristics
Table 16 summarizes all timing parameters that characterize
this memory component. The only exceptions are the core
timing parameters that are speed-bin dependent. Refer to the
Timing Parameters section for more information.
The first section of parameters pertains to the timing of the
DQ pins when driving read data.
The second section of parameters is concerned with the tim-
ing for the serial interface signals when driving register read
data.
The third section of parameters is concerned with the time
intervals needed by the interface to transition between power
states.
Timing Parameters
Table 17 summarizes the timing parameters that characterize
the core logic of this memory component. These timing
parameters will vary as a function of the component's speed
bin. The four sections deal with the timing intervals between
packets with, respectively, row-row commands, row-column
commands, column-column commands, and column-row
commands.
Table 16
Timing Characteristics
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
t
Q,DQ
DRSL DQ output delay (variation across 16 Q bits on each DQ pin)
from drive points - output delay @ 2.500 ns
>
t
CYCLE
2.000 ns
@ 3.333 ns
>
t
CYCLE
2.500 ns
@ 3.830 ns
t
CYCLE
3.333 ns
-0.052
-0.065
-0.080
+0.052
+0.065
+0.080
ns
ns
ns
Figure 51
t
QOFF,DQ
DRSL DQ output delay offset (a fixed value for all 16 Q bits on each
DQ pin) from drive points - output delay
0.000
+0.200
t
CYCLE
Figure 51
t
OR,DQ
, t
OF,DQ
DRSL DQ output - rise and fall times (20%-80%).
0.020
0.040
t
CYCLE
Figure 51
t
Q,SI
Serial SCK-to-SDO output delay @ C
LOAD,MAX
= 15 pF
2
15
ns
Figure 53
t
P,SI
Serial SDI-to-SDO propagation delay @ C
LOAD,MAX
= 15 pF
-
15
ns
Figure 53
t
OR,SI
, t
OF,SI
Serial SDO output rise/fall (20%-80%) @ C
LOAD,MAX
= 15 pF
-
10
ns
Figure 53
t
PDN-ENTRY
Time for power state to change after PDN entry
-
16
t
CYCLE
Figure 36
t
PDN-EXIT
Time for power state to change after PDN exit
0
-
t
CYCLE
Figure 36
Table 17
Timing Parameters
Symbol
Parameter and Other Conditions
Min
(A)
Min
(B)
Min
(C)
Units
Figure(s)
t
RC
Row-cycle time: interval between successive t
RC
ROWA-ACT or ROWP-REFA or t
RC-R, 2tCC
= t
RCD-R
+ t
CC
+ t
RDP
+ t
RP
a
ROWP-REFI activate commands to the t
RC-W, 2tCC, noERAW
= t
RCD-W
+ t
CC
+ t
WRP
+ t
RP
a
same bank. t
RC-W, 2tCC, ERAW
= t
RCD-W
+ t
CC
+ t
WRP
+ t
RP
a
16
16
19
23
20
20
24
28
24
24
24
28
t
CYCLE
Figure 4 -
Figure 7
t
RAS
Row-asserted time: interval between a ROWA-ACT or ROWP-REFA or ROWP-REFI activate
command and a ROWP-PRE or ROWP-REFP precharge command to the same bank.
Note that t
RAS,MAX
is 64 us for all timing bins.
10
13
17
t
CYCLE
Figure 4 -
Figure 7
t
RP
Row-precharge time: interval between a ROWP-PRE or ROWP-REFP precharge command
and a ROWA-ACT or ROWP-REFA or ROWP-REFI activate command to the same bank.
6
7
7
t
CYCLE
Figure 4 -
Figure 7
t
PP
Precharge-to-precharge time: interval between successive ROWP- t
PP
PRE or ROWP-REFP precharge commands to different banks. t
PP-D
b
4
1
4
1
4
1
t
CYCLE
Figure 4 -
Figure 7
t
RR
Row-to-row time: interval between ROWA-ACT or ROWP- t
RR
REFA or ROWP-REFI activate commands to different banks. t
RR-D
c
4
4
4
4
4
4
t
CYCLE
Figure 4 -
Figure 7
Preliminary Data Sheet E0643E30 (Ver. 3.0)
63
EDX5116ABSE
t
RCD-R
Row-to-column-read delay: interval between a ROWA-ACT activate command and a COL-RD
read command to the same bank.
5
7
7
t
CYCLE
Figure 4 -
Figure 7
t
RCD-W
Row-to-column-write delay: interval between a ROWA-ACT activate command and a COL-
WR or COL-WRM write command to the same bank.
1
3
3
t
CYCLE
Figure 4 -
Figure 7
t
CAC
Column access delay: interval from COL-RD read command to Q read data
6
7
7
t
CYCLE
Figure 10
t
CWD
Column write delay: interval from a COL-WR or COLM-WRM write command to D write
data.
3
3
3
t
CYCLE
Figure 9
t
CC
Column-to-column time: interval between successive COL-RD commands, or between succes-
sive COL-WR or COLM-WRM commands.
2
2
2
t
CYCLE
Figure 4 -
Figure 7
t
RW-BUB,
XDRDRAM
Read-to-write bubble time: interval between the end of a Q read data packet and the start of D
write data packet (the end of a data packet is the time interval t
CC
after its start).
3
3
3
t
CYCLE
Figure 13
t
WR-BUB,
XDRDRAM
Write-to-read bubble time: interval between the end of a D writed data and the start of Q read
data packet (the end of a data packet is the time interval t
CC
after its start).
3
3
3
t
CYCLE
Figure 13
t
RW
Read-to-write time: interval between a COL-RD read command and a COL-WR or COLM-
WRM write command.
d
8
9
9
t
CYCLE
Figure 12
t
WR
Write-to-read time: interval between a COL-WR or t
WR
COLM-WRM write command and a COL-RD read command. t
WR-D
e
9
2
10
2
10
2
t
CYCLE
Figure 12
t
RDP
Read-to-precharge time: interval between a COL-RD read command and a ROWP-PRE pre-
charge command to the same bank.
3
4
4
t
CYCLE
Figure 4 -
Figure 7
t
WRP
Write-to-precharge time: interval between a COL-WR or COLM-WRM write command and a
ROWP-PRE precharge command to the same bank.
10
12
12
t
CYCLE
Figure 4 -
Figure 7
t
DR
Write data-to-read time: interval between the start of D write data and a COL-RD read com-
mand to the same bank.
6
7
7
t
CYCLE
Figure 12
t
DP
Write data-to-precharge time: interval between D write data and ROWP-PRE precharge com-
mand to the same bank.
7
9
9
t
CYCLE
Figure 9
t
LRRn-LRRn
Interval between ROWP-LRRn command and a subsequent ROWP-LRRn command.
f
16
20
24
t
CYCLE
Table 4
t
REFx-LRRn
Interval between ROWP-REFx command and a subsequent ROWP-LRRn command.
16
20
24
t
CYCLE
Table 4
t
LRRn-REFx
Interval between ROWP-LRRn command and a subsequent ROWP-REFx command.
16
20
24
t
CYCLE
Table 4
a. The t
RC,MIN
parameter is applicable to all transaction types (read, write, refresh, etc.). Read and write transactions may have an additional limitation, depending upon how many
column accesses (each requiring t
CC
) are performed in each row access (t
RC
). The table lists the special cases (t
RC-R, 2tCC
, t
RC-W, 2tCC, noERAW
, t
RC-W, 2tCC, ERAW
) in which two col-
umn accesses are performed in each row access. Note that t
RC-W, 2tCC, ERAW
uses a relaxed value of t
RCD-W
that is equal to t
RCD-R,MIN
.
All other parameters are minimum.
b. t
PP-D
is the t
PP
parameter for precharges to different bank sets. See "Simultaneous Precharge" on page 57.
c. t
RR-D
is the t
RR
parameter for activates to different bank sets. See "Simultaneous Activation" on page 56.
d. See "Propagation Delay" on page 28.
e. t
WR-D
is the t
WR
parameter for write-read accesses to different bank sets. See "Multiple Bank Sets and the ERAW Feature" on page 54. Also, note that the value of t
WR-D
may
not take on the values {3,5,7} within the range{t
WR-D,MIN
, ... t
WR,MIN
-1}. t
WR-D
may assume any value
t
WR,MIN
.
f. ROWP-LRRn includes the commands {ROWP-LRR0,ROWP-LRR1,ROWP-LRR2}
ROWP-REFx includes the commands {ROWP-REFA,ROWP-REFI,ROWP-REFP}
Table 17
Timing Parameters (Continued)
Symbol
Parameter and Other Conditions
Min
(A)
Min
(B)
Min
(C)
Units
Figure(s)
Preliminary Data Sheet E0643E30 (Ver. 3.0)
64
EDX5116ABSE
Receive/Transmit Timing
Clocking
Figure 48 shows a timing diagram for the CFM/CFMN clock
pins of the memory component. This diagram represents a
magnified view of these pins. This diagram shows only one
clock cycle.
CFM and CFMN are differential signals: one signal is the com-
plement of the other. They are also high-true signals -- a low
voltage represents a logical zero and a high voltage represents a
logical one. There are two crossing points in each clock cycle.
The primary crossing point includes the high-voltage-to-low-
voltage transition of CFM (indicated with the arrowhead in the
diagram). The secondary crossing point includes the low-volt-
age-to-high-voltage transition of CFM. All timing events on
the RSL signals are referenced to the first set of edges.
Timing events are measured to and from the crossing point of
the CFM and CFMN signals. In the timing diagram, this is how
the clock-cycle time (t
CYCLE
or t
CYC,CFM
), clock-low time
(t
L,CFM
) and clock-high time (t
H,CFM
) are measured.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise
(t
R,CFM
) and fall time (t
F,CFM
) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = V
IL,CFM
+ 0.2*(V
IH,CFM
-V
IL,CFM
)
80% = V
IL,CFM
+ 0.8*(V
IH,CFM
-V
IL,CFM
)
Figure 48
Clocking Waveforms
CFM
CFMN
t
CYCLE
or t
CYC,CFM
t
R,CFM
80%
20%
V
IH,CFM
V
IL,CFM
logic 0
logic 1
t
L,CFM
t
H,CFM
t
F,CFM
Preliminary Data Sheet E0643E30 (Ver. 3.0)
65
EDX5116ABSE
RSL RQ Receive Timing
Figure 49 shows a timing diagram for the RQ11..0 request pins
of the memory component. This diagram represents a magni-
fied view of the pins and only a few clock cycles (CFM and
CFMN are the clock signals). Timing events are measured to
and from the primary CFM/CFMN crossing point in which
CFM makes its high-voltage-to-low-voltage transition. The
RQ11..0 signals are low-true: a high voltage represents a logical
zero and a low voltage represents a logical one. Timing events
on the RQ11..0 pins are measured to and from the point that
the signal reaches the level of the reference voltage V
REF,RSL
.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise (t
R,RQ
)
and fall time (t
F,RQ
) of the signals are measured from the 20%
and 80% points of the full-swing levels.
20% = V
IL,RQ
+ 0.2*(V
IH,RQ
-V
IL,RQ
)
80% = V
IL,RQ
+ 0.8*(V
IH,RQ
-V
IL,RQ
)
There are two data receiving windows defined for each
RQ11..0 signal. The first of these (labeled "0") has a set time,
t
S,RQ
, and a hold time, t
H,RQ
, measured around the primary
CFM/CFMN crossing point. The second (labeled "1") has a
set time (t
S,RQ
) and a hold time (t
H,RQ
) measured around a
point 0.5*t
CYCLE
after the primary CFM/CFMN crossing
point.
Figure 49
RSL RQ Receive Waveforms
t
S,RQ
CFM
CFMN
RQ0
t
H,RQ
t
CYCLE
RQ11
...
80%
20%
t
R,RQ
V
IH,RQ
V
IL,RQ
logic1
logic 0
V
REF,RSL
[1/2]t
CYCLE
0
1
t
S,RQ
t
H,RQ
t
F,RQ
t
S,RQ
t
H,RQ
80%
20%
t
R,RQ
V
IH,RQ
V
IL,RQ
logic 1
logic 0
V
REF,RSL
[1/2]t
CYCLE
0
1
t
S,RQ
t
H,RQ
t
F,RQ
Preliminary Data Sheet E0643E30 (Ver. 3.0)
66
EDX5116ABSE
DRSL DQ Receive Timing
Figure 50 shows a timing diagram for receiving write data on
the DQ/DQN data pins of the memory component. This dia-
gram represents a magnified view of the pins and shows only a
few clock cycles are shown (CFM and CFMN are the clock sig-
nals). Timing events are measured to and from the primary
CFM/CFMN crossing point in which CFM makes its high-
voltage-to-low-voltage transition. The DQ15..0/DQN15..0
signals are high-true: a low voltage represents a logical zero and
a high voltage represents a logical one. They are also differen-
tial -- timing events on the DQ15..0/DQN15..0 pins are mea-
sured to and from the point that each differential pair crosses.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise time
(t
IR,DQ
) and fall time (t
IF,DQ
) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = V
IL,DQ
+ 0.2*(V
IH,DQ
-V
IL,DQ
)
80% = V
IL,DQ
+ 0.8*(V
IH,DQ
-V
IL,DQ
)
There are 16 data receiving windows defined for each
DQ15..0/DQN15..0 pin pair. The receiving windows for a
particular DQi/DQNi pin pair is referenced to an offset
parameter t
DOFF,DQi
(the index "i" may take on the values {0,
1, ..15} and refers to each of the DQ15..0/DQN15..0 pin
pairs).
The t
DOFF,DQi
parameter determines the time between the pri-
mary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair. The 16 receiving windows are placed at
times t
DOFF,DQi
+(j/8)*t
CYCLE
(the index "j" may take on the
values {0,1, 2, ..15} and refers to each of the receiving win-
dows for the DQi/DQNi pin pair).
The offset values t
DOFF,DQi
for each of the 16 DQi/DQNi pin
pairs can be different. However, each is constrained to lie
inside the range {t
DOFF,MIN ,
t
DOFF,MAX
}. Furthermore, each
offset value t
DOFF,DQi
is static and will not change during sys-
tem operation. Its value can be determined at initialization.
The 16 receiving windows (j=0..15) for the first pair DQ0/
DQN0 are labeled "0" through "15". Each window has a set
time (t
S,RQ
) and a hold time (t
H,RQ
) measured around a point
t
DOFF,DQ0
+(j/8)*t
CYCLE
after the primary CFM/CFMN
crossing point.
The 16 receiving windows (j=0..15) for the each of the other
pairs DQi/DQNi are also labeled "0" through "15". Each win-
dow has a set time (t
S,RQ
) and a hold time (t
H,RQ
) measured
around a point t
DOFF,DQi
+(j/8)*t
CYCLE
after the primary
CFM/CFMN crossing point.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
67
EDX5116ABSE
Figure 50
DRSL DQ Receive Waveforms
t
S,DQ
CFM
CFMN
[(j)/8]t
CYCLE
DQ0
DQN0
t
DOFF,DQ0
1
2
0
5
6
3
4
j
14
15
t
H,DQ
t
CYCLE
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
DQi
DQNi
t
DOFF,DQi
1
2
0
5
6
3
4
j
14
15
1
2
0
5
6
3
4
j
14
15
t
DOFF,MIN
t
DOFF,MAX
...
...
...
...
...
...
...
...
V
IH,DQ
V
IL,DQ
logic 0
logic 1
...
t
S,DQ
[(j)/8]t
CYCLE
t
H,DQ
t
S,DQ
[(j)/8]t
CYCLE
t
H,DQ
t
IF,DQ
t
IR,DQ
t
IF,DQ
t
IR,DQ
80%
20%
t
IF,DQ
t
IR,DQ
V
IH,DQ
V
IL,DQ
logic 0
logic 1
80%
20%
V
IH,DQ
V
IL,DQ
logic 0
logic 1
80%
20%
i = {0,1,2,3,4,5,...15}
"
DQ15
DQN15
t
DOFF,DQ15
Preliminary Data Sheet E0643E30 (Ver. 3.0)
68
EDX5116ABSE
DRSL DQ Transmit Timing
Figure 51 shows a timing diagram for transmitting read data on
the DQ15..0/DQN15..0 data pins of the memory component.
This diagram represents a magnified view of these pins and
only a few clock cycles are shown (CFM and CFMN are the
clock signals). Timing events are measured to and from the pri-
mary CFM/CFMN crossing point in which CFM makes its
high-voltage-to-low-voltage transition. The DQ15..0/
DQN15..0 signals are high-true: a low voltage represents a log-
ical zero and a high voltage represents a logical one. They are
also differential -- timing events on the DQ15..0/DQN15..0
pins are measured to and from the point that each differential
pair crosses.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise
(t
OR,DQ
) and fall time (t
OF,DQ
) of the signals are measured
from the 20% and 80% points of the full-swing levels.
20% = V
OL,DQ
+ 0.2*(V
OH,DQ
-V
OL,DQ
)
80% = V
OL,DQ
+ 0.8*(V
OH,DQ
-V
OL,DQ
)
There are 16 data transmit windows defined for each
DQ15..0/DQN15..0 pin pair. The transmitting windows for a
particular DQi/DQNi pin pair is referenced to an offset
parameter t
QOFF,DQi
(the index "i" may take on the values {0,
1, ..15} and refers to each of the DQ15..0/DQN15..0 pin
pairs).
The t
QOFF,DQi
+t
Q,DQ,MAX
expression determines the time
between the primary CFM/CFMN crossing point and the off-
set point for the DQi/DQNi pin pair.
The offset values t
QOFF,DQi
for each of the 16 DQi/DQNi pin
pairs can be different. However, each is constrained to lie
inside the range {t
QOFF,MIN ,
t
QOFF,MAX
}. Furthermore, each
offset value t
QOFF,DQi
is static; its value will not change during
system operation. Its value can be determined at initialization
time.
The 16 transmit windows (j=0..15) for the first pair DQ0/
DQN0 are labeled "0" through "15". Each window begins at
the time (t
QOFF,DQ0
+t
Q,DQ,MAX
+((j+0.5)/8)*t
CYCLE
) and
ends at the time (t
QOFF,DQ0
+t
Q,DQ,MIN
+((j+1.5)/8)*t
CYCLE
)
measured after the primary CFM/CFMN crossing point.
The 16 transmit windows (j=0..15) for the other pairs DQi/
DQNi are also labeled "0" through "15". Each window begins
at the time (t
QOFF,DQi
+t
Q,DQ,MAX
+((j+0.5)/8)*t
CYCLE
) and
ends at the time (t
QOFF,DQi
+t
Q,DQ,MIN
+((j+1.5)/8)*t
CYCLE
)
measured after the primary CFM/CFMN crossing point.
Note that when no read data is to be transmitted on the DQ/
DQN pins (and no other component is transmitting on the
external DQ/DQN wires), then the voltage level on the DQ/
DQN pins will follow the voltage reference value
VTERM,DRSL on the VTERM pin. The logical value of each
DQ/DQN pin pair in this no-drive state will be "1/1"; when
read data is driven, each DQ/DQN pin pair will have either
the logical value of "1/0" or "0/1".
Preliminary Data Sheet E0643E30 (Ver. 3.0)
69
EDX5116ABSE
Figure 51
DRSL DQ Transmit Waveforms
t
Q,DQ,MAX
CFM
CFMN
[(j+0.5)/8]t
CYCLE
DQ0
DQN0
t
QOFF,DQ0
2
3
0
1
6
7
4
5
j
14
15
[(j-0.5)/8]t
CYCLE
t
Q,DQ,MIN
t
CYCLE
j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
t
Q,DQ,MAX
[(j+0.5)/8]t
CYCLE
DQi
DQni
t
QOFF,DQi
2
3
0
1
6
7
4
5
j
14
15
[(j-0.5)/8]t
CYCLE
t
Q,DQ,MIN
t
Q,DQ,MAX
[(j+0.5)/8]t
CYCLE
2
3
0
1
6
7
4
5
j
14
15
[(j-0.5)/8]t
CYCLE
t
Q,DQ,MIN
t
QOFF,MIN
t
QOFF,MAX
...
...
...
...
...
...
...
...
80%
20%
logic "0"
logic "1"
...
V
OH,DQ
V
OL,DQ
t
OF,DQ
t
OR,DQ
t
OF,DQ
t
OR,DQ
t
OF,DQ
t
OR,DQ
80%
20%
logic "0"
logic "1"
V
OH,DQ
V
OL,DQ
80%
20%
logic "0"
logic "1"
V
OH,DQ
V
OL,DQ
i = {0,1,2,3,4,5,...15}
DQ15
DQN15
t
QOFF,DQ15
Preliminary Data Sheet E0643E30 (Ver. 3.0)
70
EDX5116ABSE
Serial Interface Receive Timing
Figure 52 shows a timing diagram for the serial interface pins
of the memory component. This diagram represents a magni-
fied view of the pins only a few clock cycles.
The serial interface pins carry low-true signals: a high voltage
represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the V
REF,RSL
level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time
(t
R,SCK
and t
IR,SI
) and fall time (t
F,SCK
and t
IF,SI
) of the signals
are measured from the 20% and 80% points of the full-swing
levels.
20% = V
IL,SI
+ 0.2*(V
IH,SI
-V
IL,SI
)
50% = V
IL,SI
+ 0.5*(V
IH,SI
-V
IL,SI
)
80% = V
IL,SI
+ 0.8*(V
IH,SI
-V
IL,SI
)
There is one receiving window defined for each serial interface
signal (RST,CMD and SDI pins). This window has a set time
(t
S,RQ
) and a hold time (t
H,RQ
) measured around the falling
edge of the SCK clock signal.
Figure 52
Serial Interface Receive Waveforms
SCK
t
CYC,SCK
80%
20%
t
IR,
SI
V
IH,SI
V
IL,SI
logic 1
logic 0
V
REF,RSL
t
S,
SI
t
H,
SI
t
IF,
SI
80%
20%
V
IH,SI
V
IL,SI
logic 1
logic 0
V
REF,RSL
t
L,SCK
t
H,SCK
t
F,SCK
t
R,SCK
RST
CMD
SDI
Preliminary Data Sheet E0643E30 (Ver. 3.0)
71
EDX5116ABSE
Serial Interface Transmit Timing
Figure 53 shows a timing diagram for the serial interface pins
of the memory component. This diagram represents a magni-
fied view of the pins and only a few clock cycles are shown.
The serial interface pins carry low-true signals: a high voltage
represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the V
REF,RSL
level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time
(t
OR,SI
) and fall time (t
OF,SI
) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = V
OL,SI
+ 0.2*(V
OH,SI
-V
OL,SI
)
50% = V
OL,SI
+ 0.5*(V
OH,SI
-V
OL,SI
)
80% = V
OL,SI
+ 0.8*(V
OH,SI
-V
OL,SI
)
There is one transmit window defined for the serial interface
data signal (SDO pins). This window has a maximum delay
time (t
Q,SI,MAX
) from the falling edge of the SCK clock signal
and a minimum delay time (t
Q,SI,MIN
) from the next falling
edge of the SCK clock signal.
When the memory component is not selected during a serial
device read transaction, it will simply pass the information on
the SDI input to the SDO output. This combinational propa-
gation delay parameter is t
P,SI
. The t
CYC,SCK
will need to be
increased during a serial read transaction (relative to the
t
CYC,SCK
value for a serial write transaction) because of the
accumulated propagation delay through all of the XDR DRAM
devices on the serial interface.
During Initialization, when the serial identification is deter-
mined, the SDI-to-SDO path is registered, so the t
CYC,SCK
value can be set to the same value as for serial write transac-
tions. See "Initialization" on page 46.
Figure 53
Serial Interface Transmit Waveforms
SCK
t
CYC,SCK
80%
20%
V
IH,SI
V
IL,SI
logic 1
logic 0
V
REF,RSL
t
L,SCK
t
H,SCK
t
F,SCK
t
R,SCK
80%
20%
t
OR,SI
V
OH,SI
V
OL,SI
logic 1
logic 0
V
REF,RSL
t
Q,SI,MAX
t
Q,SI,MIN
t
OF,SI
80%
20%
V
IH,SI
V
IL,SI
logic 1
logic 0
V
REF,RSL
SDI
t
P,SI
SDO
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
72
EDX5116ABSE
Package Description
Package Parasitic Summary
Table 18 summarizes inductance, capacitance, and resistance
values associated with each pin group for the memory compo-
nent. Most of the parameters have maximum values only, how-
ever some have both maximum and minimum values.
The first group of parameters are for the CFM/CFMN clock
pair pins. They include inductance, capacitance, and resistance
values. The second group of parameters are for the RQ request
pins. They include inductance, mutual inductance, capacitance,
and resistance values. There are also limits on the spread in
inductance and capacitance values allowed in any one memory
component. The third group of parameters are specific to the
DQ data pins and include inductance, mutual inductance,
capacitance, and resistance values. There are also limits on the
spread in inductance and capacitance values allowed in any one
memory component.The fourth group of parameters are for
the serial interface pins. They include inductance and capaci-
tance values.
Table 18
Package Parasitic Summary
(package parasitic values are measured on randomly-sampled devices)
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
L
VTERM
VTERM pin - effective input inductance per four bits
-
2.2
nH
L
I ,CFM
CFM/CFMN pins - effective input inductance
b
-
5.0
nH
C
I ,CFM
CFM/CFMN pins - effective input capacitance
b
1.8
2.4
pF
R
I ,CFM
CFM/CFMN pins - effective input resistance
4
18
L
I ,RQ
RSL RQ pins - effective input inductance
b
-
5.0
nH
C
I ,RQ
RSL RQ pins - effective input capacitance
b
1.8
2.4
pF
R
I ,RQ
RSL RQ pins - effective input resistance
4
18
L
12,RQ
Mutual inductance between adjacent RSL RQ signals
-
0.6
nH
L
I,RQ
Difference in L
I,RQ
between any RSL RQ pins of a single device
-
1.8
nH
C
I,RQ
Difference in C
I
between CFM/CFMN average and RSL RQ pins of single device
-0.12
+0.12
pF
Z
PKG,DQ
DRSL DQ pins - package differential impedance
note - package trace length should be less than 10mm long.
70
130
C
I ,DQ
DRSL DQ pins - effective input capacitance
a
-
1.8
pF
C
I,DQ
Difference in C
I
between DQi and DQNi of each DRSL pair
a
-
0.06
pF
R
I ,DQ
DRSL DQ pins - effective input resistance
4
25
L
I ,SI
Serial Interface effective input inductance
b
-
8.0
nH
C
I ,SI
Serial Interface effective input capacitance
b
(RST, SCK, CMD)
(SDI,SDO)
1.7
-
3.0
7.0
pF
pF
a. This is the effective die input capacitance, and does not include package capacitance.
b. CFM/RQ/SI should include package capacitance / Inductance, only DQ does not include package Capacitance. This value is a combination of the device IO circuitry and pack-
age capacitance & inductance.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
73
EDX5116ABSE
Figure 54
Equivalent Circuits for Package Parasitic
GND Pin
SCK,CMD,RST Pin
Pad
L
I,SI
C
I,SI
GND Pin
RQ Pin
Pad
L
I,RQ
R
I,RQ
C
I,RQ
RQ Pin
L
12,RQ
RQ Pin
L
12,RQ
CFM Pin
GND Pin
GND Pin
DQ Pin
Pad
R
I,DQ
C
I,DQ
Pad
R
I,DQ
C
I,DQ
DQN Pin
Z
PKG,DQ
/2
Z
PKG,DQ
/2
Pad
R
I,CFM
C
I,CFM
Pad
R
I,CFM
C
I,CFM
CFMN Pin
SDI,SDO Pin
R
TERM,DQ
R
TERM,DQ
L
I,CFM
L
I,CFM
Preliminary Data Sheet E0643E30 (Ver. 3.0)
74
EDX5116ABSE
Package Drawing
104-ball FBGA (
BGA)
Solder ball: Lead free (Sn-Ag-Cu)
15.18
0.1
0.2 S A
14.56 0.1
INDEX MARK
0.2 S B
0.10 S
0.10 S
0.40 0.05
S
INDEX MARK
B
104-
0.50 0.05
0.12 M S A B
1.27
12.7
2.0
12.0
0.8
A
Unit: mm
ECA-TS2-0147-01
1.05 0.1
Preliminary Data Sheet E0643E30 (Ver. 3.0)
75
EDX5116ABSE
Package Pin Numbering
Figure 55 summarizes the device package's pin assignments.
Figure 55
CSP x16 Package - Pin Numbering (top view)
1
2
3
4
5
6
7
P
DQ5
DQ5N
DQ7N
DQ7
N
GND
VDD
VTERM
GND
M
DQ1
DQ1N
DQ3N
DQ3
L
GND
RQ10
RQ11
GND
K
VDD
RQ8
RQ9
VDD
J
VDD
RQ6
RQ7
GND
H
VREF
RQ4
CFMN
CFM
G
GND
RQ2
RQ5
GND
F
VDD
RQ0
RQ3
VDD
E
GND
RST
RQ1
GND
D
SD0
CMD
SCK
SDI
C
DQ0
DQ0N
DQ2N
DQ2
B
GND
VDD
VTERM
GND
A
DQ4
DQ4N
DQ6N
DQ6
A8
not used when
width is x1,x2,x4
not used when
width is x1,x2,x4
not used when
width is x1
not used when
width is x1,x2,x4
not used when
width is x1,x2
not used when
width is x1,x2
not used when
width is x1,x2,x4
L
K
J
H
G
F
E
D
C
B
A
1
DQN3
DQN9
VDD
GND
VDD
GND
VDD
SDI
DQN8
DQN2
2
DQ3
DQ9
VDD
GND DQ8 DQ2
3
DQN15
DQN5
VDD
RQ10
CFM
RSRV
RQ4
RQ0
DQN4
DQN14
4
DQ15
DQ5
GND RQ11 CFMN
RSRV RQ3 GND DQ4 DQ14
5
VDD VDD
VTERM
VDD
VTERM VDD VDD
6
GND
GND
GND
GND
GND
VDD
VDD
GND
GND
7
8
9
10
11
GND
VTERM
GND
VDD
GND
GND
VDD
VTERM
GND
12
VDD GND GND
VDD
GND GND VDD
13
DQN7
DQN13
VDD
RQ9
RQ7
VREF
RQ1
VDD
DQN12
DQN6
14
DQ7 DQ13
CMD RQ8 RQ6
RQ5
RQ2 GND DQ12 DQ6
15
DQN11 DQN1 SCK
RST DQN0
DQN10
16
DQ11
DQ1
GND
VDD
VDD
GND
VDD
SDO
DQ0
DQ10
A16
Preliminary Data Sheet E0643E30 (Ver. 3.0)
76
EDX5116ABSE
Recommended Soldering
Conditions
Please consult with our sales offices for soldering conditions
of the EDX5116ABSE.
Type of Surface Mount Device
EDX5116ABSE: 104-ball FBGA (
BGA)
< Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E0643E30 (Ver. 3.0)
77
EDX5116ABSE
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0643E30 (Ver. 3.0)
78
EDX5116ABSE
Rambus and the Rambus Logo are trademarks or registered trademarks of Rambus Inc. in the United States and other countries.
Rambus and other parties may also have trademark rights in other terms used herein.
BGA is a registered trademark of Tessera, Inc.
M01E0107
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
Document Outline
PDF 
ZIP