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- /RAS-Only Refresh Cycle
- /CAS-Before-/RAS Refresh Cycle
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EOL Product

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

HM5117805 Series

16 M EDO DRAM (2-Mword

8-bit)

2 k Refresh

E0156H10 (Ver. 1.0)

(Previous ADE-203-630D (Z))

Jun. 27, 2001

Description

The HM 5117805 i s a C M OS dynam i c R AM orga ni ze d 2, 097,152-w ord

8-bi t . It em pl oys t he m os t

adva nce d C M OS t ec hnology for hi gh per form a nce and l ow powe r. The HM 5117805 off ers Ext ende d Da ta
Out (ED O) P age M ode as a hi gh s pee d ac ce s s m ode. M ul ti pl exe d addr es s i nput per m it s t he HM 5117805 t o
be packaged in standard 28-pin plastic SOJ and 28-pin TSOP.

Features

Single 5 V (±10%)

Access time: 50 ns/60 ns/70 ns (max)

Power dissipation

Active mode: 605 mW/550 mW/495 mW (max)

Standby mode : 11 mW (max)

: 0.83 mW (max) (L-version)

EDO page mode capability

Long refresh period

2048 refresh cycles : 32 ms

: 128 ms (L-version)

4 variations of refresh

RAS-only refresh

CAS-before-RAS refresh

Hidden refresh

Self refresh (L-version)

Battery backup operation (L-version)

EOL Product

HM5117805 Series

Data Sheet E0156H10

Ordering Information

Type No.

Access time

Package

HM5117805J-5
HM5117805J-6
HM5117805J-7

50 ns
60 ns
70 ns

400-mil 28-pin plastic SOJ (CP-28DA)

HM5117805LJ-5
HM5117805LJ -6
HM5117805LJ -7

50 ns
60 ns
70 ns

HM5117805S-5
HM5117805S-6
HM5117805S-7

50 ns
60 ns
70 ns

300-mil 28-pin plastic SOJ (CP-28DNA)

HM5117805LS-5
HM5117805LS-6
HM5117805LS-7

50 ns
60 ns
70 ns

HM5117805TT-5
HM5117805TT-6
HM5117805TT-7

50 ns
60 ns
70 ns

400-mil 28-pin plastic TSOP II (TTP-28DA)

HM5117805LTT-5
HM5117805LTT-6
HM5117805LTT-7

50 ns
60 ns
70 ns

HM5117805TS-5
HM5117805TS-6
HM5117805TS-7

50 ns
60 ns
70 ns

300-mil 28-pin plastic TSOP II (TTP-28DB)

HM5117805LTS-5
HM5117805LTS-6
HM5117805LTS-7

50 ns
60 ns
70 ns

EOL Product

HM5117805 Series

Data Sheet E0156H10

Pin Arrangement

I/O0

I/O1

I/O2

I/O3

RAS

A10

I/O7

I/O6

I/O5

I/O4

CAS

(Top view)

I/O0

I/O1

I/O2

I/O3

RAS

A10

I/O7

I/O6

I/O5

I/O4

CAS

HM5117805TS/LTS Series

(Top view)

HM5117805S/LS Series

HM5117805TT/LTT Series

HM5117805J/LJ Series

Pin Description

Pin name

Function

A0 to A10

Address input
-- Row/Refresh address
-- Column address

A0 to A10
A0 to A9

I/O0 to I/O7

Data input/Data output

RAS

Row address strobe

CAS

Column address strobe

Read/Write enable

Output enable

Power supply

Ground

No connection

EOL Product

HM5117805 Series

Data Sheet E0156H10

Block Diagram

·
·
·

Timing and control

Column

address

buffers

Row

address

buffers

I/O buffers

I/O0

I/O7

RAS

CAS

Column decoder

Row decoder

2M array

A10

EOL Product

HM5117805 Series

Data Sheet E0156H10

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V

1.0 to +7.0

Supply voltage relative to V

1.0 to +7.0

Short circuit output current

Iout

Power dissipation

1.0

Operating temperature

Topr

0 to +70

°C

Storage temperature

Tstg

55 to +125

°C

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

4.5

5.0

5.5

Input high voltage

2.4

6.5

Input low voltage

1.0

0.8

Note:

1. All voltage referred to V

EOL Product

HM5117805 Series

Data Sheet E0156H10

DC Characteristics (Ta = 0 to +70°C, V

= 5 V ± 10%, V

= 0 V)

HM5117805

-5

-6

-7

Parameter

Symbol

Min Max Min Max Min Max Unit

Test conditions

Operating current*

CC1

110 --

100 --

= min

Standby current

CC2

TTL interface

RAS

CAS

= V

Dout = High-Z

CMOS interface

RAS

CAS

0.2 V

Dout = High-Z

Standby current
(L-version)

CC2

150 --

150 µA

CMOS interface

RAS

CAS

0.2 V

Dout = High-Z

RAS

-only refresh current*

CC3

110 --

100 --

= min

Standby current*

CC5

RAS

= V

CAS

= V

Dout = enable

CAS

-before-

RAS

refresh

current

CC6

110 --

100 --

= min

EDO page mode
current*

CC7

100 --

HPC

= min

Battery backup current*

(Standby with CBR refresh)
(L-version)

CC10

500 --

500 µA

CMOS interface
Dout = High-Z
CBR refresh:
t

= 62.5 µs

RAS

0.3 µs

Self refresh mode current
(L-version)

CC11

300 --

300 µA

CMOS interface

RAS

CAS

0.2V

Dout = High-Z

Input leakage current

10 10

µA

0 V

Vin

7 V

Output leakage current

10 10

µA

0 V

Vout

7 V

Dout = disable

Output high voltage

2.4

High Iout = 2 mA

Output low voltage

0.4

Low Iout = 2 mA

Notes: 1. I

depends on output load condition when the device is selected. I

max is specified at the output

open condition.

2. Address can be changed once or less while

RAS

= V

3. Address can be changed once or less while

CAS

= V

CAS

= L (

0.2 V) while

RAS

= L (

0.2 V).

EOL Product

HM5117805 Series

Data Sheet E0156H10

Capacitance (Ta = 25°C, V

= 5 V ± 10%)

Parameter

Symbol

Typ

Max

Unit

Notes

Input capacitance (Address)

Input capacitance (Clocks)

Output capacitance (Data-in, Data-out)

I/O

1, 2

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

CAS

= V

to disable Dout.

AC Characteristics (Ta = 0 to +70°C, V

= 5 V ±10%, V

= 0 V)

*1, *2, *18

Test Conditions

Input rise and fall time: 2 ns

Input levels: V

= 0 V, V

= 3 V

Input timing reference levels: 0.8 V, 2.4 V

Output timing reference levels: 0.8 V, 2.0 V

Output load: 1 TTL gate + C

(100 pF) (Including scope and jig)

EOL Product

HM5117805 Series

Data Sheet E0156H10

Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)

HM5117805

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Random read or write cycle time

104

124

RAS

precharge time

CAS

precharge time

RAS

pulse width

RAS

10000 60

10000 70

10000 ns

CAS

pulse width

CAS

10000 10

10000 13

10000 ns

Row address setup time

ASR

Row address hold time

RAH

Column address setup time

ASC

Column address hold time

CAH

RAS

CAS

delay time

RCD

RAS

to column address delay time t

RAD

RAS

hold time

RSH

CAS

hold time

CSH

CAS

RAS

precharge time

CRP

to Din delay time

OED

delay time from Din

DZO

CAS

delay time from Din

DZC

Transition time (rise and fall)

EOL Product

HM5117805 Series

Data Sheet E0156H10

Read Cycle

HM5117805

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Access time from

RAS

RAC

8, 9

Access time from

CAS

CAC

9, 10, 17

Access time from address

9, 11, 17

Access time from

OEA

Read command setup time

RCS

Read command hold time to

CAS

RCH

Read command hold time from

RAS

RCHR

Read command hold time to

RAS

RRH

Column address to

RAS

lead time

RAL

Column address to

CAS

lead time

CAL

CAS

to output in low-Z

CLZ

Output data hold time

Output data hold time from

OHO

Output buffer turn-off time

OFF

13, 20

Output buffer turn-off to

OEZ

CAS

to Din delay time

CDD

Output data hold time from

RAS

OHR

Output buffer turn-off to

RAS

OFR

Output buffer turn-off to

WEZ

to Din delay time

WED

RAS

to Din delay time

RDD

RAS

CAS

delay time

RNCD

EOL Product

HM5117805 Series

Data Sheet E0156H10

Write Cycle

HM5117805

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write command setup time

WCS

Write command hold time

WCH

Write command pulse width

Write command to

RAS

lead time

RWL

Write command to

CAS

lead time

CWL

Data-in setup time

Data-in hold time

Read-Modify-Write Cycle

HM5117805

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Read-modify-write cycle time

RWC

111

135

161

RAS

delay time

RWD

CAS

delay time

CWD

Column address to

delay time

AWD

hold time from

OEH

Refresh Cycle

HM5117805

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

CAS

setup time (CBR refresh cycle) t

CSR

CAS

hold time (CBR refresh cycle)

CHR

setup time (CBR refresh cycle)

WRP

hold time (CBR refresh cycle)

WRH

RAS

precharge to

CAS

hold time

RPC

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Cycle

HM5117805

-5

-6

-7

Parameter

Symbol

Min Max

Unit

Notes

EDO page mode cycle time

HPC

EDO page mode

RAS

pulse width

RASP

100000 --

100000 ns

Access time from

CAS

precharge

CPA

9, 17

RAS

hold time from

CAS

precharge t

CPRH

Output data hold time from

CAS

low t

DOH

9, 17

CAS

hold time referred

COL

CAS

setup time

COP

Read command hold time from

CAS

precharge

RCHC

EDO Page Mode Read-Modify-Write Cycle

HM5117805

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

EDO page mode read- modify-write
cycle time

HPRWC

delay time from

CAS

precharge t

CPW

Refresh

Parameter

Symbol

Max

Unit

Note

Refresh period

REF

2048 cycles

Refresh period (L-version)

REF

128

2048 cycles

EOL Product

HM5117805 Series

Data Sheet E0156H10

Self Refresh Mode (L-version)

HM5117805L

-5

-6

-7

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

RAS

pulse width (self refresh)

RASS

100

µs

RAS

precharge time (self refresh)

RPS

110

130

CAS

hold time (self refresh)

CHS

Notes: 1. AC measurements assume t

= 2 ns.

2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization

cycles (any combination of cycles containing

RAS

-only refresh or

CAS

-before-

RAS

refresh). If the

internal refresh counter is used, a minimum of eight

CAS

-before-

RAS

refresh cycles are required.

3. Operation with the t

RCD

(max) limit insures that t

RAC

(max) can be met, t

RCD

(max) is specified as a

reference point only; if t

RCD

is greater than the specified t

RCD

(max) limit, then access time is

controlled exclusively by t

CAC

4. Operation with the t

RAD

(max) limit insures that t

RAC

(max) can be met, t

RAD

(max) is specified as a

reference point only; if t

RAD

is greater than the specified t

RAD

(max) limit, then access time is

controlled exclusively by t

5. Either t

OED

or t

CDD

must be satisfied.

6. Either t

DZO

or t

DZC

must be satisfied.

7. V

(min) and V

(max) are reference levels for measuring timing of input signals. Also, transition

times are measured between V

(min) and V

(max).

8. Assumes that t

RCD

(max) and t

RAD

(max). If t

RCD

or t

RAD

is greater than the maximum

recommended value shown in this table, t

RAC

exceeds the value shown.

9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.

10. Assumes that t

RCD

(max) and t

RAD

(max).

11. Assumes that t

RCD

(max) and t

RAD

(max).

12. Either t

RCH

or t

RRH

must be satisfied for a read cycles.

13. t

OFF

(max) and t

OEZ

(max) define the time at which the outputs achieve the open circuit condition and

are not referred to output voltage levels.

14. t

WCS

, t

RWD

, t

CWD

, t

AWD

and t

CPW

are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only; if t

WCS

(min), the cycle is an early write cycle and the

data out pin will remain open circuit (high impedance) throughout the entire cycle; if t

RWD

(min),

CWD

(min), and t

AWD

(min), or t

CWD

(min), t

AWD

(min) and t

CPW

(min), the

cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.

15. These parameters are referred to

CAS

leading edge in early write cycles and to

leading edge

in delayed write or read-modify-write cycles.

16. t

RASP

defines

RAS

pulse width in EDO page mode cycles.

17. Access time is determined by the longest among t

, t

CAC

and t

CPA

18. In delayed write or read-modify-write cycles,

must disable output buffer prior to applying data

to the device.

19. t

HPC

(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read

cycles. If both write and read operation are mixed in a EDO page mode

RAS

cycle (EDO page

mode mix cycle (1), (2)), minimum value of

CAS

cycle (t

CAS

+ t

+ 2 t

) becomes greater than the

specified t

HPC

(min) value.The value of

CAS

cycle time of mixed EDO page mode is shown in EDO

page mode mix cycle (1) and (2).

EOL Product

HM5117805 Series

Data Sheet E0156H10

20. Data output turns off and becomes high impedance from later rising edge of

RAS

and

CAS

. Hold

time and turn off time are specified by the timing specifications of later rising edge of

RAS

and

CAS

between t

OHR

and t

and between t

OFR

and t

OFF

21. Please do not use t

RASS

timing, 10 µs

RASS

100 µs. During this period, the device is in transition

state from normal operation mode to self refresh mode. If t

RASS

100 µs, then

RAS

precharge time

should use t

RPS

instead of t

22. If you use

RAS

only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of

distributed CBR refresh with 15.6 µs interval should be executed within 32 ms immediately after
exiting from and before entering into the self refresh mode.

23. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR

refresh should be executed within 15.6 µs immediately after exiting from and before entering into
self refresh mode.

24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self

fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.

25. XXX: H or L (H: V

(min)

(max), L: V

(min)

(max))

///////: Invalid Dout

When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V

or V

EOL Product

HM5117805 Series

Data Sheet E0156H10

Timing Waveforms

*25

Read Cycle

RAS

Address

Dout

Din

RAS

CSH

CRP

RCD

RSH

CAS

RAD

RAL

CAL

ASC

CAH

ASR

Row

Column

RAH

RCS

RCH

RRH

CDD

DZC

High-Z

Dout

DZO

OED

RAC

OEA

CAC

CLZ

OFF

OHO

OEZ

CAS

RDD

WED

OFR

OHR

WEZ

RCHR

EOL Product

HM5117805 Series

Data Sheet E0156H10

Early Write Cycle

RAS

Address

Din

Dout

RAS

CRP

CSH

RCD

RSH

CAS

ASR

RAH

ASC

CAH

Column

Row

WCS

WCH

Din

WCS

(min)

High-Z*

CAS

EOL Product

HM5117805 Series

Data Sheet E0156H10

Delayed Write Cycle

*18

Address

CAS

RAS

Din

Dout

RAS

CSH

RCD

RSH

CAS

CRP

Column

Row

ASR

RAH

ASC

CAH

RCS

CWL

RWL

DZC

DZO

OED

OEH

CLZ

OEZ

High-Z

Din

High-Z

Invalid Dout

EOL Product

HM5117805 Series

Data Sheet E0156H10

Read-Modify-Write Cycle

*18

Address

RAS

Din

Dout

RWC

RAS

CRP

CAS

RCD

RAD

ASR

RAH

ASC

CAH

Column

Row

RCS

CWD

CWL

AWD

RWD

RWL

DZC

Din

High-Z

DZO

OED

OEH

OEA

CAC

RAC

OHO

OEZ

CLZ

Dout

High-Z

CAS

EOL Product

HM5117805 Series

Data Sheet E0156H10

RAS-Only Refresh Cycle

RAS

CAS

Address

Dout

High-Z

Row

RAS

CRP

RPC

CRP

ASR

RAH

OFF

OFR

EOL Product

HM5117805 Series

Data Sheet E0156H10

CAS-Before-RAS Refresh Cycle

RAS

CAS

Dout

Address

RAS

RPC

CSR

CHR

RPC

CRP

WRH

WRP

OFF

OFR

High-Z

EOL Product

HM5117805 Series

Data Sheet E0156H10

Hidden Refresh Cycle

Din

Dout

Address

RAS

RCD

RSH

CHR

CRP

RAD

RAL

CAH

ASC

RAH

ASR

CDD

DZC

DZO

OED

OEZ

OHO

OFF

CAC

RAC

CLZ

Dout

Column

Row

OEA

High-Z

RCH

RRH

CAS

WED

RDD

WEZ

OFR

OHR

RCS

WRH

RRH

WRP

WRH

WRP

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Read Cycle

Din

Dout

Address

RAS

CAS

RCH

RRH

DZC

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

OHR

COL

CPA

CAC

OEA

RAC

CAC

CPA

OEZ

OEA

OEZ

CAC

RASP

COP

CAS

CAL

CSH

HPC

CRP

ASR

RAH

Column 1

Column 2

Column 3

Column 4

CAH

ASC

CAH

ASC

CAH

ASC

WED

RAL

Row

Dout 2

Dout 4

Dout 1

CAS

RCS

Dout 3

OHO

CPRH

HPC

OEA

WEZ

DZO

OED

RNCD

OHO

DOH

RCH

RCHR

CAL

RSH

RCHC

CPA

ASC

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Early Write Cycle

* t

WCS

(min)

RAS

Address

Din

Dout

RASP

CSH

HPC

RSH

CRP

CAS

RCD

ASR

RAH

ASC

CAH

ASC

CAH

ASC

CAH

WCH

WCS

WCH

WCS

WCH

WCS

Din 1

Din 2

Din N

High-Z*

Row

Column 1

Column 2

Column N

CAS

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Delayed Write Cycle

*18

Din

Dout

Address

RAS

RASP

CRP

RSH

CAS

HPC

CAS

CSH

RCD

ASC

CAH

ASC

CAH

ASC

CAH

RAD

ASR

RAH

RCS

RWL

CWL

DZC

DZO

OED

DZO

OED

DZO

OED

OEH

OEZ

CLZ

OEZ

CLZ

OEZ

Invalid Dout

Din

Column N

Column 2

Column 1

Row

High-Z

CAS

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Read-Modify-Write Cycle

*18

Din

Dout

Address

RAS

RASP

CRP

HPRWC

RCD

CAS

RAD

ASR

ASC

RAH

CAH

CWL

CPW

CWL

CPW

CWL

RWD

AWD

CWD

RCS

CWD

RCS

CWD

RCS

DZC

DZO

OEH

RAC

OEZ

CLZ

Dout N

Dout 2

Dout 1

Din

Column N

Column 2

Column 1

Row

RWL

OHO

OEA

CAC

OEZ

CLZ

OHO

OEA

CAC

CPA

OEZ

CLZ

OHO

OEA

CAC

CPA

High-Z

OED

RSH

CAS

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Mix Cycle (1)

Din

Dout

Address

RAS

CAS

RCH

RRH

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

CPA

CAC

CPA

OEZ

OEA

RASP

CAS

CRP

ASR

RAH

Column 1

Column 2

Column 3

Column 4

ASC

CAH

ASC

CAH

RAL

CAL

Row

Dout 2

Dout 4

CPA

CAS

WCS

Dout 3

WCH

WED

WEZ

Din 3

Din 1

OEA

OED

CAC

ASC

CPW

AWD

OHO

CAL

RCS

CSH

RCD

RSH

DOH

ASC

EOL Product

HM5117805 Series

Data Sheet E0156H10

EDO Page Mode Mix Cycle (2)

Din

Dout

Address

RAS

CAS

RNCD

RCH

RRH

CDD

RDD

High-Z

OFR

OEZ

OHO

OFF

CPA

CAC

OEZ

OEA

RASP

CAS

CSH

CRP

ASR

RAH

Column 1

Column 2

Column 3

Column 4

ASC

CAH

ASC

CAH

ASC

CAH

RAL

RCS

Row

Dout 1

Dout 4

CPA

CAS

Dout 3

OHO

WED

WEZ

Din 3

Din 2

OEA

CAC

CPW

RCH

RCS

WCH

RAC

OED

COL

OEA

OHO

OEZ

OED

RCS

CAL

RCD

RCHR

WCS

RSH

ASC

COP

EOL Product

HM5117805 Series

Data Sheet E0156H10

Self Refresh Cycle (L-version)

*21, 22, 23, 24

RAS

Dout

RASS

RPS

RPC

CSR

CHS

CRP

OFF

OFR

High-Z

CAS

WRP

WRH

EOL Product

HM5117805 Series

Data Sheet E0156H10

Package Dimensions

HM5117805J/LJ Series (CP-28DA)

9.40

0.25

0.43

0.10

3.50

0.26

18.54 Max

18.17

0.74

10.16

0.13

11.18

0.13

0.10

2.85

0.12

1.30 Max

1.27

0.80

+0.25 0.17

Hitachi Code
JEDEC
EIAJ
Weight (reference value)

CP-28DA
Conforms
Conforms
1.16 g

0.41

0.08

Unit: mm

Dimension including the plating thickness

Base material dimension

EOL Product

HM5117805 Series

Data Sheet E0156H10

HM5117805S/LS Series (CP-28DNA)

0.43

0.10

3.50

0.26

1.165 Max

0.10

1.27

Hitachi Code
JEDEC
EIAJ
Weight (reference value)

CP-28DNA
--
--
0.95 g

0.41

0.08

Unit: mm

6.79

0.18

+ 0.25

0.36

2.45

0.74

18.84 Max

18.41

7.62

0.12

8.51

0.12

0.90

0.26

Dimension including the plating thickness

Base material dimension

EOL Product

HM5117805 Series

Data Sheet E0156H10

HM5117805TT/LTT Series (TTP-28DA)

1.27

0.21

0.42

0.08

0.10

10.16

18.41

18.81 Max

1.20 Max

0.13

0.05

11.76

0.20

0.50

0.10

1.15 Max

0.145

0.05

0.68

0.80

Hitachi Code
JEDEC
EIAJ
Weight (reference value)

TTP-28DA
Conforms
--
0.43 g

0.40

0.06

0.125

0.04

Unit: mm

Dimension including the plating thickness

Base material dimension

EOL Product

HM5117805 Series

Data Sheet E0156H10

HM5117805TS/LTS Series (TTP-28DB)

Hitachi Code
JEDEC
EIAJ
Weight (reference value)

TTP-28DB
--
--
0.35 g

18.41

18.81 Max

1.27

0.21

0.42

0.08

1.20 Max

0.10

7.62

9.22

0.2

0.13

0.05

1.15 Max

0.50

0.10

0.63

0.145

0.05

0.40

0.06

0.125

0.04

0.80

Unit: mm

Dimension including the plating thickness

Base material dimension

EOL Product

HM5117805 Series

Data Sheet E0156H10

Cautions

1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any

third party's patent, copyright, trademark, or other intellectual property rights for information contained
in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third
party's rights, including intellectual property rights, in connection with use of the information contained
in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.

However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such
as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily
injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Elpida Memory, Inc..

7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.

semiconductor products.

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Document Outline

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