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Электронный компонент: HM5216165

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EOL Product
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM5216165 Series
16 M LVTTL Interface SDRAM (512-kword
16-bit
2-bank)
100 MHz/83 MHz
E0167H10 (Ver. 1.0)
(Previous ADE-203-280C (Z))
Jun. 12, 2001
Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2
banks for improved performance.
Features
3.3 V Power supply
Clock frequency: 100 MHz/83 MHz
LVTTL interface
Single pulsed
RAS
2 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
Programmable
CAS latency: 1/2/3
Byte control by DQMU and DQML
Refresh cycles: 4096 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
EOL Product
HM5216165 Series
Data Sheet E0167H10
2
Ordering Information
Type No.
Frequency
Package
HM5216165TT-10H
HM5216165TT-12
100 MHz
83 MHz
400-mil 50-pin plastic TSOP II (TTP-50D)
Pin Arrangement
V
CC
I/O0
I/O1
V
SS
Q
I/O2
I/O3
V
CC
Q
I/O4
I/O5
V
SS
Q
I/O6
I/O7
V
CC
Q
DQML
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
V
SS
I/O15
I/O14
V
SS
Q
I/O13
I/O12
V
CC
Q
I/O11
I/O10
V
SS
Q
I/O9
I/O8
V
CC
Q
NC
DQMU
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
HM5216165TT Series
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
EOL Product
HM5216165 Series
Data Sheet E0167H10
3
Pin Description
Pin name
Function
A0 to A11
Address input
Row address
A0 to A10
Column address
A0 to A7
Bank select address A11
I/O0 to I/O15
Data-input/output
CS
Chip select
RAS
Row address strobe command
CAS
Column address strobe command
WE
Write enable command
DQMU
DQML
Upper byte input/output mask
Lower byte input/output mask
CLK
Clock input
CKE
Clock enable
V
CC
Power for internal circuit
V
SS
Ground for internal circuit
V
CC
Q
Power for I/O pin
V
SS
Q
Ground for I/O pin
NC
No connection
EOL Product
HM5216165 Series
Data Sheet E0167H10
4
Block Diagram
Column address
counter
Column address
buffer
Row address
buffer
Refresh
counter
A0 A11
A0 A11
I/O0 I/O15
Input
buffer
Output
buffer
Control logic &
timing generator
Row decoder
Row decoder
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Memory array
CLK
CKE
CS
RAS
CAS
WE
DQML
A0 A7
Bank 0
Bank 1
DQMU
2048 row X 256 column X 16 bit
2048 row X 256 column X 16 bit
EOL Product
HM5216165 Series
Data Sheet E0167H10
5
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is
precharged.
A11 (input pin): A11 is a bank select signal (BS). The memory array of the HM5216165 is divided into
bank 0 and bank 1, both which contain 2048 row
256 column
16 bits. If A11 is Low, bank 0 is selected,
and if A11 is High, bank 1 is selected.
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK
rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down
and clock suspend modes.
DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output
buffers.
Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low,
the output buffer becomes Low-Z.
Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If
DQMU/DQML is Low, the data is written.
I/O0 to I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a
conventional DRAM.
V
CC
and V
CC
Q (power supply pins): 3.3 V is applied. (V
CC
is for the internal circuit and V
CC
Q is for the
output buffer).
V
SS
and V
SS
Q (power supply pins): Ground is connected. (V
SS
is for the internal circuit and V
SS
Q is for the
output buffer.)
EOL Product
HM5216165 Series
Data Sheet E0167H10
6
Command Operation
Command Truth Table
The synchronous DRAM recognizes the following commands specified by the
CS, RAS, CAS, WE and
address pins.
Function
Symbol
CKE
n - 1 n
CS
RAS CAS WE
A11 A10
A0
to A9
Ignore command
DESL
H
H
No operation
NOP
H
L
H
H
H
Burst stop in full page
BST
H
L
H
H
L
Column address and read command
READ
H
L
H
L
H
V
L
V
Read with auto-precharge
READ A
H
L
H
L
H
V
H
V
Column address and write command
WRIT
H
L
H
L
L
V
L
V
Write with auto-precharge
WRIT A
H
L
H
L
L
V
H
V
Row address strobe and bank act.
ACTV
H
L
L
H
H
V
V
V
Precharge select bank
PRE
H
L
L
H
L
V
L
Precharge all bank
PALL
H
L
L
H
L
H
Refresh
REF/SELF H
V
L
L
L
H
Mode register set
MRS
H
L
L
L
L
V
V
V
Note:
H: V
IH
. L: V
IL
.
: V
IH
or V
IL
. V: Valid address input
Ignore command [DESL]: When this command is set (
CS is High), the synchronous DRAM ignore
command input at the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page
(256)), and is illegal otherwise. Full page burst continues until this command is input. When data
input/output is completed for a full-page of data (256), it automatically returns to the start address, and
input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY7) and the bank select address
(BS). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page (256), this command is
illegal.
EOL Product
HM5216165 Series
Data Sheet E0167H10
7
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A11) become the
burst write start address. When the single write mode is selected, data is only written to the location specified
by the column address (AY0 to AY7) and the bank select address (A11).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page
(256), this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11
(BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is
High, bank 1 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If
A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
DQM Truth Table
Function
Symbol
CKE
n - 1
n
DQMU
DQML
Upper byte write enable/output enable
ENBU
H
L
Lower byte write enable/output enable
ENBL
H
L
Upper byte write inhibit/output disable
MASKU
H
H
Lower byte write inhibit/output disable
MASKL
H
H
Note:
H: V
IH
. L: V
IL
.
: V
IH
or V
IL
.
I
DOD
is needed.
The HM5216165 series can mask input/output data by means of DQMU and DQML. DQMU masks the
upper byte and DQML masks the lower byte. During reading, the output buffer is set to Low-Z by setting
DQMU/DQML to Low, enabling data output. On the other hand, when DQMU/DQML is set to High, the
output buffer becomes High-Z, disabling data output. During writing, data is written by setting
DQMU/DQML to Low. When DQMU/DQML is set to High, the previous data is held (the new data is not
written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details,
refer to the DQM control section of the HM5216165 operating instructions.
EOL Product
HM5216165 Series
Data Sheet E0167H10
8
CKE Truth Table
Current state
Function
CKE
n-1
n
CS
RAS CAS
WE
Address
Active
Clock suspend mode entry
H
L
H
Any
Clock suspend
L
L
Clock suspend
Clock suspend mode exit
L
H
Idle
Auto refresh command REF
H
H
L
L
L
H
Idle
Self refresh entry SELF
H
L
L
L
L
H
Idle
Power down entry
H
L
L
H
H
H
H
L
H
Self-refresh
Self refresh exit SELFX
L
H
L
H
H
H
L
H
H
Power down
Power down exit
L
H
L
H
H
H
L
H
H
Note:
H: V
IH
. L: V
IL
.
: V
IH
or V
IL
.
Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by
setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as
shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ A suspend: The data being output is held (and continues to be output).
WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the
internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM
starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAMs.)
During the auto refresh operation, refresh address and bank select address are generated inside the
synchronous DRAM. For every auto refresh cycle, the internal address counter is updated. Accordingly,
4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the
banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed
after auto refresh, no precharge command is required after auto refresh.
EOL Product
HM5216165 Series
Data Sheet E0167H10
9
Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM
starts self refresh operation. After the execution of this command, self refresh continues while CKE is Low.
Since self refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can
exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE
state.
Power down exit: When this command is executed at the power down mode, the synchronous DRAM can
exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE
state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the synchronous DRAM.
Current state
CS
RAS CAS WE
Address
Command
Operation
Precharge
H
DESL
Enter IDLE after t
RP
L
H
H
H
NOP
Enter IDLE after t
RP
L
H
H
L
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Idle
H
DESL
NOP
L
H
H
H
NOP
NOP
L
H
H
L
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
EOL Product
HM5216165 Series
Data Sheet E0167H10
10
Current state
CS
RAS CAS WE
Address
Command
Operation
Row active
H
DESL
NOP
L
H
H
H
NOP
NOP
L
H
H
L
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
Begin read
L
H
L
L
BA, CA, A10
WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*
3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read
H
DESL
Continue burst to end
L
H
H
H
NOP
Continue burst to end
L
H
H
L
BST
Burst stop on full page
L
H
L
H
BA, CA, A10
READ/READ A
Continue burst read to
CAS
latency and new read
L
H
L
L
BA, CA, A10
WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*
3
L
L
H
L
BA, A10
PRE, PALL
Term burst read and Precharge
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read with
auto-precharge
H
DESL
Continue burst to end and
precharge
L
H
H
H
NOP
Continue burst to end and
precharge
L
H
H
L
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*
3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
EOL Product
HM5216165 Series
Data Sheet E0167H10
11
Current state
CS
RAS CAS WE
Address
Command
Operation
Write
H
DESL
Continue burst to end
L
H
H
H
NOP
Continue burst to end
L
H
H
L
BST
Burst stop on full page
L
H
L
H
BA, CA, A10
READ/READ A
Term burst and new read
L
H
L
L
BA, CA, A10
WRIT/WRIT A
Term burst and new write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*
3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
precharge*
2
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Write with
auto-precharge
H
DESL
Continue burst to end and
precharge
L
H
H
H
NOP
Continue burst to end and
precharge
L
H
H
L
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*
3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Refresh
(auto refresh)
H
DESL
Enter IDLE after t
RC
L
H
H
H
NOP
Enter IDLE after t
RC
L
H
H
L
BST
Enter IDLE after t
RC
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL
L
L
L
H
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Notes: 1. H: V
IH
. L: V
IL
.
: V
IH
or V
IL
.
The other combinations are inhibit.
2. An interval of t
DPL
is required between the final valid data input and the precharge command.
3. If t
RRD
is not satisfied, this operation is illegal.
EOL Product
HM5216165 Series
Data Sheet E0167H10
12
From [PRECHARGE]
To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the
IDLE state after t
RP
has elapsed from the completion of precharge.
From [IDLE]
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From [ROW ACTIVE]
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t
RCD
is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an interval
of t
RAS
is required.)
From [READ]
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r
CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge mode.
EOL Product
HM5216165 Series
Data Sheet E0167H10
13
From [READ with AUTO PRECHARGE]
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the synchronous DRAM then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
From [WRITE]
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge
mode.
From [WRITE with AUTO-PRECHARGE]
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of t
RC
is required.)
Attempting to make the currently active bank active results in an illegal command.
From [REFRESH]
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after t
RC
), the synchronous DRAM automatically
enters the IDLE state.
EOL Product
HM5216165 Series
Data Sheet E0167H10
14
Simplified State Diagram
PRECHARGE
WRITE
SUSPEND
READ
SUSPEND
ROW
ACTIVE
IDLE
IDLE
POWER
DOWN
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
POWER
ON
WRITEA
WRITEA
SUSPEND
READA
READA
SUSPEND
ACTIVE
CLOCK
SUSPEND
SR ENTRY
SR EXIT
MRS
REFRESH
CKE
CKE_
ACTIVE
WRITE
READ
WRITE
WITH AP
READ
WITH AP
POWER
APPLIED
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
CKE
CKE_
PRECHARGE
AP
READ
WRITE
WRITE
WITH
AP
READ
WITH
READ
WITH AP
WRITE
WITH AP
PRECHARGE
PRECHARGE
PRECHARGE
BST
(on full page)
BST
(on full page)
*1
READ
Read
WRITE
Write
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
EOL Product
HM5216165 Series
Data Sheet E0167H10
15
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A11, A10, A9, A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the
column address specified in the write cycle.
Burst read and SINGLE WRITE: Data is only written to the column address specified during the write
cycle, regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle.
A6, A5, A4: (LMODE): These pins specify the
CAS latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
A2 A1
A0
Burst Length
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
1
1
F.P.
BT=0
BT=1
1
0
0
R
1
1
0
R
1
2
4
8
R
R
R
A3
0 Sequential
1
Interleave
Burst Type
A6
A5
A4 CAS Latency
0
0
0
R
0
0
1
1
0
1
0
2
0
1
1
3
1
X
X
R
R is Reserved(inhibit)
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
R
Write mode
A8
0
1
Burst read and burst write
1
Burst read and SINGLE WRITE
0
1
R
1
1
0
1
R
R
F.P. =Full Page (256)
A10
A11
A10
0
X
X
X
A11
0
X
X
X
X: 0 or 1
EOL Product
HM5216165 Series
Data Sheet E0167H10
16
Burst Sequence
A2
A1
A0
Addressing(decimal)
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
Interleave
Sequence
1
0
0
1
1
0
1
0
1
Starting Ad.
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0,
0, 1,
0, 1, 2,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
6,
4, 5,
6, 5, 4,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
6, 5, 4, 3, 2, 1, 0,
Burst length = 8
A1
A0
Addressing(decimal)
0
0
0
1
1
0
1
1
Interleave
Sequence
Starting Ad.
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Burst length = 4
A0
Addressing(decimal)
0
1
Interleave
Sequence
Starting Ad.
0, 1,
1, 0,
0, 1,
1, 0,
Burst length = 2
EOL Product
HM5216165 Series
Data Sheet E0167H10
17
Operation of HM5216165 Series
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the
status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank
active command cycle. An interval of t
RCD
is required between the bank active command input and the
following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CAS Latency-1) cycle after read command set. HM5216165 series can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page (256). The start address for a burst read is specified by
the column address (AY0 to AY7) and the bank select address (A11) at the read command set cycle. In a read
operation, data output starts after the number of cycles specified by the
CAS Latency. The CAS Latency can
be set to 1, 2, 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the
next cycle after the successive burst-length data has been output. When the burst length is full-page (256),
data is repeatedly output until the burst stop command is input. The
CAS latency and burst length must be
specified at the mode register.
CAS Latency
READ
CLK
Command
Dout
ACTV
Row
Column
out 0
out 1
out 2
out 3
Address
CL = 1
CL = 2
CL = 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
t
RCD
CL:
CAS
latency
Burst length = 4
EOL Product
HM5216165 Series
Data Sheet E0167H10
18
Burst Length
READ
CLK
Command
Dout
ACTV
Row
Column
out 0
out 6
out 7
out 8
Address
out 0 out 1
out 4
out 5
out 0 out 1 out 2 out 3
BL = 1
out 0 out 1 out 2
out 3
out 0 out 1 out 2 out 3
out 6
out 7
out 4
out 5
out 255
out 0
out 1
BL = 2
BL = 4
BL = 8
BL = full page (256)
t
RCD
BL: Burst length
CAS
latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the
mode register.
Burst write
A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same
cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and
full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7)
and the bank select address (A11) at the write command set cycle.
WRIT
CLK
Command
Din
ACTV
Row
Column
in 0
in 6
in 7
in 8
Address
in 1
in 4
in 5
in 3
BL = 1
in 6
in 7
in 4
in 5
in 255
in 0
in 1
BL = 2
BL = 4
BL = 8
BL = full page (256)
t
RCD
in 0
in 0
in 0
in 0
in 1
in 1
in 1
in 2
in 2
in 2
in 3
in 3
CAS
latency = 1, 2, 3
EOL Product
HM5216165 Series
Data Sheet E0167H10
19
Single write
A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is
only written to the column address (AY0 to AY7) and the bank select address (A11) specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0).
Write
CLK
Command
Din
Active
Row
Column
in 0
Address
t
RCD
CAS
latency = 1, 2, 3
Burst length = 1, 2, 4, 8, full page
EOL Product
HM5216165 Series
Data Sheet E0167H10
20
Auto Precharge
Read with auto precharge: In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command executed
for the same bank after the execution of this command must be the bank active (ACTV) command. In
addition, an interval defined by l
APR
is required before execution of the next command.
CAS
latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
1
same cycle as the final data is output
CLK
READ
CL = 1 Command
out0
out1
out2
Dout
lAPR
out3
ACTV
READ
out0
out1
READ
out0
out2
out3
ACTV
out2
out1
lAPR
lAPR
CL = 2 Command
CL = 3 Command
Dout
Dout
ACTV
out3
Note: Internal auto-precharge starts at the timing indicated by " ".
At CLK = 50 MHz ( l changes depending on the operating frequency. )
APR
EOL Product
HM5216165 Series
Data Sheet E0167H10
21
Write with auto precharge: In this operation, since precharge is automatically performed after completing a
burst write or single write operation, a precharge command need not be executed after each write operation.
The command executed for the same bank after the execution of this command must be the bank active
(ACTV) command. In addition, an interval of l
APW
is required between the final valid data input and input of
the next command.
Burst Write (Burst Length = 4)
CLK
Command
I/O (input)
WRIT
l
in0
in1
in2
APW
ACTV
in3
Single Write
CLK
Command
I/O (input)
lAPW
WRIT
ACTV
in
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during
a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The
timing from command input to the last data changes depending on the
CAS latency setting. In addition, the
BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8.
CAS
latency
BST to valid data
BST to high impedance
1
0
1
2
1
2
3
2
3
EOL Product
HM5216165 Series
Data Sheet E0167H10
22
CAS Latency = 1, Burst Length = full page
CLK
Command
I/O (output)
out
out
out
out
l
BSR
0 cycle
l
BSH
1 cycle
BST
out
CAS Latency = 2, Burst Length = full page
l = 1 cycle
BSR
CLK
Command
I/O (output)
out
out
out
out
l = 2 cycle
BSH
BST
out
out
CAS Latency = 3, Burst Length = full page
l = 2 cycle
BSR
CLK
Command
I/O (output)
out
out
out
out
l = 3 cycle
BSH
BST
out
out
out
EOL Product
HM5216165 Series
Data Sheet E0167H10
23
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent
cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst
lengths of 1, 2, 4 and 8. And an interval of t
DPL
is required between the BST command and the next precharge
command.
Burst Length = full page
t
CLK
Command
I/O (input)
in
DPL
in
PRE/PALL
BST
I = 0 cycle
BSW
EOL Product
HM5216165 Series
Data Sheet E0167H10
24
Command Intervals
Read command to Read command interval:
Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CLK
Command
Dout
out B3
Address
(A0-A10)
out B1 out B2
BS (A11)
ACTV
Row
Column A
READ
READ
Column B
out A0 out B0
Bank0
Active
Column =A
Read
Column =B
Read
Column =A
Dout
Column =B
Dout
CAS
Latency = 3
Burst Length = 4
Bank0
Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank-active command.
Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read
that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CLK
Command
Dout
out B3
Address
(A0-A10)
out B1 out B2
BS (A11)
ACTV
Row 0
Row 1
ACTV
READ
Column A
out A0 out B0
Bank0
Active
Bank1
Active
Bank0
Read
Bank1
Read
READ
Column B
Bank0
Dout
Bank1
Dout
CAS
Latency = 3
Burst Length = 4
EOL Product
HM5216165 Series
Data Sheet E0167H10
25
Write command to Write command interval:
Same bank, same ROW address: When another write command is executed at the same ROW address of
the same bank as the preceding write command, the second write can be performed after an interval of no less
than 1 cycle. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CLK
Command
Din
in B3
Address
(A0-A10)
in B1
in B2
BS (A11)
ACTV
Row
Column A
WRIT
WRIT
Column B
in A0
in B0
Bank0
Active
Column =A
Write
Column =B
Write
Burst Write Mode
Burst Length = 4
Bank0
Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
Different bank: When the bank changes, the second write can be performed after an interval of no less than
1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write
command has priority.
WRITE to WRITE Command Interval (different bank)
CLK
Command
Din
in B3
Address
(A0-A10)
in B1
in B2
BS (A11)
ACTV
Row 0
Row 1
ACTV
WRIT
Column A
in A0
in B0
Bank0
Active
Bank1
Active
Bank0
Write
Bank1
Write
WRIT
Column B
Burst Write Mode
Burst Length = 4
EOL Product
HM5216165 Series
Data Sheet E0167H10
26
Read command to Write command interval:
Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z before
data input.
READ to WRITE Command Interval (1)
CLK
Command
Dout
in B2
in B3
READ WRIT
in B0
in B1
High-Z
Din
CL=1
CL=2
CL=3
DQMU
/DQML
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CLK
Command
Dout
READ
WRIT
High-Z
Din
CL=1
CL=2
CL=3
DQMU
/DQML
High-Z
2 clock
High-Z
Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, DQMU/DQML must be set
High so that the output buffer becomes High-Z before data input.
EOL Product
HM5216165 Series
Data Sheet E0167H10
27
Write command to Read command interval:
Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
CLK
Command
Din
WRIT
READ
in A0
out B1
out B2
out B3
out B0
Dout
Column=A
Write
Column=B
Read
Column=B
Dout
CAS Latency
DQMU/DQML
Burst Write Mode
CAS
Latency = 1
Burst Length = 4
Bank0
WRITE to READ Command Interval (2)
CLK
Command
Din
WRIT
READ
in A0
out B1
out B2
out B3
out B0
Dout
Column=A
Write
Column=B
Read
Column=B
Dout
CAS Latency
in A1
DQMU/DQML
Burst Write Mode
CAS
Latency = 1
Burst Length = 4
Bank0
Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot
be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one cycle before the read command is executed (as in the case of the
same bank and the same address).
EOL Product
HM5216165 Series
Data Sheet E0167H10
28
Read command to Precharge command interval (same bank): When the precharge command is executed
for the same bank as the read command that preceded it, the minimum interval between the two commands is
one cycle. However, since the output buffer then becomes High-Z after the cycles defined by l
HZP
, there is a
possibility that burst read data output will be interrupted, if the precharge command is input during burst read.
To read all data by burst read, the cycles defined by l
EP
must be assured as an interval from the final data
output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CAS Latency = 1, Burst Length = 4
CLK
out A0
out A1
out A2
Command
Dout
READ
PRE/PALL
out A3
CL=1
l = 0 cycle
EP
CAS Latency = 2, Burst Length = 4
CLK
Command
Dout
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=2
l = -1 cycle
EP
CAS Latency = 3, Burst Length = 4
CLK
Command
Dout
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=3
l = -2 cycle
EP
EOL Product
HM5216165 Series
Data Sheet E0167H10
29
READ to PRECHARGE Command Interval (same bank): To stop output data
CAS Latency = 1, Burst Length = 1, 2, 4, 8
CLK
out A0
Command
Dout
READ
PRE/PALL
l
HZP
=1
High-Z
CAS Latency = 2, Burst Length = 1, 2, 4, 8
CLK
Command
Dout
READ
PRE/PALL
out A0
l
HZP
=2
High-Z
CAS Latency = 3, Burst Length = 1, 2, 4, 8
CLK
Command
Dout
READ
PRE/PALL
out A0
l
HZP
=3
High-Z
EOL Product
HM5216165 Series
Data Sheet E0167H10
30
Write command to Precharge command interval (same bank): When the precharge command is executed
for the same bank as the write command that preceded it, the minimum interval between the two commands is
1 cycle.
WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is
unfinished, the input data must be masked by means of DQMU and DQML for assurance of the cycle defined
by t
DPL
.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
CLK
Command
Din
WRIT
PRE/PALL
t
DPL
DQM
CLK
in A0
in A1
Command
Din
WRIT
PRE/PALL
t
DPL
DQM
Burst Length = 4 (To write all data)
CLK
in A0
in A1
in A2
Command
Din
WRIT
PRE/PALL
in A3
t
DPL
DQM
EOL Product
HM5216165 Series
Data Sheet E0167H10
31
Bank active command interval:
Same bank: The interval between the two bank-active commands must be no less than t
RC
.
In the case of different bank-active commands: The interval between the two bank-active commands must
be no less than t
RRD
.
Bank active to bank active for same bank
CLK
Command
Address
(A0-A10)
BS (A11)
Bank 0
Active
ACTV
ROW
ACTV
ROW
Bank 0
Active
t
RC
Bank active to bank active for different bank
CLK
Command
Address
(A0-A10)
BS (A11)
Bank 0
Active
Bank 1
Active
ACTV
ROW:0
ACTV
ROW:1
t
RRD
EOL Product
HM5216165 Series
Data Sheet E0167H10
32
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than t
RSA
.
CLK
Command
Address
(A0-A11)
Mode
Register Set
Bank
Active
MRS
ACTV
t
RSA
BS & ROW
CODE
EOL Product
HM5216165 Series
Data Sheet E0167H10
33
DQM Control
The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of
DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting
DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMU/DQML
to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal
reading operations continue. The latency of DQMU/DQML during reading is 2.
CLK
I/O (output)
out 0
out 1
l = 2 Latency
out 3
DOD
DQMU
/DQML
High-Z
Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be
written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the
previous data is held. The latency of DQMU/DQML during writing is 0.
CLK
I/O (input)
in 0
in 1
l = 0 Latency
in 3
;;
;
DID
DQMU
/DQML
EOL Product
HM5216165 Series
Data Sheet E0167H10
34
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto-
refresh command updates the internal counter every time it is executed and determines the banks and the
ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096
cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-
Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the
auto-refresh, an additional precharge operation by the precharge command is not required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held
Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-
refresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 s
interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately after exiting
from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in
normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval should be executed
within 64 ms immediately after exiting from and before entering into self refresh mode.
Others
Power-down mode: The synchronous DRAM enters power-down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power
down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM
exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal
refresh is not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous
DRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the synchronous DRAM terminates clock suspend
mode, and command input is enabled from the next cycle. For details, refer to the "CKE Truth Table".
Power-up sequence: During power-up sequence, the DQMU/DQML and the CKE must be set to High.
When 200 s has past after power on, all banks must be precharged using the precharge command. After t
RP
delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode
register.
EOL Product
HM5216165 Series
Data Sheet E0167H10
35
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V
SS
V
T
1.0 to +4.6
V
1
Supply voltage relative to V
SS
V
CC
1.0 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
P
T
1.0
W
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Note:
1. Respect to V
SS
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
V
CC
, V
CC
Q
3.0
3.6
V
1
V
SS
, V
SS
Q
0
0
V
Input high voltage
V
IH
2.0
4.6
V
1, 2
Input low voltage
V
IL
0.3
0.8
V
1, 3
Notes: 1. All voltage referred to V
SS
2. V
IH
(max) = 5.5 V for pulse width
5 ns
3. V
IL
(min) = 1.0 V for pulse width
5 ns
EOL Product
HM5216165 Series
Data Sheet E0167H10
36
DC Characteristics (Ta = 0 to 70C, V
CC
, V
CC
Q = 3.3 V 0.3 V, V
SS
, V
SS
Q = 0 V)
HM5216165
-10H
-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Test conditions
Notes
Operating current
I
CC1
--
130
--
105
mA
Burst length = 1
t
RC
= min
1, 2, 4
Standby current
(Bank Disable)
I
CC2
--
3
--
3
mA
CKE = V
IL
, t
CK
= min 5
--
2
--
2
mA
CKE = V
IL
CLK = V
IL
or V
IH
Fixed
6
--
50
--
41
mA
CKE = V
IH
,
NOP command
t
CK
= min
3
Active standby current
(Bank active)
I
CC3
--
7
--
7
mA
CKE = V
IL
, t
CK
= min,
I/O = High-Z
1, 2
--
51
--
43
mA
CKE = V
IH
,
NOP command
t
CK
= min,
I/O = High-Z
1, 2, 3
Burst operating current
(
CAS
latency = 1)
I
CC4
--
65
--
55
mA
t
CK
= min, BL = 4
1, 2, 4
(
CAS
latency = 2)
I
CC4
--
100
--
85
mA
(
CAS
latency = 3)
I
CC4
--
150
--
125
mA
Refresh current
I
CC5
--
85
--
70
mA
t
RC
= min
Self refresh current
I
CC6
--
2
--
2
mA
V
IH
V
CC
0.2
V
IL
0.2 V
7
Input leakage current
I
LI
10
10
10
10
A
0
Vin
V
CC
Output leakage current
I
LO
10
10
10
10
A
0
Vout
V
CC
I/O = disable
Output high voltage
V
OH
2.4
--
2.4
--
V
I
OH
= 2 mA
Output low voltage
V
OL
--
0.4
--
0.4
V
I
OL
= 2 mA
Notes: 1. I
CC
depends on output load condition when the device is selected. I
CC
(max) is specified at the
output open condition.
2. One bank operation.
3. Input signal transition is once per two CLK cycles.
4. Input signal transition is once per one CLK cycle.
5. After power down mode, CLK operating current.
6. After power down mode, no CLK operating current.
7. After self refresh mode set, self refresh current.
EOL Product
HM5216165 Series
Data Sheet E0167H10
37
Capacitance (Ta = 25C, V
CC
, V
CC
Q = 3.3 V 0.3 V)
Parameter
Symbol
Min
Max
Unit
Notes
Input capacitance (Address)
C
I1
2
5
pF
1, 3
Input capacitance (Signals)
C
I2
2
5
pF
1, 3
Output capacitance (I/O)
C
O
4
7
pF
1, 2, 3
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. DQMU/DQML = V
IH
to disable Dout.
3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 70C, V
CC
, V
CC
Q = 3.3 V 0.3 V, V
SS
, V
SS
Q = 0 V)
HM5216165
-10H
-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
System clock cycle time
(
CAS
latency = 1)
t
CK
30
--
36
--
ns
1
(
CAS
latency = 2)
t
CK
15
--
18
--
(
CAS
latency = 3)
t
CK
10
--
12
--
CLK high pulse width
t
CKH
3
--
4
--
ns
1
CLK low pulse width
t
CKL
3
--
4
--
ns
1
Access time from CLK
(
CAS
latency = 1)
t
AC
--
27
--
32
ns
1, 2
(
CAS
latency = 2)
t
AC
--
9
--
12
(
CAS
latency = 3)
t
AC
--
7.5
--
9
Data-out hold time
t
OH
3
--
3
--
ns
1, 2
CLK to Data-out low impedance
t
LZ
0
--
0
--
ns
1, 2, 3
CLK to Data-out high impedance
(
CAS
latency = 1)
t
HZ
--
13
--
15
ns
1, 4
(
CAS
latency = 2, 3)
t
HZ
--
7
--
9
Data-in setup time
t
DS
2
--
3
--
ns
1
Data in hold time
t
DH
1
--
1
--
ns
1
Address setup time
t
AS
2
--
3
--
ns
1
Address hold time
t
AH
1
--
1
--
ns
1
CKE setup time
t
CES
2
--
3
--
ns
1, 5
CKE setup time for power down exit
t
CESP
2
--
3
--
ns
1
CKE hold time
t
CEH
1
--
1
--
ns
1
EOL Product
HM5216165 Series
Data Sheet E0167H10
38
AC Characteristics (Ta = 0 to 70C, V
CC
, V
CC
Q = 3.3 V 0.3 V, V
SS
, V
SS
Q = 0 V) (cont)
HM5216165
-10H
-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Command (
CS
,
RAS
,
CAS
,
WE
, DQM)
setup time
t
CS
2
--
3
--
ns
1
Command (
CS
,
RAS
,
CAS
,
WE
, DQM)
hold time
t
CH
1
--
1
--
ns
1
Ref/Active to Ref/Active command period
t
RC
90
--
100
--
ns
1
Active to precharge command period
t
RAS
60
120000 70
120000 ns
1
Active to precharge on full page mode
t
RASC
--
120000 --
120000 ns
1
Active command to column command
(same bank)
t
RCD
30
--
30
--
ns
1
Precharge to active command period
t
RP
30
--
30
--
ns
1
Write recovery or data-in to precharge lead
time
t
DPL
15
--
15
--
ns
1
Active (a) to Active (b) command period
t
RRD
20
--
20
--
ns
1
Transition time (rise to fall)
t
T
1
5
1
5
ns
Refresh period
t
REF
--
64
--
64
ms
Notes: 1. AC measurement assumes t
T
= 1 ns. Reference level for timing of input signals is 1.40 V.
2. Access time is measured at 1.40 V. Load condition is CL = 50 pF with current source.
3. t
LZ
(max) defines the time at which the outputs achieves the low impedance state.
4. t
HZ
(max) defines the time at which the outputs achieves the high impedance state.
5. t
CES
defines CKE setup time to CKE rising edge except power down exit command.
Test Conditions
Input and output timing reference levels: 1.4 V
Input waveform and output load: See following figures
t
T
2.8 V
V SS
Input
80%
20%
t
T
500
+1.4 V
I/O
CL
Output
EOL Product
HM5216165 Series
Data Sheet E0167H10
39
Relationship Between Frequency and Minimum Latency
HM5216165
Parameter
-10H
-12
Frequency (MHz)
t
CK
(ns)
Symbol
100
10
66
15
33
30
83
12
55
18
28
36
Notes
Active command to column command
(same bank)
t
RCD
3
2
1
3
2
1
1
Active command to active command
(same bank)
t
RC
9
6
3
9
6
3
= [t
RAS
+ t
RP
]
1
Active command to precharge command
(same bank)
t
RAS
6
4
2
6
4
2
1
Precharge command to active command
(same bank)
t
RP
3
2
1
3
2
1
1
Write recovery or data-in to precharge
command (same bank)
t
DPL
2
1
1
2
1
1
1
Active command to active command
(different bank)
t
RRD
2
2
1
2
2
1
1
Self refresh exit time
I
SREX
2
2
2
2
2
2
2
Last data in to active command
(Auto precharge, same bank)
I
APW
5
3
2
5
3
2
= [t
DPL
+ t
RP
]
Self refresh exit to command input
I
SEC
9
6
3
9
6
3
= [t
RC
]
Precharge command to high impedance
(
CAS
latency = 3)
I
HZP
3
3
3
3
3
3
(
CAS
latency = 2)
I
HZP
--
2
2
--
2
2
(
CAS
latency = 1)
I
HZP
--
--
1
--
--
1
Last data out to active command (auto
precharge) (same bank)
I
APR
1
1
1
1
1
1
Last data out to precharge
(early precharge)
(
CAS
latency = 3)
I
EP
2
2
2
2
2
2
(
CAS
latency = 2)
I
EP
--
1
1
--
1
1
(
CAS
latency = 1)
I
EP
--
--
0
--
--
0
Column command to column command
I
CCD
1
1
1
1
1
1
Write command to data in latency
I
WCD
0
0
0
0
0
0
DQM to data in
I
DID
0
0
0
0
0
0
DQM to data out
I
DOD
2
2
2
2
2
2
CKE to CLK disable
I
CLE
1
1
1
1
1
1
EOL Product
HM5216165 Series
Data Sheet E0167H10
40
Relationship Between Frequency and Minimum Latency (cont)
HM5216165
Parameter
-10H
-12
Frequency (MHz)
t
CK
(ns)
Symbol
100
10
66
15
33
30
83
12
55
18
28
36
Notes
Register set to active command
t
RSA
1
1
1
1
1
1
CS to command disable
I
CDD
0
0
0
0
0
0
Power down exit to command input
I
PEC
1
1
1
1
1
1
Burst stop to output valid data hold
(
CAS
latency = 3)
I
BSR
2
2
2
2
2
2
(
CAS
latency = 2)
I
BSR
--
1
1
--
1
1
(
CAS
latency = 1)
I
BSR
--
--
0
--
--
0
Burst stop to output high impedance
(
CAS
latency = 3)
I
BSH
3
3
3
3
3
3
(
CAS
latency = 2)
I
BSH
--
2
2
--
2
2
(
CAS
latency = 1)
I
BSH
--
--
1
--
--
1
Burst stop to write data ignore
I
BSW
0
0
0
0
0
0
Notes: 1. t
RCD
to t
RRD
are recommended value.
2. When self refresh exit is executed, CKE should be kept "H" longer than l
SREX
from exit cycle.
EOL Product
HM5216165 Series
Data Sheet E0167H10
41
Timing Waveforms
Read Cycle
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
CLK
CKE
CS
t
RAS
t
RCD
t
CH
t
CS
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
RAS
CAS
WE
A11
;
;
;
;
;
;
;;
;;
;
;;
;;
;
;;
;
;
;
;;
;
;
;
;
;
;;
;
;
;
;;
;
;
;
;
;
;
;;
;
;;
A10
Address
DQMU
/DQML
I/O(input)
I/O(output)
;
;
;
t
CH
t
CS
t
CKH
t
t
CK
t
AC
t
AC
CKL
t
AC
t
OH
t
OH
t
HZ
t
OH
t
RP
t
RC
Burst length = 4
Bank0 Access
= V
IH
or V
IL
;
;;
;
;
;
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
AH
t
AS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AC
;
;
t
LZ
V
IH
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
42
Write Cycle
CLK
CKE
CS
t
RAS
t
RCD
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAS
CAS
WE
A11
;
;
;
;
;
;
;
A10
Address
DQMU
/DQML
I/O(input)
I/O(output)
t
CH
t
CS
t
CKH
t
t
CK
t
DH
t
DH
CKL
t
DH
t
DH
t
DS
t
DS
t
DS
t
DS
t
RP
t
RC
t
RWL
Bank 0
Write
t
CH
t
CS
Bank 0
Active
Bank 0
Precharge
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
AS
t
CH
t
CS
t
AH
t
AS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
CH
t
CS
t
AH
t
AS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
t
AH
t
AS
;;
;
;
;
;
;
;;
;
;
;
;
;;
;
;;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;;
;
;
;;
;
;
;
;
;
;;
;
;;
;;
;
;
;;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;;
;;
;
V
IH
Burst length = 4
Bank0 Access
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
43
Mode Register Set Cycle
;
;
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
CKE
CS
RAS
CAS
WE
A11(BS)
Address
DQMU
/DQML
I/O(input)
I/O(output)
;
;
;
;;
;
;;
;;
;;
;;
;;
;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;;
;
;;
;
;
;
;;
;
;
;
;;
;;
;
;
High-Z
b
b+3
b'
b'+1
b'+2
b'+3
t
valid
C: b'
RSA
code
t RCD
t RP
Precharge
If needed
Mode
register
Set
Bank 1
Active
Bank 1
Read
;;
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
;;
;
;;
;
;
;;
;
;;
;
;
;
;
;;
;
;
;
;
;
;
;;
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
R: b
C: b
;
;;
;
;
;;
;
;
;
;;
;
;
;
;
;;
;
Output mask
V
IH
t
RCD
= 3
CAS
Latency = 3
Burst Length = 4
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
44
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
;
;
;
;
;
;
R:a
C:a
R:b
C:b
C:b'
C:b"
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
CLK
A11(BS)
;
;
;
;
;
;;
;
;
;
;
;;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
R:a
C:a
R:b
C:b
C:b'
C:b"
;
;
;
;
;
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
;
;
;
;
;
;
;;
;
;
;
;
;
;
;
;;
;
;
;
;
;
;
;
;
;
;;
;
;
;
;
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
;
;
;
;;
;
;;
;
;
;
;
;;
;
;
;
;
;
;;
;
;;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 1
Read
Bank 1
Read
Bank 1
Read
Bank 0
Precharge
Bank 1
Precharge
Bank 0
Active
Bank 0
Write
Bank 1
Active
Bank 1
Write
Bank 1
Write
Bank 1
Write
Bank 0
Precharge
Bank 1
Precharge
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
A11(BS)
High-Z
High-Z
;;
;
;;
;
;
;;
;;
;
;;
;
;
V
IH
V
IH
Read cycle
RAS
-
CAS
delay = 3
CAS
Latency = 3
Burst Length = 4
= V
IH
or V
IL
;
Write cycle
RAS
-
CAS
delay = 3
CAS
Latency = 3
Burst Length = 4
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
45
Read/Single Write Cycle
;;
;
;
;;
;;
;
;
;
;
;
;
;
;;
;;
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
;
;
;
;
;
;
;
;
;
;
;
;
R:a
C:a
R:b
C:a'
;
;
;
;
;
;
;
;
;
;
;
;
;
R:a
C:a
C:a
;;
;
;
;
;
;
;
;
a
a
a
a
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;;
;;
;
;
;
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 0
Write
Bank 0
Precharge
Bank 1
Precharge
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
;
;
;
;
;
;
;
;
;;
R:b
Bank 1
Active
;
;
;
;
;
;
;
;;
;
;;
;
;
;;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
C:a
Bank 0
Read
a
a+1 a+2 a+3
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Bank 0
Write
Bank 0
Write
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
CLK
A11(BS)
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
A11(BS)
;
;;
;;
;
;
;
;
;;
C:b
b
c
a+1
a+3
a+1 a+2 a+3
C:c
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
V
IH
V
IH
Read/Single write
RAS
-
CAS
delay = 3
CAS
Latency = 3
Burst Length = 4
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
46
Read/Burst Write Cycle
;;
;
;
;;
;;
;
;
;
;
;
;
;
;;
;;
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
;
;
;
;
;
;
;
;
;
;
;
;
R:a
C:a
R:b
C:a'
;
;
;
;
;
;
;
;
;
;
;
;
;
R:a
C:a
C:a
;;
;
;
;
;
;
;
;
a
a
a
a
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;;
;;
;
;
;
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 0
Write
Bank 0
Precharge
Bank 1
Precharge
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
;
;
;
;
;
;
;
;
;;
R:b
Bank 1
Active
;
;
;
;
;
;
;
;;
;
;;
;
;
;;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
C:a
Bank 0
Read
a
a+1 a+2 a+3
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Bank 0
Write
Bank 0
Write
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
CLK
A11(BS)
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
A11(BS)
;
;;
;;
;
;
;
;
;;
C:b
b
c
a+1
a+3
a+1 a+2 a+3
C:c
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
V
IH
V
IH
Read/Single write
RAS
-
CAS
delay = 3
CAS
Latency = 3
Burst Length = 4
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
47
Full Page Read/Write Cycle
High-Z
0
1
2
3
4
5
6
7
8
9
260 261 262 263 264 265 266 267 268 269
;
;
;
;
;
R:a
C:a
R:b
a-2
a-1
a
a+1
a+2
;
;
;
;
;
;
;
;
;
;
;
;
;
R:a
C:a
R:b
High-Z
;
a
a+1
a+2
a+3
a+1
a+2
a+3
a+4
a+5
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;;
;
;
;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Bank 0
Active
Bank 0
Read
Bank 1
Active
Burst stop
Bank 1
Precharge
Bank 0
Active
Bank 0
Write
Bank 1
Active
Burst stop
Bank 1
Precharge
a
a+1
a+2
a+3
a+3
a+4
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
a+6
a+5
;;
;
;
;
;
;
;
;
;;
;;
;;
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
CLK
A11(BS)
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
A11(BS)
a+4
;
;;
;
;;
V
IH
V
IH
a+5
Read cycle
RAS
-
CAS
delay = 3
CAS
Latency = 3
Burst Length = full page
= V
IH
or V
IL
;;
Write cycle
RAS
-
CAS
delay = 3
CAS
Latency = 3
Burst Length = full page
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
48
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
CS
CAS
WE
A11(BS)
Address
DQMU
/DQML
I/O(input)
I/O(output)
;
;;
;
;
;;
;
;;
;
;;
;
;
;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
High-Z
RP
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;;
;
;;
;
;
Precharge
If needed
Auto Refresh
Active
Bank 0
t
RC
t
RC
t
Auto Refresh
Read
Bank 0
;;
;
;
;;
;
;
R:a
C:a
A10=1
RAS
;
;
;
;
;;
;
;;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;;
;
;;
;;
;;
;
;;
;
;
;
;;
;
;
;
;;
;
;
;
;;
;
;;
;
a
a+1
V
IH
Refresh cycle and
Read cycle
RAS
-
CAS
delay=2
CAS
latency=2
Burst length=4
= V
IH
or V
IL
;
Self Refresh Cycle
CLK
CKE
CS
RAS
CAS
WE
A11(BS)
Address
DQMU
/DQML
I/O(imput)
t
RP
High-Z
Self refresh cycle
RAS-CAS delay = 3
CAS Latency = 3
Burst Length = 4
t
RC
I/O(output)
CKE Low
I
SREX
A10=1
Precharge command
If needed
Self refresh entry
command
Self refresh exit
ignore command
or No operation
Next
clock
enable
Next
clock
enable
Auto
refresh
Self refresh entry
command
=V
IH
or V
IL
CKE High
EOL Product
HM5216165 Series
Data Sheet E0167H10
49
Clock Suspend Mode
;
;
;
;
;
;
;
;;
;;
;;
;
;;
;;
;
;;
;
;
;
;
;
;
;
;
;
;
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
;
;;
;;
R:a
C:a
R:b
a
a+1 a+2
a+3
b
b+1 b+2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;;
;
;
R:a
C:a R:b
C:b
;
;
;
;
;
;
;
;
;
;
a
a+1 a+2
b
b+1 b+2 b+3
;
;
;
;
;
;
;
;
;
;
;
;
;
C:b
;;
;
;
;
;
;
;;
;
;
;
Bank0
Active
Active clock
suspend start
Active clock
supend end
Bank0
Read
Bank1
Active
Read suspend
start
Read suspend
end
Bank0
Precharge
Bank1
Read
Earliest Bank1
Precharge
Bank0
Write
Bank0
Active
Active clock
suspend start
Active clock
suspend end
Bank1
Active
Write suspend
start
Write suspend
end
Bank1
Write
Bank0
Precharge
Earliest Bank1
Precharge
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
b+3
;;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;;
;;
;
;
;
;;
;;
;
;;
;;
;
;
;
;
;
;;
;
;
;
;
;
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
CLK
A11(BS)
CKE
RAS
CS
CAS
WE
Address
DQMU
/DQML
I/O
(input)
I/O
(output)
A11(BS)
a+3
High-Z
High-Z
;
;
;
;
;;
;
;
;;
;
;;
;
;;
;
;;
;;
;;
;;
;;
;
;;
;
;
;
;;
;;
;
;;
;;
;
;
t
CESP
t
CEH
t
CES
Read cycle
RAS
-
CAS
delay=2
CAS
latency=2
Burst length=4
= V
IH
or V
IL
;
Write cycle
RAS
-
CAS
delay=2
CAS
latency=2
Burst length=4
= V
IH
or V
IL
;
EOL Product
HM5216165 Series
Data Sheet E0167H10
50
Power Down Mode
CLK
CKE
CS
RAS
CAS
WE
A11(BS)
Address
DQMU
/DQML
I/O(input)
I/O(output)
;;
;;
;
;
;;
;
;
;
;;
;
;
;;
;
;
;
;
;
;
;
;
;;
;
;;
;;
;
;
;
;;
;;
;;
;
;
;;
;
;
;
;;
;;
;
;;
;
;
;
;
;
;
;;
;
;
;;
;
;;
;;
;;
;
;
;;
;
;
;;
;;
;
;
;;
;
;;
;
;
;
;;
;
;
;
;
;
;
;
Precharge command
If needed
Power down entry
Active Bank 0
Power down
mode exit
;
;;
;
;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CKE Low
R: a
;;
;
;
;
A10=1
RP
t
;
;;
;;
;
High-Z
;
Power down cycle
RAS
-
CAS
delay=3
CAS
latency=2
Burst length=4
= V
IH
or V
IL
;
Power Up Sequence
CLK
CKE
CS
RAS
CAS
WE
Address
DQMU
/DQML
I/O
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
V
IH
V
IH
Valld
code
Valld
High-Z
t
RP
All banks
Precharge
Auto Refresh
t
RC
Auto Refresh
t
RC
Mode register
Set
t
RSA
Bank active
If needed
EOL Product
HM5216165 Series
Data Sheet E0167H10
51
Package Dimensions
HM5216165TT Series (TTP-50D)
0.13
M
0.10
0.80
50
26
1
25
20.95
21.35 Max
0.27
0.07
1.20 Max
10.16
1.15 Max
0.13
0.05
11.76
0.20
0
5
0.145
0.05
0.50
0.10
0.68
0.80
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-50D
--
--
0.50 g
0.25
0.05
0.125
0.04
Unit: mm
Dimension including the plating thickness
Base material dimension
EOL Product
HM5216165 Series
Data Sheet E0167H10
52
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any
third party's patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information contained in this
document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage
when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as
fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury,
fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
Elpida Memory, Inc. 2001
C