* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

GENERAL DESCRIPTION

EM73982 is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 372-nibble
RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernal
function. EM73982 also contains 5 interrupt sources, 3 I/O ports (including 1 input port and 2 bidirection ports),
LCD display (40x8), built-in sound generator and speech synthesizer.
Except low-power consumption and high speed, EM73982 also have a sleep mode for power saving function.
EM73982 is suitable for appliaction in many fields, for example : family appliance, consumer products, hand
held games and the toy controller ... etc.

FEATURES

· Operation voltage

: 2.4V to 5.5V.

· Clock source

: Single clock system for both RC and Crystal are available by mask option.

External clock and internal clock are available by mask option.

· Oscillation frequency : 480K, 1M, 2M and 4M Hz are available by mask option.
· Instruction set

: 109 powerful instructions.

· Instruction cycle time : Up to 2us for 4 MHz.
· ROM capacity

: 16384 X 8 bits.

· RAM capacity

: 372 X 4 bits.

· Input port

: 1 port (P0.0-P0.3) and sleep/hold releasing function are available by mask option.

(each input pin is pull-up and pull-down resistor available by mask option).

· Bidirection port

: 2 ports (P4, P8). P4.0 and SOUND is available by mask option. P8(0..3) and sleep/

hold releasing function are available by mask option.

· 12-bit timer/counter

: Two 12-bit timer/counters are programmable for timer, event counter and pulse width

measurement.

· Built-in time base counter : 22 stages.
· Subroutine nesting

: Up to 13 levels.

· Interrupt

: External . . . . . 1 input interrupt sources.

Internal . . . . . . 2 Timer overflow interrupts.

1 Time base interrupt.
1 Speech ending interrupt.

· LCD driver

: 40 X 8 dots, 1/8 duty, LCD bias is 1/4 and modified 1/4 available by mask option, LCD

bias resistor is 20K X 5 and 10K X 5 available by mask option.

· Sound effect

: Tone generator, random generator and volume control.

· Speech synthesizer

: Speech data ROM . . 24K bytes.

Sample rate . . . . . . . 4K, 5K, 8K, 10K, 12K, 15K, 20K programmable.

· Power saving function : Sleep mode and Hold mode.
· Package type :

EM73982H

Chip form

68 pins.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

FUNCTION BLOCK DIAGRAM

PIN DESCRIPTIONS

Symbol

Pin-type

Function

Power supply (+)

Power supply (-)

RESET

RESET-A

System reset input signal, low active
mask option :

none
pull-up

XIN/CLK

OSC-A/OSC-C Crystal/RC or external clock source connecting pin

XOUT/NC

OSC-A/OSC-C Crystal connecting pin

P0.(0..3)/WAKEUP0..3

INPUT-B

4-bit input port with Sleep/Hold releasing function

mask option :

wakeup enable, pull-up
wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none

P4.0/SOUND

I/O-O

1-bit bidirection I/O port or inverse sound effect output
mask option :

SOUND enable, push-pull, high current PMOS
SOUND disable, open-drain
SOUND disable, push-pull, high current PMOS
SOUND disable, push-pull, low current PMOS

P4(1..3)

I/O-N

3-bit bidirection I/O port with high current source.

mask option :

open-drain

push-pull, high current PMOS
push-pull, low current PMOS

P8.0/WAKEUPA

I/O-L

2-bit bidirection I/O port with external interrupt sources input only for

P8.2(INT0)/WAKEUPC

P8.2 and Sleep/Hold releasing function

mask option :

wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain

Interrupt

Control

Time

Base

Timer/Counter

(TA,TB)

System Control

Instruction Decoder

Instruction Register

ROM

Data Bus

Reset

Control

Clock

Generator

Timing

Generator

Sleep Mode

Control

Data pointer

ACC

ALU

Flag

Stack pointer

Stack

ROM

I/O Control

P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3

P4.0/SOUND

P4.1

P4.2

P4.3

P8.0/WAKEUPA

P8.1(TRGB)/WAKEUPB

P8.2(INT0)/WAKEUPC

P8.3(TRGA)/WAKEUPD

RESET

XIN/CLK XOUT/NC

SOUND GEN.

LCD Driver

COM0~COM7

SOUND

SEG0~SEG39

Voice

Synthesizer

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

FUNCTION DESCRIPTIONS

P8.1(TRGB)/WAKEUPB I/O-L

2-bit bidirection I/O port with time/counter A,B external input and Sleep

P8.3(TRGA)/WAKEUPD

/Hold releasing function

mask option :

wakeup enable, push-pull
wakeup disable, push-pull
wakeup disable, open-drain

Built-in Speech synthesizer analog signal output

SOUND

Built-in sound effect output

COM0~COM7

LCD common output pins

SEG0~SEG39

LCD segment output pins

TEST

Test pin must be floating

Symbol

Pin-type

Function

ACCUMULATOR

Accumulator is a 4-bit data register for temporary data. For the arithematic, logic and comparative opertion
.., ACC plays a role which holds the source data and result.

FLAGS

There are three kinds of flag, CF (Carry flag), ZF (Zero flag), SF (Status flag), these 3 1-bit flags are affected
by the arithematic, logic and comparative .... operation.
All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction executed.

(1) Carry Flag ( CF )

The carry flag is affected by following operation:
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1",

in another word, if the operation has no carry-out, CF will be "0".

b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow, in the CF

will be "0", in another word, if no borrow-in, CF will be "1".

c. Comparision: CF is as a borrow-in indicator for Comparision operation as the same as subtraction

operation.

d. Rotation: CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : For TFCFC instruction, the content of CF sends into SF then clear itself "0".

For TTSFC instruction, the content of CF sends into SF then set itself "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1",
otherwise, the ZF will be "0".

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

ZF CF SF

ALU

DATA BUS

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status.

a. SF is initiated to "1" for reset condition.

b. Branch instruction is decided by SF, when SF=1, branch condition will be satisified, otherwise,

branch condition will not be satisified by SF = 0.

PROGRAM EXAMPLE:
Check following arithematic operation for CF, ZF, SF

LDIA #00h;

LDIA #03h;

ADDA #05h;

ADDA #0Dh;

ADDA #0Eh;

ALU

The arithematic operation of 4 - bit data is performed in ALU unit. There are 2 flags can be affected by
the result of ALU operation, ZF and SF. The operation of ALU can be affected by CF only.

ALU STRUCTURE

ALU supported user arithematic operation function, including : addition, subtraction and rotaion.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

ALU FUNCTION

(1) Addition:

For instruction ADDAM, ADCAM, ADDM #k, ADD #k,y .... ALU supports addition function.
The addition operation can affect CF and ZF. For addition operation, if the result is "0", ZF will be "1",
otherwise, not equal "0", ZF will be "0". When the addition operation has a carry-out, CF will be "1",
otherwise, CF will be "0".

EXAMPLE:

Operation

Carry

Zero

3+4=7

7+F=6

0+0=0

8+8=0

(2) Subtraction:

For instruction SUBM #k, SUBA #k, SBCAM, DECM... ALU supports user subtraction function. The
subtraction operation can affect CF and ZF, For subtraction operation, if the result is negative, CF will
be "0", it means a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result
of subtraction operation is "0", the ZF will be "1", otherwise, ZF will be "1".

EXAMPLE:

Operation

Carry

Zero

8-4=4

7-F= -8(1000)

9-9=0

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

ACC

MSB

LSB

3 2 1 0

H REGISTER

3 2 1 0

L REGISTER

ACC

MSB

LSB

(3) Rotation:

There are two kinds of rotation operation, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value to left, shift the CF value into the LSB bit of Acc and the shift out data
will be hold in CF.

RRCA instruction operation rotates Acc value to right, shift the CF value into the MSB bit of Acc and the
shift out data will be hold in CF.

PROGRAM EXAMPLE: To rotate Acc right and shift a "1" into the MSB bit of Acc.

TTCFS; CF

RRCA; rotate Acc right and shift CF=1 into MSB.

HL REGISTER

HL register are two 4-bit registers, they are used as a pair of pointer for the address of RAM memory and also
2 independent temporary 4-bit data registers. For some instruction, L register can be a pointer to indicate the
pin number (Port4).

HL REGISTER STRUCTURE

HL REGISTER FUNCTION

(1) For instruction : LDL #k, LDH #k, THA, THL, INCL, DECL, EXAL, EXAH, HL register used as a

temporary register.

PROGRAM EXAMPLE:

Load immediate data "5h" into L register, "Dh" into H register.

LDL #05h;
LDH #0Dh;

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

(2) For instruction LDAM, STAM, STAMI .., HL register used as a pointer for the address of RAM memory.

PROGRAM EXAMPLE: Store immediate data #Ah into RAM of address 35h.

LDL #5h;
LDH #3h;
STDMI #0Ah; RAM[35]

Ah, LR

(3) For instruction : SELP, CLPL, TFPL, L regieter be a pointer to indicate the bit of I/O port.

When LR = 0 indicate P4.0

PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"

LDL #00h;
SEPL ; P4.0

STACK POINTER (SP)

Stack pointer is a 4-bit register which stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is accepted, the SP will be decreased one automatically, in another word, if
returning from a subroutine, the SP will be increased one.
The data transfer between ACC and SP is by instruction of "LDASP" and "STASP" at RAM bank0.

DATA POINTER (DP)

Data pointer is a 12-bit register which stores the address of ROM can indicate the ROM code data
specified by user (refer to data ROM).

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

SCALL, subroutine call entry address

Data table for
[LDAX],[LDAXI]
instruction

Subroutine call entry address
designated by [LCALL a]
instruction

PROGRAM ROM ( 16K X 8 bits ) for EM73982

16 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of program ROM can be divided into 6 parts.
1. Address 0000h: Reset start address.
2. Address 0002h - 000Ch : 5 kinds of interrupt service routine entry addresses.
3. Address 000Eh-0086h : SCALL subroutine entry address, only available at 000Eh,0016h,001Eh,0026h,

002Eh, 0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh,
0086h.

4. Address 0000h - 07FFh : LCALL subroutine entry address.
5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program region.
6. Address 1000h - 1FFFh (bank 1, 2, 3) : Only these area could be used as program ROM Data area which used

by LDAX, LDAXI instruction.

address Bank 0 :

0000h

Reset start address

0002h

INT0; interrupt service routine entry address

0004h

Reserved

0006h

TRGA

0008h

TRGB

000Ah

TBI

000Ch

SPI

000Eh
0086h

07FFh
0800h

0FFFh

1000h

Bank 1

1FFFh

Bank 2

Bank 3

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

User's program and fixed data are stored in the program ROM. User's program is according the PC value
to send next executed instruction code.
The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits each bank.
The bank of the program ROM is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC
and P3 are initialized to "0" during reset.
When P3(1..0)=00B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the the bank0 and
bank2 will be selected. P3(1..0)=01B, the bank0 and bank3 will be selected.

Address

P3=xx00B

P3=xx01B

P3=xx10b

0000h

:
:

Bank0

0FFFh

1000h

:
:

Bank1

Bank2

Bank3

1FFFh

PROGRAM EXAMPLE:

BANK 0

START:

:
:
:
LDIA

#00H

; set program ROM to bank1

OUTA P3
B

XA1

XA :

:
:
LDIA

#01H

; set program ROM to bank2

OUTA P3
B

XB1

XB :

:
:
LDIA

#02H

; set program ROM to bank3

OUTA P3
B

XC1

XC :

:
:
B

XD :

:
:
:

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- -

BANK

XA1 :

:
:
B

XA2 :

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

XA2

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 2

XB1 :

:
:
B

XB2 :

:
B

XB2

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 3

XC1 :

:
:
B

XC2 :

:
B

XC2

Fixed data can be read out by table-look-up instruction. Table-look-up instruction is depended on the Data
Pointer (DP) to indicate the ROM address, then to get the ROM code data :

LDAX

Acc

ROM[DP]

LDAXI

Acc

ROM[DP]

,DP+1

DP is a 12-bit data register which can store the program ROM address to be the pointer for the ROM code data.
First, user load ROM address into DP by instruction "STADPL, STADPM, STADPH", then user can get the
lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction "LDAXI".
To access DP (LDADPL, LDADPM, LDADPH, STADPL, STADPM, STADPH), user must switch RAM
at BANK0.

PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.

LDIA #07h;
STADPL

; [DP]

07h

STADPM

; [DP]

07h

STADPH

; [DP]

07h, Load DP=777h

:
LDL #00h

;

LDH #03h

;

OUT #00H,P3

;

LDAX

; ACC

STAMI

; RAM[30]

LDAXI

; ACC

STAM

; RAM[31]

;
ORG 1777h
DATA 56h

;

DATA RAM ( 372-nibble )

There is total 372 - nibble data RAM from address 000 to 17Fh
Data RAM includes 3 parts: zero page region, stacks and data area.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

ZERO- PAGE:

From 000h to 00Fh is the location of zero-page. It is used as the pointer in zero -page addressing mode for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To wirte immediate data "07h" to address "003h" of RAM and to clear bit 2 of RAM.

STD #07h, 03h ; RAM[03]

07h

CLR 0Eh,2 ; RAM[0Eh]

STACK:

There are 13 - level (maximum) stack for user using for subroutine (including interrupt and CALL). User
can assign any level to be the starting stack by giving the level number to stack pointer (SP).
When user using any instruction of CALL or subroutine, before entry the subroutine, the previous PC address
will be saved into stack until return from those subroutines, the PC value will be restored by the data saved
in stack.

DATA AREA:

Except the special area used by user, the whole RAM can be used as data area for storing and loading general
data.

ADDRESSING MODE

The 372 nibble data memory consists two banks (bank 0 and bank 1). There are 244x4 bits (address
000h~0F3h) on bank 0 and 128x4 bits (address 100h~17Fh) on bank 1.

Increment

Address

020h - 02Fh

0C0h - 0CFh

0D0h - 0DFh

0E0h - 0EFh

Level 0

Level 4

Level 8

Level 12

Level 1

Level 5

Level 9

Level 2

Level 6

Level 10

Level 3

Level 7

Level 11

Increment

Zero-page

000h - 00Fh

010h - 01Fh

0F0h - 0F3h

:
:
:

110h - 11Fh

160h - 16Fh

170h - 17Fh

100h - 10Fh

:
:
:

Bank 0

Bank 1

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

P9.3

instruction field

RAM address

xxxx xxxx

instruction field

RAM address

yyyy

0000 yyyy

There are three addressing modes in the data memory :

(1) Indirect addressing mode:

The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected.
When P9.3 is set to "1", the bank 1 is selected. The address in the bank are specified by the HL registers.

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".

SEP P9,3 ; P9.3

LDL #3h

; LR

LDH #4h

; HR

LDAM

; Acc

RAM[134h]

CLP P9,3 ; P9.3

LDL #2h

; LR

LDH #3h

; HR

STAM

; RAM[023h]

Acc

(2) Direct addressing mode:

The bank is selected by P9.3. When P9.3 is cleared to "0", the bank 0 is selected.
When P9.3 is set to "1", the bank 1 is selected. The address in the bank are directly specified by 8 bits of the
second byte in the instruction field.

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".

SEP P9,3 ; P9.3

LDA 43h

; Acc

RAM[134h]

CLP P9,3 ; P9.3

STA 23h

; RAM[023h]

Acc

(3) Zero-page addressing mode:

The zero-page is the bank 0 (address 000h~00Fh). The address are the lower 4 bits of the second byte in the
instruction field.

PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".

STD #0Fh, 05h ; RAM[05h]

0Fh

P9.3

RAM address

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

PROGRAM COUNTER

Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the
instruction of program ROM.
For a 8K - byte size ROM, PC can indicate address form 0000h - 1FFFh, for BRANCH and CALL instrcutions,
PC is changed by instruction indicating.

(1) Branch instruction:

SBR a

SBR a
Object code: 00aa aaaa
Condition: SF=1; PC

12-6.a

(branch condition satisified)

PC Hold original PC value+1

SF=0; PC

PC +1 (branch condition not satisified)

PC Original PC value + 1

LBR a

LBR a
Object code: 1100 aaaa aaaa aaaa
Condition: SF=1; PC

12.a

(branch condition satisified)

Hold

a a

SF=0; PC

PC +2 (branch condition not satisified)

PC Original PC value + 2

SLBR a

SLBR a
Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)

0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)

Condition: SF=1; PC

a (branch condition satisified)

PC a

SF=0 ; PC

PC + 3 (branch condition not satisified)

Original PC value + 3

(2) Subroutine instruction:

SCALL a

SCALL a
Object code: 1110 nnnn
Condition : PC

a ; a=8n+6 ; n=1..Fh ; a=86h, n=0

PC 0

LCALL a

LCALL a
Object code: 0100 0aaa aaaa aaaa
Condition: PC

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

PC 0

RET

RET
Object code: 0100 1111
Condition: PC

STACK[SP]; SP + 1

The return address stored in stack

RT I

RT I
Object code: 0100 1101
Condition : FLAG. PC

STACK[SP]; EI

1; SP + 1

The return address stored in stack

(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC,The interrupt vectors are as following:

INT0

INT0 (External interrupt from P8.2)

PC 0

TRGA

TRGA (Timer A overflow interrupt)

PC 0

TRGB

TRGB (Time B overflow interrupt)

PC 0

TBI

TBI (Time base interrupt)

PC 0

SPI

SPI (Speech ending interrupt)

PC 0

(4) Reset operation:

PC 0

(5) Other operations:

For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

CLOCK AND TIMING GENERATOR

The clock generator is supported by a single clock system, the clock source comes from crystal (resonator)
or RC oscillation is decided by mask option, the working frequency range is 480 K Hz to 4 MHz.

CLOCK AND TIMING GENERATOR STRUCTURE

The clock generator connects outside compoments (crystal or resonator by XIN and XOUT pin for crystal
osc. type, Resistor and capacitor by CLK pin for RC osc type, these two type is decided by mask option).
The clock generator generates a basic system clock "fc".
When CPU sleeping, the clock generator will be stoped until the sleep condition released.
The system clock control generates 4 basic phase signals (S1, S2, S3, S4) and system clock.

CLOCK AND TIMING GENERATOR FUNCTION

The frequency of fc is the oscillation frequency for XIN, XOUT by crystal ( resonator) or for CLK by RC osc.
When CPU sleeps, the XOUT pin will be in "high" state. When user choose RC osc, XOUT pin is no used.
The instruction cycle equal 8 basic clock fc.

1 instructure cycle = 8 / fc

TIMING GENERATOR AND TIME BASE

The timing generator produces the system clock from basic clock pulse.
1 instruction cycle = 8 basic clock pulses
There are 22 stages time base.

When working in the single clock mode, the timebase clock source is come from fc.

Time base provides basic frequency for following function:
1. TBI (time base interrupt).
2. Timer/counter, internal clock source.
3. Warm-up time for sleep - mode releasing.

XIN/CLK

XOUT

Crystal connection

XIN/CLK

XOUT

RC connection

sleep

XIN/CLK

XOUT

clock generator

System clock control

System clock

Mask option

Mask option for choose Crystal or RC oscillation

Prescaler

Binary counter

1 2 3

5 6 7 8 9 10 11 12 13

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

TIME BASE INTERRUPT (TBI )

The time base can be used to generate a fixed frequency interrupt. There are 8 kinds of frequencies can be
selected by setting "P25"

Single clock mode
P25 3

( initial value 0000 )

0 0 x x: Interrupt disable
0 1 0 0: Interrupt frequency XIN / 2

0 1 0 1: Interrupt frequency XIN / 2

0 1 1 0: Interrupt frequency XIN / 2

0 1 1 1: Interrupt frequency XIN / 2

1 1 0 0: Interrupt frequency XIN / 2

1 1 0 1: Interrupt frequency XIN / 2

1 1 1 0: Interrupt frequency XIN / 2

1 1 1 1: Interrupt frequency XIN / 2

1 0 x x: Reserved

TIMER / COUNTER ( TIMERA, TIMERB)

Timer/counters can support user three special functions:
1. Even counter
2. Timer.
3. Pulse-width measurement.

These three functions can be executed by 2 timer/counter independently.
For timerA, the counter data is saved in timer register TAH, TAM, TAL, which user can set counter initial
value and read the counter value by instruction "LDATAH(M,L), STATAH(M,L)" and timer register is
TBH, TBM, TBL and W/R instruction "LDATBH (M,L), STATBH (M,L)".

The basic structure of timer/counter is composed by two same structure counter, these two counters can be
set initial value and send counter value to timer register, P28 and P29 are the command ports for timerA
and timer B, user can choose different operation mode and different internal clock rate by setting these two
ports. When timer/counter overflow, it will generate a TRGA(B) interrupt request to interrupt control unit.
To access TA, TB, user must switch RAM at bank0.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

Port 28

3 2 1 0

TMSA

IPSA

Initial state: 0000

TIMER/COUNTER MODE SELECTION

TMSA (B) Function description

0 0

Stop

0 1

Event counter mode

1 0

Timer mode

1 1

Pulse width measurement mode

Port 29

3 2 1 0

TMSB

IPSB

Initial state: 0000

INTERRUPT CONTROL

TRGA request

P8.3/
TRGA

EVENT COUNTER CONTROL

TIMER CONTROL

internal clock

P28

12 BIT COUNTER

TMSA

IPSA

DATA BUS

P8.1/
TRGB

EVENT COUNTER CONTROL

TIMER CONTROL

internal clock

P29

12 BIT COUNTER

TMSB

IPSB

TRGB request

PULSE-WIDTH MEASUREMENT

CONTROL

PULSE-WIDTH MEASUREMENT

CONTROL

TIMER/COUNTER CONTROL

P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event
counter and pulse-width measurement mode.

Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/
counterB.

INTERNAL PULSE-RATE SELECTION

IPSA(B) Function description

0 0

XIN/2 Hz

0 1

XIN/2 Hz

1 0

XIN/2 Hz

1 1

XIN/2 Hz

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

Internal pulse

TimerB (TimerA )value

n+1

n+2

n+3

n+4

n+5

n+6

n+7

P8.1/TRGB (P8.3/TRGA)

TimerB (TimerA) value n

n+1

n+2

n+3

n+4

n+5

n+6

TIMER/COUNTER FUNCTION

Timer/counterA can be programmable for timer, event counter and pulse width measurement. Each timer/
counter can execute any one of these functions independly.

EVENT COUNTER MODE

For event counter mode, timer/counter increases one at any rising edge of P8.1/TRGB for timerB (P8.3/
TRGA for timer A). When timerB (timerA) counts overflow, it will give interrupt control an interrupt request
TRGB (TRGA).

PROGRAM EXAMPLE: Enable timerA with P28

LDIA #0100B;
OUTA P28; Enable timerA with event counter mode

TIMER MODE

For timer mode, timer/counter increase one at any rising edge of internal pulse. User can choose 4 kinds
of internal pulse rate by setting IPSB for timerB (IPSA for timerA).
When timer/counter counts overflow, TRGB (TRGA) will be generated to interrupt control unit.

PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock XlN=4MHz

LDIA #0100B;
EXAE; enable mask 2
EICIL 110111B; interrupt latch

0, enable EI

LDIA #06H;
STATAL;
LDIA #01H;
STATAM;
LDIA #0FH;
STATAH;
LDIA #1000B;
OUTA P28; enable timerA with internal pulse rate: XIN/2

NOTE:

The preset value of timer/counter register is calculated as following procedure.
Internal pulse rate: XIN/2

; XIN = 4MHz

The time of timer counter count one = 2

/XIN = 1024/4000=0.256ms

The number of internal pulse to get timer overflow = 60 ms/ 0.256ms = 234.375 = 0EAH
The preset value of timer/counter register = 1000H - 0EAH = 0F16H

PULSE WIDTH MEASUREMENT MODE

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

For the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as
external timer/counter input (P8.1/TRGB, P8.3/TRGA), interrupt request will be generated as soon as
timer/counter count overflow.

Internal pulse

TimerB(TimerA) value

n+1

n+2

n+3

n+4

n+5

P8.1/TRGB(P8.3/TRGA)

PROGRAM EXAMPLE:

Enable timerA by pulse width measurement mode.

LDIA #1100b;
OUTA P28; Enable timerA with pulse width measurement mode.

INTERRUPT FUNCTION

There are 5 interrupt sources, 2 external interrupt sources, 3 internal interrupt sources. Multiple
interrupts are admitted according the priority.

Type

Interrupt source

Priority

Interrupt

Program ROM

Latch

Enable condition

entry address

External

External interrupt(INT0)

IL5

EI=1

002h

Internal

Reserved

IL4

EI=1, MASK3=1

004h

Internal

TimerA overflow interrupt (TRGA)

IL3

EI=1, MASK2=1

006h

Internal

TimerB overflow interrupt (TRGB)

IL2

EI=1, MASK1=1

008h

Internal

Time base interrupt(TBI)

IL1

00Ah

Internal

Speech ending interrupt (SPI)

IL0

EI=1,MASK0=1

00Ch

INTERRUPT STRUCTURE

Interrupt controller:

IL0-IL5

: Interrupt latch. Hold all interrupt requests from all interrupt sources. ILr can not be

set by program, but can be reset by program or system reset, so IL only can decide
which interrupt source can be accepted.

MASK0-MASK3

: Except INT0, MASK register can promit or inhibit all interrupt sources.

MASK0 MASK1 MASK1 MASK2 MASK3

IL0

IL1

TBI
r1

Reset by system reset and program
instruction

IL2

IL3

TRGA

IL4

IL5

INT0

Priority checker

Entry address generator

Interrupt request

Interrupt entry address

Reset by system reset and program
instruction
Set by program instruction
by EICIL or DICIL

TRGB

SPI

Reserved

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

: Enable interrupt Flip-Flop can promit or inhibit all interrupt sources, when inter-

rupt happened, EI is cleared to "0" automatically, after RTI instruction happened,
EI will be set to "1" again.

Priority checker: Check interrupt priority when multiple interrupts happened.

INTERRUPT FUNCTION

The procedure of interrupt operation:
1. Push PC and all flags to stack.
2. Set interrupt entry address into PC.
3. Set SF= 1.
4. Clear EI to inhibit other interrupts happened.
5. Clear the IL for which interrupt source has already be accepted.
6. To excute interrupt subroutine from the interrupt entry address.
7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.

PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"

LDIA #1100B;
EXAE; set mask register "1100B"
EICIL 111111B ; enable interrupt F.F.

POWER SAVING FUNCTION ( Sleep / Hold functlon )

During sleep and hold condition, CPU holds the system's internal status with a low power consumption, for
the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for
the stability of system clock running after wakeup. In the other way, for the hold mode, the system clock
does not stop at all and it does not need a warm-up time any way.
The sleep and hold mode is controlled by Port 16 and released by P0(0..3)/WAKEUP0..3 or P8(0..3)/
WAKEUPA..D.

Sleep and hold condition:

1. Osc stop (sleep only) and CPU internal status held.
2. Internal time base clear to "0".

P16 3 2 1 0

initial value :0000

SWWT Set wake-up warm-up time

2 /XIN
2 /XIN
2 /XIN
Hold mode

SE Enable sleep/hold

0 Reserved

1 Enable sleep / hold rnode

0
1

Wake-up in edge release mode
Wake-up in level release mode

0 0
0 1
1 0
1 1

18
14
16

WM SE SWWT

WM Set wake-up release mode

3. CPU internal memory, flags, register, I/O held original states.
4. Program counter hold the executed address after sleep release.

Release condition:

1. Osc start to oscillating (sleep only).
2. Warm-up time passing (sleep only).
3. According PC to execute the following program.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

There is only one kind of sleep/hold release mode.

1. Edge release mode:

Release sleep/hold condition by the falling edge of any one of P0(0..3)/WAKEUP0..3 or P8(0..3)/
WAKEUPA..D.

Note : There are 8 independent mask options for wakeup function in EM73962. So, the wakeup function
of P0(0..3)/WAKEUP0..3 and P8(0..3)/WAKEUPA..D are enabled or disabled independently.

LCD DRIVER

It can directly drive the liquid crystal display ( LCD ) and has 40 segments, 8 commons output pins.
There are total 40x8 dots can be display. The VRLC pin is the LCD driver power input, there is the voltage
of ( Vcc - VRLC ) to LCD.

(1) LCD driver control command register:

Port27 3

Initial value: 0h

LDC

LDC *

LCD DISPLAY CONTROL

LDC

Function description

LCD display disable

Blanking, change COMMON pin output

Reserved

LCD display enable

* : Don't care.

P27 is the LDC driver control command register. The initial value is 0000.
When LDC ( bit2 and bit3 of P27 ) is set to "0000", the LCD display is disabled.
When LDC is set to "0010", the LCD is blanking, the COM pins are inactive and the SEG pins continuously
output the display data.
The power switch of LCD driver is turned off when the CPU is reseted.
When LDC is set to "0110", the LCD display is enabled, the power switch is turned on and it can not be turned
off forever except the CPU is reseted again.
The power switch is also turned off during the sleep operation. Users must enable the LCD display again
by self when the CPU is waked up.

(2) LCD display data area:

The LCD display data is stored in the display data area of the data memory (RAM).
The display data area begins with address 20H during reset. The LCD display data area is as below:

C O M 0

C O M 1

C O M 2

C O M 3

C O M 4

C O M 5

C O M 6

C O M 7

20H

30H

40H

50H

60H

70H

80H

90H

b
i
t
0

b
i
t
1

b
i
t
2

b
i
t
3

S
E
G
0

S
E
G
1

S
E
G
2

S
E
G
3

S
E
G
4

S
E
G
5

S
E
G
6

S
E
G
7

S
E
G
8

S
E
G
9

S
E
G
1
0

S
E
G
1
1

S
E
G
1
2

S
E
G
1
3

S
E
G
1
4

S
E
G
1
5

S
E
G
1
6

S
E
G
1
7

S
E
G
1
8

S
E
G
1
9

S
E
G
2
0

S
E
G
2
1

S
E
G
2
2

S
E
G
2
3

S
E
G
2
4

S
E
G
2
5

S
E
G
2
6

S
E
G
2
7

S
E
G
2
8

S
E
G
2
9

S
E
G
3
0

S
E
G
3
1

S
E
G
3
2

S
E
G
3
3

S
E
G
3
4

S
E
G
3
5

S
E
G
3
6

S
E
G
3
7

S
E
G
3
8

S
E
G
3
9

RAM

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

Read automatically the display data from the display data area and send to the LCD driver by the hardware.
Therefore, the display patterns can be changed only by overwritting the contents of the display data area
with the software.
The data memory which is not used to store the LCD display data and the addresses are not connected to the
LCD can be used to store the ordinary user's processing data.

PROGRAM EXAMPLE:

LDIA #1100B

; LCD display enable

OUTA P27
LDIA #1010B
STA 24H

(3) LCD waveform :

: ON

: OFF

COM0

COM1

COM7

SEG0

SEG0-COM0

VDD

V4
V3
V2
V1

VSS

COM0

VDD

V4
V3
V2
V1

VSS

COM1

SEG0

COM0

COM1

SEG0

SEG0-COM0

VDD

V3
V2
V1

VSS

COM0

VDD

V3
V2
V1

VSS

COM1

SEG0-COM0

OFF

SEG0-COM0

SEG0-COM1

SEG0-COM0

SEG0-COM1

OFF

SEG0-COM1

OFF

Frame freq.=65Hz

Frame freq.
=65Hz

* TYPE A, 1/4 bias :

* TYPE B, 1/4 bias :

* TYPE A, modify 1/4 bias :

* TYPE B, modify 1/4 bias :

BIAS

VDD

VSS

Modify 1/4

17/23

12/23

11/23

6/23

1/4

3/4

1/2

1/4

S
E

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

SOUND EFFECT

EM73962 has a built-in sound generator. It includes the tone generator, random generator and volume control.
The tone generator is a binary down counter and the random generator is a 9-bit linear feedback shift register.
When the CPU is reseted or sleeping, the sound generator is disabled and the output (P4.0/SOUND) is high.

Low

PWM

volume control

÷2

f2x2

P23,P24

P17

SOUND

P.30

Output
control

Tone

generator

Random

generator

3 kinds

of divider

Tone frequency register

The 8-bit tone frequency register is P24 and P23. The tone frequency will be changed when user output the
different data to P23. Thus, the data must be output to P24 before P23 when user want to change the 8-bit
tone frequency (TF).

Port24

Port23

3 2 1

Initial value : 1111 1111

Higher nibble register

Lower nibble register

** f1=240K/2

, f2=f1/(TF+1)/2, TF=1~255, TF-0

** Example : BFREQ=10, TF=00110001B.

f1=60K Hz, f2=60K Hz/50/2=600 Hz

Random generator

f(x)=x

Port30

3 2 1 0

BFREQ

SMODE

Initial value : 0000

BFREQ Basic frequency (f1) select

SMODE

Sound generator mode

240 KHz

Disable

120 KHz

Tone output

60 KHz

Random output

don't care

Tone+random output

There are 3 kinds of basic frequency for sound generator which can be selected by P30. The output of sound
effect is tone and random combination.

Sound generator command register

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

SPEECH SYNTHESIZER

BLOCK DIAGRAM

P6 Write

P5 Write

Speech ROM

Speech Decoder

7 Bits DAC

SPI

P6.3 read

Speech

Interrupt

Speech

Active

Set Speech Address

(Write 3times)

Set Sample Rate

tp=

60KHz

Volume control register
The are 8 levels of volume for sound generator. P17 is the volume control register.

Port17

Initial value : * 1111

3 2 1 0

VCR

ts/tp

8/8

7/8

6/7

5/8

4/8

3/8

2/8

1/8

PROGRAM EXAMPLE:

LDIA

#1001B ; basic frequency : 60 KHz tone output

OUTA

P30

LDIA

#0011B ; 600 Hz tone output

OUTA

P24

LDIA

#0001B

OUTA

P23

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

OPERATION PROCEDURE

(1) Write the speech wave file name to a document file (*.SET)

ex : Document filename : TEST.SET

TRY.WAV
GOOD.WAV
HURRY.WAV
:
:

(2) Run the speech convertind program address by SC982.exe, to get the speech section address table.

ex : Run C:\SC982 TEST.SET

:
:
Generated following files :
TEST.ADR
TEST.COD
TEST.SEG

(3) Write the TEST1.ADR in your program

ex : TEST.ASM

:
TRY

EQU 0040 H/40H

; Speech ROM Address get from TEST.ADR

GOOD

EQU 0D00H/40H

;

HURRY

EQU 19C0H/40H

;

:
:
LDIA

# TRY

; PLAY TRY.WAV

OUT

LDIA

# TRY/10H

; Send the speech address by writing P6 three times

OUT

LDIA

# TRY/100H

OUT

LDIA

# 0011B

; set 8K sample rate and enable speech

OUT

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

RESET FUNCTION

When CPU in normal working condition and RESET pin holds in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, and when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :

Hardware condition in RESET (f1) state

Initial value

Program counter

0000h

Status flag

01h

Interrupt enable flip-flop ( EI )

00h

MASK0 ,1, 2, 3

00h

Interrupt latch ( IL )

00h

P3, P5, P6, P9, 16, 25, 27, 28, 29, 30

00h

P4, 8, 17, 23, 24

0Fh

XIN

Start oscillation

The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to V

and a diode to V

RESET

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

EM73982 I/O PORT DESCRIPTION :

Port

Input function

Output function

Note

Input port , wakeup function

P3(1..0) : ROM bank selection

input port

Output port, P4.0/SOUND

P5(0..3) : Speech sample rate

P6.3 : Speech Active pin

P6(0..3) : Speech ROM address

Input port, wakeup function,

Output port

external interrupt input

P9.3 : RAM bank selection

Sleep/Hold mode control register

Sound effect volume control register

Sound effect frequency register

low nibble

Sound effect command register

high nibble

Timebase control register

LCD control register

Timer/counter A control register

Timer/counter B control register

Sound effect command register

NOTE : E : external
I : internal

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

DC ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS (V

=3±0.3V, V

=0V, T

OPR

=25

Parameters Sym.

Min.

Typ.

Max.

Unit

Conditions

Supply current

0.7

=3.3V,no load,Fc=4MHz

(RC osc : R=6.2K

, C=20pF)

0.1

µA

=3.3V, sleep mode

Hysteresis voltage

HYS+

0.5V

0.75V

RESET, P0, P8

HYS-

0.2V

0.4V

Input current

±1

µA

P0, RESET, V

=3.3V,V

=3.3/0V

±1

µA

Open-drain, V

=3.3V,V

=3.3/0V

-500

µA

Push-pull, V

=3.3V ,V

=0.4V,except P4

Output voltage

O H

2.4

Push-pull, V

=2.7V,P4(high current PMOS),

SOUND,I

=-0.9mA

2.0

Push-pull, V

=2.7V,others,I

=-40µA

0.3

=2.7V,I

=0.9mA

Leakage current

µA

Open-drain, V

=3.3V, V

=3.3V

Input resistor

100

200

300

600

900

RESET

Frequency stability

Fc=4MHz,RC osc,[F(3V)-F(2.4V)]/F(3V)

Frequency variation

Fc=4MHz, V

=3V,RC osc,

[F(typical)-F(worse case)]/F(typical)

Output current of V

2.0

3.0

4.0

=3V,V

=0.7V

RECOMMANDED OPERATING CONDITIONS

Items

Sym.

Ratings

Condition

Supply Voltage

D D

2.4V to 5.5V

Input Voltage

0.90xV

to V

0V to 0.10xV

Operating Frequency

480K to 4MHz

CLK (RC osc)

480K to 4.19MHz

XIN,XOUT (crystal osc)

ABSOLUTE MAXIMUM RATINGS

Items

Sym.

Ratings

Conditions

Supply Voltage

-0.5V to 6V

Input Voltage

-0.5V to V

+0.5V

Output Voltage

-0.5V to V

+0.5V

Power Dissipation

300mW

OPR

=50

Operating Temperature

OPR

C to 50

Storage Temperature

STG

-55

C to 125

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

=4.5±0.5V, V

=0V, T

OPR

=25

Parameters Sym.

Min.

Typ.

Max.

Unit

Conditions

Supply current

4.5

5.5

=5V, no load, Fc=4MHz(crystal osc)

1.5

=5V, no load, Fc=4MHz(RC osc :

R=7.5K

, C=20pF)

0.1

=5V, sleep mode

Hysteresis voltage

HYS+

0.5V

0.75V

RESET, P0, P8

HYS-

0.2V

0.4V

Input current

±1

P0, RESET, V

=5V, V

=5/0V

±1

Open-drain, V

=5V, V

=5/0V

-1

Push-pull, V

=5V ,V

=0.4V, except P4

Output voltage

O H

3.0

Push-pull, P4(high current PMOS), SOUND
V

=4V, I

=-4mA

2.4

Push-pull, P4(low current PMOS), P8
V

=4V, I

=-200

O L

1.0

=4V, I

=4mA

Leakage current

Open-drain, V

=5V, V

=5V

Input resistor

150

100

300

450

RESET

Frequency stability

Fc=4MHz,RC osc,[F(4.5V)-F(3.6V)]/F(4.5V)

Frequency variation

Fc=4MHz, V

=4.5V,RC osc,

[F(typical)-F(worse case)]/F(typical)

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

RESET

mask option

XIN

XOUT

Crystal
Osc.

mask option

: mask option

P0/WAKEUP TYPE

INPUT-A

XIN

WAKEUP function
mask option

RC Osc.

(comparator)

TYPE I/O

Output
data
latch

Input
data

Output
data

path B

path A

SEL

Special function
control input

WAKEUP function
mask option

RESET PIN TYPE

TYPE RESET-A

OSCILLATION PIN TYPE

TYPE OSC-A

TYPE OSC-C

INPUT PIN TYPE

TYPE INPUT-A

TYPE INPUT-B

I/O PIN TYPE

TYPE I/O

TYPE I/O-L

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

PAD DIAGRAM

21 22 23 24 25 26 27 28 29 30 31 32 33 34

68 67 66 65 64 63 62 61 60 59 58 57 56 55

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

COM0

COM1

SEG8

ESG9

SEG10

SEG11

ESG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

VSS

P8.0

P8.1

P8.2

P8.3

P0.0

P0.1

P0.2

P0.3

RESET

TEST

XIN

XOUT

VDD

SOUND

P4.0

P4.1

P4.2

P4.3

COM7

COM6

COM5

COM4

COM3

COM2

COM1

(0,0)

EM73982

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

Pad No.

Symbol

SEG7

-839.6

1063.4

SEG6

-839.6

952.9

SEG5

-839.6

842.5

SEG4

-839.6

732.0

SEG3

-839.6

621.6

SEG2

-839.6

511.1

SEG1

-839.6

400.6

SEG0

-828.2

290.2

VSS

-828.2

179.7

P8.0

-834.7

59.9

P8.1

-834.7

-52.1

P8.2

-834.7

-164.2

P8.3

-834.7

-276.2

P0.0

-834.7

-388.3

P0.1

-834.7

-500.3

P0.2

-834.7

-612.4

P0.3

-834.7

-724.5

RESET

-834.7

-836.5

TEST

-839.6

-948.1

XIN

-839.6

-1060.2

XOUT

-719.9

-1049.6

VDD

-605.6

-1035.2

-489.9

-1044.7

SOUND

-374.4

-1044.7

P4.0

-262.4

-1044.7

P4.1

-150.3

-1044.7

P4.2

-38.3

-1044.7

P4.3

73.8

-1044.7

COM7

185.9

-1049.6

COM6

296.3

-1049.6

COM5

406.8

-1049.6

COM4

517.2

-1049.6

COM3

627.7

-1049.6

COM2

738.2

-1049.6

COM1

848.6

-1049.6

COM0

839.6

-929.9

SEG39

839.6

-819.5

SEG38

839.6

-709.0

Chip Size : 2000 x 2420 UM.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

Pad No.

Symbol

SEG37

839.6

-598.5

SEG36

839.6

-488.1

SEG35

839.6

-377.6

SEG34

839.6

-267.2

SEG33

839.6

-156.7

SEG32

839.6

-46.2

SEG31

839.6

64.2

SEG30

839.6

174.7

SEG29

839.6

285.1

SEG28

839.6

395.6

SEG27

839.6

506.1

SEG26

839.6

616.5

SEG25

839.6

727.0

SEG24

839.6

837.4

SEG23

839.6

947.9

SEG22

839.6

1058.4

SEG21

718.0

1049.4

SEG20

607.5

1049.4

SEG19

497.1

1049.4

SEG18

386.6

1049.4

SEG17

276.2

1049.4

SEG16

165.7

1049.4

SEG15

55.2

1049.4

SEG14

-55.2

1049.4

SEG13

-165.7

1049.4

SEG12

-276.1

1049.4

SEG11

-386.6

1049.4

SEG10

-497.1

1049.4

SEG9

-607.5

1049.4

SEG8

-718.0

1049.4

NOTE : Unit :

For PCB layout, IC substrate must be floated or connected to Vss.

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

INSTRUCTION TABLE

(1) Data Transfer

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

LDA x

0110 1010 xxxx xxxx

Acc

RAM[x]

LDAM

0101 1010

Acc

RAM[HL]

LDAX

0110 0101

Acc

ROM[DP]

LDAXI

0110 0111

Acc

ROM[DP]

,DP+1

LDH #k

1001 kkkk

LDHL x

0100 1110 xxxx xx00

RAM[x],HR

RAM[x+1] 2

LDIA #k

1101 kkkk

Acc

LDL #k

1000 kkkk

STA x

0110 1001 xxxx xxxx

RAM[x]

Acc

STAM

0101 1001

RAM[HL]

Acc

STAMD 0111 1101

RAM[HL]

Acc, LR-1

STAMI

0111 1111

RAM[HL]

Acc, LR+1

STD #k,y

0100 1000 kkkk yyyy

RAM[y]

STDMI #k

1010 kkkk

RAM[HL]

k, LR+1

THA

0111 0110

Acc

TLA

0111 0100

Acc

(2) Rotate

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

RLCA 0101 0000

Acc

RRCA 0101 0001

Acc

(3) Arithmetic operation

3) Arithmetic operation

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

ADCAM

0111 0000

Acc

Acc + RAM[HL] + CF

ADD

#k,y

0100 1001 kkkk yyyy

RAM[y]

RAM[y] +k

ADDA #k

0110 1110 0101 kkkk

Acc

Acc+k

ADDAM

0111 0001

Acc

Acc + RAM[HL]

ADDH #k

0110 1110 1001 kkkk

HR+k

ADDL

0110 1110 0001 kkkk

LR+k

ADDM #k

0110 1110 1101 kkkk

RAM[HL]

RAM[HL] +k

DECA

0101 1100

Acc

Acc-1

DECL

0111 1100

LR-1

DECM

0101 1101

RAM[HL]

RAM[HL] -1

INCA

0101 1110

Acc

Acc + 1

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

INCL

0111 1110

LR + 1

INCM

0101 1111

RAM[HL]

RAM[HL]+1

SUBA

0110 1110 0111 kkkk

Acc

k-Acc

SBCAM

0111 0010

Acc

RAM[HLl - Acc - CF'

SUBM #k

0110 1110 1111 kkkk

RAM[HL]

k - RAM[HL]

((
((
(

4) Logical operation

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

Flag
C

ANDA #k

0110 1110 0110 kkkk Acc

Acc&k

ANDAM

0111 1011

Acc

Acc & RAM[HL]

ANDM #k

0110 1110 1110 kkkk RAM[HL]

RAM[HL]&k

ORA

0110 1110 0100 kkkk Acc

Acc k

ORAM

0111 1000

Acc

Acc RAM[HL]

ORM

0110 1110 1100 kkkk RAM[HL]

RAM[HL] k

XORAM

0111 1001

Acc

Acc^RAM[HL]

(5) Exchange

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

EXA

0110 1000 xxxx xxxx Acc

RAM[x]

EXAH

0110 0110

Acc

EXAL

0110 0100

Acc

EXAM

0101 1000

Acc

RAM[HL]

EXHL x

0100 1100 xxxx xx00

RAM[x],

RAM[x+1]

(6) Branch

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

SBR a

00aa aaaa

If SF=1 then PC

12-6

5-0

else null

LBR a 1100 aaaa aaaa aaaa

If SF= 1 then PC

a else null

SLBR a

0101 0101 1100 aaaa

If SF=1 then PC

a else null

aaaa aaaa

(a:1000~1FFFh)

0101 0111 1100 aaaa

aaaa aaaa

(a:0000~0FFFh)

(7) Compare

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

CMP

#k,y 0100 1011 kkkk yyyy

k-RAM[y]

CMPA x

0110 1011 xxxx xxxx

RAM[x]-Acc

- -

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

(8) Bit manipulation

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

CLM

1111 00bb

RAM[HL]

CLP

p,b

0110 1101 11bb pppp

PORT[p]

CLPL

0110 0000

PORT[LR

3-2

+4]

1-0

CLR y,b

0110 1100 11bb yyyy

RAM[y]

SEM

1111 01bb

RAM[HL]

SEP

p,b

0110 1101 01bb pppp

PORT[p]

SEPL

0110 0010

PORT[LR

3-2

+4]

l-0

SET

y,b

0110 1100 01bb yyyy

RAM[y]

y,b

0110 1100 00bb yyyy

RAM[y]

TFA

1111 10bb

Acc

TFM b

1111 11bb

RAM[HL]

TFP

p,b

0110 1101 00bb pppp

PORT[p]

TFPL

0110 0001

PORT[LR

3-2

+4]

1-0

y,b

0110 1100 10bb yyyy

RAM[y]

TTP

p,b

0110 1101 10bb pppp

PORT[p]

(9) Subroutine

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

LCALL a

0100 0aaa aaaa aaaa

STACK[SP]

PC,

SP -1, PC

SCALL a

1110 nnnn

STACK[SP]

PC,

SP - 1, PC

a, a = 8n + 6

=115

),0086h (n = 0)

RET

0100 1111

SP + 1, PC

STACK[SP]

(10) Input/output

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

INA p

0110 1111 0100 pppp

Acc

PORT[p]

INM p

0110 1111 1100 pppp

RAM[HL]

PORT[p]

OUT #k,p

0100 1010 kkkk pppp

PORT[p]

OUTA p

0110 1111 000p pppp

PORT[p]

Acc

OUTM p

0110 1111 100p pppp

PORT[p]

RAM[HL]

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

CMPAM

0111 0011

RAM[HL] - Acc

CMPH #k

0110 1110 1011 kkkk

k - HR

CMPIA #k 1011 kkkk

k - Acc

CMPL #k

0110 1110 0011 kkkk

k-LR

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Cycle Flag

Flag

TFCFC

0101 0011

CF', CF

TTCFS

0101 0010

CF, CF

TZS

0101 1011

(12) Interrupt control

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

CIL r

0110 0011 11rr rrrr

IL & r

DICIL r

0110 0011 10rr rrrr

EIF

0,IL

IL&r

EICIL r

0110 0011 01rr rrrr

EIF

1,IL

IL&r

EXAE

0111 0101

MASK

Acc

RTI

0100 1101

SP+1,FLAG.PC

STACK[SP],EIF

(13) CPU control

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

Flag
C

NOP

0101 0110

no operation

(14) Timer/Counter & Data pointer & Stack pointer control

Mnemonic Object code ( binary )

Operation description

Byte

Cycle

Flag

LDADPL

0110 1010 1111 1100

Acc

[DP]

LDADPM

0110 1010 1111 1101

Acc

[DP]

LDADPH

0110 1010 1111 1110

Acc

[DP]

LDASP

0110 1010 1111 1111

Acc

LDATAL

0110 1010 1111 0100

Acc

[TA]

LDATAM

0110 1010 1111 0101 Acc

[TA]

LDATAH

0110 1010 1111 0110 Acc

[TA]

LDATBL

0110 1010 1111 1000

Acc

[TB]

LDATBM

0110 1010 1111 1001

Acc

[TB]

LDATBH

0110 1010 1111 1010

Acc

[TB]

STADPL

0110 1001 1111 1100

[DP]

Acc

STADPM

0110 1001 1111 1101

[DP]

Acc

STADPH

0110 1001 1111 1110

[DP]

Acc

STASP

0110 1001 1111 1111

Acc

STATAL

0110 1001 1111 0100

[TA]

Acc

STATAM

0110 1001 1111 0101

[TA]

Acc

STATAH

0110 1001 1111 0110

[TA]

Acc

STATBL

0110 1001 1111 1000

[ TB]

Acc

STATBM

0110 1001 1111 1001

[TB]

Acc

STATBH

0110 1001 1111 1010

[TB]

Acc

(11) Flag manipulation

* This specification are subject to be changed without notice.

EM73982

4-BIT MICROCONTROLLER

11.30.2001

**** SYMBOL DESCRIPTION

Symbol

Description

Symbol

Description

H register

L register

Program counter

Data pointer

Stack pointer

STACK[SP]

Stack specified by SP

Accumulator

FLAG

All flags

Carry flag

Zero flag

Status flag

Enable interrupt register

Interrupt latch

MASK

Interrupt mask

PORT[p]

Port ( address : p )

Timer/counter A

Timer/counter B

RAM[HL]

Data memory (address : HL)

RAM[x]

Data memory (address : x )

ROM[DP]

Low 4-bit of program memory

ROM[DP]

High 4-bit of program memory

[DP]

Low 4-bit of data pointer register

[DP]

Middle 4-bit of data pointer register

[DP]

High 4-bit of data pointer register

[TA]

([TB]

)

Low 4-bit of timer/counter A

[TA]

([TB]

)

Middle 4-bit of timer/counter A

(timer/counter B) register

[TA]

([TB]

)

High 4-bit of timer/counter A

-0

Contents of bit assigned by bit

(timer/counter B) register

1 to 0 of LR

3-2

Bit 3 to 2 of LR

5-0

Bit 5 to 0 of destination address for

branch instruction

12-6

Bit 12 to 6 of program counter

Transfer

Exchange

Addition

Substraction

Logic AND

Logic OR

Logic XOR

Inverse operation

Concatenation

4-bit immediate data

8-bit RAM address

4-bit zero-page address

4-bit or 5-bit port address

Bit address

6-bit interrupt latch

- -

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EM73982

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EM73982