Applications
1
Features
n Industrial controllers
Alarm systems with periodic wake up
PABX and telephone systems
Point of sale terminals
Automotive electronics
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n Digital trimming and temperature compensation
facilities
Can be synchronized to 50 Hz or nearest s/min
50 ns access time with 50 pF load capacitance
Standby on power down typically 1.2 A
Universal interface compatible with both Intel and Motorola
Simple 8 bit interface with no delays or busy flags
16 bytes of user RAM
Power fail input disables during power up / down or reset
Bus can be tri-state in power fail mode
Wide voltage range, 2.0 V to 5.5 V
12 or 24 hour data formats
Time to 1/100 of a second
Leap year correction and week number calculation
Alarm and timer interrupts
Programmable interrupts: 10 ms, 100 ms, s or min
Sleep mode capability
Alarm programmable up to one month
Timer measures elapsed time up to 24 hours
Temperature range -40 to +85 C
Packages DIP20 and SO20
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O
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Description
The A3024 is a low power CMOS real time clock. Standby
current is typically 1.2
A and the access time is 50 ns. The
interface is 8 bits with multiplexed address and data bus.
Multiplexing of address and data is handled by the input line
/D. There are no busy flags in the A3024, internal time update
cycles are invisible to the user's software. Time data can be
read from the A3024 in 12 or 24 hour data formats. An external
signal puts the A3024 in standby mode. Even in standby, the
A3024 pulls the
pin active low on an internal alarm interrupt.
Calendar functions include leap year correction and week
number calculation. Time precision can be achieved by digital
triming. The A3024 can be synchronized to an external 50 Hz
signal or to the nearest second or minute.
m
A
IRQ
Very Low Power 8-Bit 32 kHz RTC with
Digital Trimming, User RAM and High Level Integration
Pin Assignment
DIP20 / SO20
Fig. 2
SYNC
PF
A
IRQ
AD0
AD1
AD2
AD3
/D
V
X
SS
IN
NC
AD7
AD6
AD5
AD4
V
X
RD
WR
CS
DD
OUT
A3024
Typical Operating Configuration
Fig. 1
CPU
Address
Decoder
Address
Bus
Data
Bus
WR
W
RD
DS
IRQ
or
R/
or
CS
RD
WR
RAM
AD0 to AD7
A3024
X in
X out
CS
IRQ
RD
WR
A/D
EM MICROELECTRONIC-MARIN SA
A3024
R
Absolute Maximum Ratings
Operating Conditions
Handling Procedures
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond specified
operating conditions may affect device reliability or cause
malfunction.
This device has built-in protection against high static voltages
2
Table 1
Parameter
Maximum voltage at V
Max. voltage at remaining pins
Min. voltage on all pins
DD
Maximum storage temperature
Minimum storage temperature
Maximum electrostatic discharge
to MIL-STD-883C method 3015
Maximum soldering conditions
V
DDmax
V
max
V
min
T
STOmin
T
STOmax
V
Smax
T
Smax
V
+ 7.0V
SS
V
+ 0.3V
DD
V
- 0.3V
SS
-55 C
O
+125 C
O
1000V
250 C x 10s
O
Symbol Conditions
or electric fields; however, it is advised that normal precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when all
terminal voltages are kept within the supply voltage range.
Unused inputs must always be tied to a defined logic voltage
level.
T
A
-40
2.0
5.0
+85
O
C
V
V/ s
m
nF
kHz
pF
k
W
5.5
6
12.5
50
100
32.768
8.2
35
7
V
DD
C
L
R
S
f
dv/dt
Table 2
Parameter
Symbol Min. Typ. Max. Units
Operating temperature
Logic supply voltage
Supply voltage dv/dt
(power-up & down)
Decoupling capacitor
Crystal Characteristics
Frequency
Load Capacitance
Series resistance
Electrical Characteristics
V
= 5.0V 10%, V
= 0 V, T = -40 to +85 C, unless otherwise specified
DD
S
A
O
S
1)
2)
3)
4)
With
= 0 (V ) all I/O pads can be tri-state, tested.
With
= 1 (V
),
= 1 (V
) and all other I/O pads fixed to V
or to V : same standby current, not tested.
All other inputs to V
and all outputs open.
At a given temperature.
See Fig. 4
PFO
PFO
CS
SS
DD
DD
DD
SS
DD
Table 3
Standby current
1)
Dynamic current
2)
IRQ (open drain)
Inputs and Outputs
Output low voltage
Input logic low
Output low voltage
Input logic high
Output logic low
Output logic high
PF activation voltage
PF hysteresis
Pullup on SYNC
Input leakage
Output tri-state leakage
Oscillator Characteristics
Starting voltage
Frequency tolerance
Frequency stability
Temperature stability
Start-up time
Frequency Characteristics
I
DD
I
DD
V
OL
V
OL
V
IL
V
IH
V
OL
V
OH
V
H
V
PFL
I
IN
I
LS
I
TS
V
STA
V
STA
T
STA
Df/f
f
sta
t
sta
ppm/V
ppm
T
+25 C
A
O
T = +25 C addr. 10 hex = 00 hex
A
O
210
4)
251
ppm
2.0
V
5.5 V
DD
3)
1
5
addr. 10 hex = 00 hex
see Fig. 5
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Units
T = +25 C
A
0
V
= 0.8 V
ILS
V <V <V
SS
IN
DD
CS = 1
T = +25 C
A
0
T = +25 C
A
0
I
= 6 mA
OL
I
= 6 mA
OH
0.2
V
DD
V
V
V
V
V
0.8
V
DD
0.4
2.4
0.5
V
DD
100
mV
mA
nA
nA
20
10
1000
10
1000
2
V
V
s
2.5
1
I
= 8 mA
OL
I
= 1 mA, V
= 2 V
OH
DD
0.4
0.4
V
V
V
= 3 V,
= 0
DD
PF
V
= 5 V,
= 0
DD
PF
1.2
2
10
15
1.5
mA
mA
mA
CS
RD
= 4 MHz,
= V ,
SS
WR = V
DD
A3024
R
3
Typical Frequency on IRQ
DF
F
0
ppm
T [ C]
A
0
Address 10 hex = 00 hex
Quartz recommended
32.768 Hz 30 ppm
with 8.2 pF load capacitance
250
200
150
100
50
0
-50
-30
-10
10
30
50
70
90
Fig. 4
Typical Standby Current at V
= 5 V
DD
5
4
3
2
1
0
-50
25
50
80
95
T [ C]
A
0
I
[ A]
DD
m
Typical standby current range at V
= 5 V
DD
Fig. 3
Characteristic of a Quartz
Fig. 5
= the ratio of the change in frequency to the nominal value
expressed in ppm (It can be thought of as the frequency
deviation at any temperature.)
= the temperature of interest in C
= the turnover temperature (25 5 C)
O
O
To determine the clock error (accuracy) at a given temperature, add
the frequency tolerance at 25 C to the value obtained from the
formula above.
O
[ppm]
F
r
equency
ratio
[
ppm]
-100
-200
-300
-400
T -100
O
T - 50
O
Temperature [ C]
O
T [ C]
O
T
O
T +50
O
T +100
O
DF
F
0
DF
F
O
ppm
C
O
2
= - 0.038
(T - T ) 10%
O
2
DF/F
O
T
T
O
min.
max.
A3024
R
4
Fig. 6a
t
CS
t
ACC
t
W
t
A/Dt
t
R
t
A/Ds
t
F
DATA VALID
t
DF
CS
A/D
RD DS
/
DATA
Read Timing for Intel (
and
pulse) and Motorola (
or
pin tied to
, and R/ )
RD
WR
DS
RD
CS
W
Timing Waveforms
V
= 5.0 10%, V
= 0 V, and T = -40 to +85 C
DD
SS
A
0
Timing Characteristics
1)
2)
3)
4)
5)
t
starts from
(
) or
, whichever activates last
Typically, t
= 5 + 0.9 C
in ns; where C
(external parasitic capacitance) is in pF
t
starts from
(
) or
, whichever deactivates first
t
ends at
(R/ ) or
, whichever deactivates first
t
starts from
(R/ ) or
, whichever deactivates first
/D must come before a
and
or a
and
combination. The user has to guarantee this.
ACC
ACC
EXT
EXT
DF
DW
DH
RD DS
CS
RD DS
CS
WR
W
CS
WR
W
CS
A
CS
RD
CS
WR
Table 4
Parameter
Chip select duration, write cycle
Write pulse duration
Time between two transfers
RAM access time
Data valid to Hi-impedance
Write data settle time
Data hold time
Advance write time
response delay
Rise time (all timing waveform signals)
Fall time (all timing waveform signals)
delay after /D
delay to /D
1)
2)
3)
4)
5)
PF
A
CS
A
CS
t
CS
t
WR
t
W
t
ACC
t
DF
t
DW
t
DH
t
ADW
t
PF
t
R
t
F
t
A/Ds
t
A/Dt
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
100
10
50
10
10
5
10
60
40
100
200
200
50
30
C
= 50 pF
LOAD
Symbol
Test Conditions
Min.
Typ.
Max.
Units
A3024
R
5
Fig. 6d
CS
A/D
RD
WR
Data Bus
D0 to D7
Valid Address
Valid Data
Read
Intel Interface
Write Timing
t
CS
t
W
t
A/Dt
t
A/Ds
t
WR
t
DW
DATA VALID
Fig. 6b
t
DH
CS
A/D
RD
WR
DATA
Write
Fig. 6c
CS
A/D
RD
WR
Data Bus
D0 to D7
Valid Address
Valid Data
A3024
R
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