EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Ultra Low Power Multi I/O Microcontroller
Features
Low Power - typical 1.8A active mode
- typical 0.35A standby mode
- typical 0.1A sleep mode
@ 1.5V, 32kHz, 25 C
Low Voltage - 1.2 to 3.6 V
buzzer - three tone
ROM
-
2k
16 (Mask Programmed)
RAM
-
96
4 (User Read/Write)
2 clocks per instruction cycle
RISC
architecture
4 software configurable 4-bit ports
Up to 16 inputs (4 ports)
Up to 12 outputs (3 ports)
Serial (Output) Write buffer - SWB
Voltage
level
detection
Analogue
watchdog
Timer
watchdog
8 bit timer / event counter
Internal interrupt sources (timer, event
counter, prescaler, SWB)
External interrupt sources (portA + portC)
Description
The EM6603 is an advanced single chip low cost,
mask programmed - CMOS 4-bit microcontroller. It
contains ROM, RAM, watchdog timer, oscillation
detection circuit, combined timer / event counter,
prescaler, voltage level detector and a number of
clock functions. Its low voltage and low power
operation make it the most suitable controller for
battery, stand alone and mobile equipment. The
EM66XX series is manufactured using EM
Microelectronic's Advanced Low Power CMOS
Process.
Typical Applications
sensor
interfaces
domestic
appliances
security
systems
bicycle
computers
automotive
controls
TV & audio remote controls
measurement
equipment
R/F and IR. control
Figure 1.Architecture
Figure 2.Pin Configuration
EM MICROELECTRONIC
- MARIN SA
EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6603 at a glance
Power Supply
- Low Voltage, low power architecture
including internal voltage regulator
- 1.2V ... 3.6 V battery voltage
- 1.8
A in active mode
- 0.35
A in standby mode
- 0.1
A in sleep mode
@ 1.5V, 32kHz, 25 C
- 32 kHz Oscillator
RAM
- 96 x 4 bit, direct addressable
ROM
- 2048 x 16 bit metal mask programmable
CPU
- 4 bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
Main Operating Modes and Resets
- Active mode
(CPU is running)
- Standby mode
(CPU in Halt)
- Sleep mode
(No clock, Reset State)
- Initial reset on Power-On (POR)
- External reset pin
- Watchdog timer (time-out) reset
- Oscillation detection watchdog reset
- Reset with input combination on PortA
(metal option)
4-Bit Input PortA
- Direct input read
- Debounced or direct input selectable (reg.)
- Interrupt request on input's rising or falling edge,
selectable by register.
- Pull-down or none, selectable by metal mask
- Software test variables for conditional jumps
- PA3 input for the event counter
- Reset with input combination on PortA
(metal option)
4-Bit Input/Output PortB
- separate input or output selection by register
- Pull-up, Pull-down or none, selectable by metal mask if
used as Input
- Buzzer output on PB0
4-Bit Input/Output PortC
- Input or Output port as a whole port
- Debounced or direct input selectable (reg.)
- Interrupt request on input's rising or falling edge,
selectable by register.
- Pull-up, pull-down or none, selectable by
metal mask if used as input
- CMOS or N-channel open drain mode
4-Bit Input/Output PortD
- Input or Output port as a whole port
- Pull-up, Pull-down or none, selectable by metal
mask if used as Input
- CMOS or N-channel open drain mode
- Serial Write Buffer clock and data output
Serial (output) Write Buffer
- max. 256 bits long clocked with
16/8/2/1kHz
- automatic send mode
- interactive send mode : interrupt request
when buffer is empty
Buzzer Output
- if used output on PB0
- 3 tone buzzer - 1kHz, 2kHz, 2.66kHz
Prescaler
-
32kHz output possible on the STB/RST pin
-
15 stage system clock divider down to 1 Hz
- 3 interrupt requests : 1Hz/8Hz/32Hz
- Prescaler reset (from 8kHz to 1Hz)
8-bit Timer / Event Counter
-
8-bit auto-reload count-down timer
- 6 different clocks from prescaler
- or event counter from the PA3 input
- parallel load
- interrupt request when comes to 00 hex.
Supply Voltage Level Detector
- 3 software selectable levels (1.3V, 2.0V,
2.3V or user defined between 1.3V and 3.0V)
- Busy flag during measure
- Active only on request during measurement to
reduce power consumption
Interrupt Controller
-
8 external interrupt sources: 4 from Port A and 4
from Port C
- 3 internal interrupt sources, prescaler, timer and
Serial Write Buffer
- each interrupt request is individually maskable
- interrupt request flag is cleared automatically on
register read
EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of Contents
1
OPERATING MODES
5
1.1
STANDBY M
ODE
5
1.2
SLEEP MODE
5
2
POWER SUPPLY
5
3
RESET
6
3.1
O
SCILLATION DETECTION CIRCUIT
6
3.2
R
ESET
P
IN
6
3.3
I
NPUT PORT
(PA0..PA3) RESET
7
3.4
W
ATCHDOG
T
IMER
RESET
7
3.5
CPU S
TATE AFTER
RESET
7
4
OSCILLATOR
8
4.1
P
RESCALER
8
5
WATCHDOG TIMER
8
6
INPUT AND OUTPUT PORTS
9
6.1
P
ORT
A
9
6.2
P
ORT
A
REGISTERS
10
6.3
P
ORT
B
11
6.4
P
ORT
B
REGISTERS
11
6.5
P
ORT
C
12
6.6
P
ORT
C
REGISTERS
12
6.7
P
ORT
D
14
6.8
P
ORT
D
REGISTERS
14
7
BUZZER
15
7.1
B
UZZER
R
EGISTER
15
8
TIMER/EVENT COUNTER
16
8.1
T
IMER
/C
OUNTER REGISTERS
17
9
INTERRUPT CONTROLLER
18
9.1
I
NTERRUPT CONTROL REGISTERS
18
10
SUPPLY VOLTAGE LEVEL DETECTOR (SVLD)
20
10.1
SVLD
REGISTER
20
11
SERIAL (OUTPUT) WRITE BUFFER SWB
21
11.1
SWB A
UTOMATIC SEND MODE
23
11.2
SWB I
NTERACTIVE SEND MODE
25
12
STROBE / RESET OUTPUT
26
13
TEST AT EM - ACTIVE SUPPLY CURRENT TEST 26
14
METAL MASK OPTIONS
27
15
28
15
PERIPHERAL MEMORY MAP
28
16
ELECTRICAL SPECIFICATIONS
30
16.1
A
BSOLUTE MAXIMUM RATINGS
30
16.2
S
TANDARD
O
PERATING
C
ONDITIONS
30
16.3
H
ANDLING
P
ROCEDURES
30
16.4
DC
CHARACTERISTICS
- P
OWER
S
UPPLY
P
INS
30
16.5
DC
CHARACTERISTICS
- I
NPUT
/O
UTPUT
P
INS
31
16.6
DC
CHARACTERISTICS
- S
UPPLY
V
OLTAGE
D
ETECTOR
L
EVELS
32
16.7
O
SCILLATOR
33
16.8
I
NPUT
T
IMING CHARACTERISTICS
33
17
PAD LOCATION DIAGRAM
34
18
PACKAGE AND ORDERING INFORMATION
34
18.1 O
RDERING
I
NFORMATION
36
18.2
P
ACKAGE
M
ARKING
36
18.3
C
USTOMER
M
ARKING
36
19
SPECIFICATION CHANGE
37
Table of Figures
Figure 1.Architecture
1
Figure 2.Pin Configuration
1
Figure 3.Typical Configuration
4
Figure 4.Mode Transition diagram
5
Figure 5.System reset generation
6
Figure 6.Port A
10
Figure 7.Port B
11
Figure 8.Port C
13
Figure 9.Port D
14
Figure 10.Timer / Event Counter
16
Figure 11.Interrupt Request generation
19
Figure 12.Serial write buffer
22
Figure 13.Automatic Serial Write Buffer transmission
23
Figure 14.Interactive Serial Write Buffer transmission
25
Figure 15. EM6603 PAD Location Diagram
34
Figure 16. Dimensions of PDIP24 Pack. - Pack. type "A"
34
Figure 17. Dimensions of TSSOP24 Pack. - Pack. type "F"
35
Figure 18. Dimensions of SOP24 Pack. SOIC Pack. type "B"
35
Table of Tables
Table 1. Pin Description
4
Table 2.StandBy and Sleep Activities
5
Table 3. PortA Inputs RESET options (metal Hardware option)
7
Table 4. Watchdog-Timer Option (software option)
7
Table 5. Initial Value After RESET
7
Table 6.Prescaler interrupt source
8
Table 7. Prescaler control register - PRESC
8
Table 8.Watchdog register - WD
8
Table 9.Input / Output Ports Overview
9
Table 10.Option register - Option
9
Table 11.PortA input status register - PortA
10
Table 12.PortA Interrupt request register - IRQpA
10
Table 13.PortA interrupt mask register - MportA
10
Table 14.PortB input status register - PortB
11
Table 15.PortB Input/Output control register - CIOportB
11
Table 16.Ports A&C Interrupt Request
12
Table 17.PortC input/output register - PortC
12
Table 18.PortC Interrupt request register - IRQpC
12
Table 19.PortC interrupt mask register - MportC
12
Table 20.PortD Input/Output register - PortD
14
Table 21.Ports control register - CPIOB
14
Table 22.Buzzer frequency selection
15
Table 23.Buzzer control register - BEEP
15
Table 24.Timer Clock Selection
17
Table 25.Timer control register - TimCtr
17
Table 26.LOW Timer Load/Status register -LTimLS (4 low bits)
17
Table 27.HIGH Timer Load/Status register-HTimLS (4 high bits)
17
Table 28.PA3 counter input selection register - PA3cnt
17
Table 29.PA3 counter input selection
17
Table 30.Main Interrupt request register - IntRq (Read Only)*
18
Table 31.register - CIRQD
19
Table 32. SVLD level selection
20
Table 33.SVLD control register - SVLD
20
Table 34.SWB clock selection
21
Table 35.SWB clock selection register - ClkSWB
21
Table 36.PortD status
21
Table 37.SWB buffer register - SWbuff
22
Table 38.SWB Low size register - LowSWB
22
Table 39.SWB High size register - HighSWB
22
Table 40 Input/Output Ports
27
Table 41 PortA RESET option
27
Table 42 SVLD levels
27
EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
Table 1. Pin Description
Pin Number Pin Name
Function
Remarks
1
port A, 0
input 0 port A
interrupt request; tvar 1
2
port A, 1
input 1 port A
interrupt request; tvar 2
3
port A, 2
input 2 port A
interrupt request; tvar 3
4
port A, 3
input 3 port A
interrupt request; event counter input
5
port B, 0
input / output 0 port B
buzzer output
6
port B, 1
input / output 1 port B
7
port B, 2
input / output 2 port B
8
port B, 3
input / output 3 port B
9
test
test input terminal
for EM test purpose only (internal pull-down)
10
Qout/osc 1
crystal terminal 1
11
Qin/osc 2
crystal terminal 2 (input)
Can accept trimming capacitor tw. Vss
12
Vss
negative power supply terminal
13
STB/RST
strobe / reset status
C reset state + port B, C, D write
14
port C, 0
input / output 0 port C
interrupt request
15
port C, 1
input / output 1 port C
interrupt request
16
port C, 2
input / output 2 port C
interrupt request
17
port C, 3
input / output 3 port C
interrupt request
18
port D, 0
input / output 0 port D
SWB Serial Clock Output
19
port D, 1
input / output 1 port D
SWB Serial Data Output
20
port D, 2
input / output 2 port D
21
port D, 3
input / output 3 port D
22
reset
reset terminal
Active high (internal pull-down)
23
Vreg
internal voltage regulator
Needs typ. 100nF capacitor tw. Vss
24
Vdd
positive power supply terminal
Figure 3.Typical Configuration
For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg
For Vdd>1.8V then the configuration shown in Fig.3 should be used.
EM6603
03/02 REV. G/439
Copyright
2002, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
1 Operating
modes
The EM6603 has two low power dissipation modes:
STANDBY and SLEEP. Figure 4 is a transition
diagram for these modes.
1.1 STANDBY
Mode
Executing a HALT instruction puts the EM6603 into
STANDBY mode. The voltage regulator, oscillator,
Watchdog timer, interrupts and timer/event counter are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers, RAM,
and I/O pins retain their states prior to STANDBY
mode. STANDBY is cancelled by a RESET or an
Interrupt request if enabled.
1.2 SLEEP
MODE
Writing to the SLEEP* bit in the IntRq* register puts
the EM6603 in SLEEP mode. The oscillator stops and
most functions of the EM6603 are inactive. To be able
to write the SLEEP bit, the SLmask bit must first be
set to 1. In SLEEP mode only the voltage regulator
and RESET input are active. The RAM data integrity is
maintained. SLEEP mode may be cancelled only by a
RESET at the terminal pin of the EM6603. The RESET
must be high for at least 2sec.
Figure 4.Mode Transition diagram
Table 2 : shows the state of the EM6603 functions in
STANDBY and SLEEP modes.
Table 2.StandBy and Sleep Activities
FUNCTION
STANDBY SLEEP
Oscillator
Active
Stopped
Instruction Execution Stopped
Stopped
Registers and Flags
Retained
Reset
Interrupt Functions
Active
Stopped
RAM
Retained
Retained
Timer/Counter
Active
Stopped
Watchdog
Active
Stopped
I/O pins
Active
High-Z or
Retained
Supply VLD
Stopped
Stopped
Reset pin
Active
Active
Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to
guarantee that the oscillator has started correctly. During this time the circuit is in RESET and the strobe output
STB/RST is high. Waking up from SLEEP mode clears the SLEEP flag but not the SLmask bit. By reading
SLmask one can therefore determine if the EM6603 was powered up (SLmask = 0), or woken from SLEEP mode
(SLmask = 1).
2 Power
Supply
The EM6603 is supplied by a single external power supply between Vdd and Vss, the circuit reference being at
Vss (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the oscillator and internal
logic. Output drivers are supplied directly from the external supply Vdd. A typical connection configuration is shown
in Figure 3.
For Vdd less then 1.4V it is recommended that Vdd is connected directly to Vreg
For Vdd>1.8V then the configuration shown in Fig.3 should be used.
*registers are marked in bold and underlined like
IntRq
*Bits/Flags in registers are marked in bold only like SLEEP
PDF 
ZIP