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Электронный компонент: EM6607

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R
EM6607
Copyright 2005, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Ultra-low power microcontroller
with 4 high drive outputs
Features
Low Power
typical 1.8A active mode
typical 0.5A standby mode
typical 0.1A sleep mode
@ 1.5V, 32kHz, 25 C
Low Voltage 1.2 to 3.3 V
ROM
2k
16 (Mask Programmed)
RAM
96
4 (User Read/Write)
2 clocks per instruction cycle
RISC
architecture
5 software configurable 4-bit ports
1 High drive output port
Up to 20 inputs
(5 ports)
Up to 16 outputs
(4 ports)
buzzer three tone
Serial Write buffer SWB
Supply Voltage level detection (SVLD).
Analogue and timer watchdog
8 bit timer / event counter
Internal interrupt sources (timer, event counter,
prescaler)
External interrupt sources (portA + portC)

Description
The EM6607 is a single chip low power, mask
programmed CMOS 4-bit microcontroller. It contains
ROM, RAM, watchdog timer, oscillation detection circuit,
combined timer / event counter, prescaler, voltage level
detector and a number of clock functions. Its low voltage
and low power operation make it the most suitable
controller for battery, stand alone and mobile equipment.
The EM6607 microcontroller is manufactured using EM's
Advanced Low Power CMOS Process.
In 24 Pin package it is direct replacement for EM6603.

Typical Applications
sensor
interfaces
domestic
appliances
clocks
security
systems
bicycle
computers
automotive
controls
TV & audio remote controls
measurement
equipment
R/F and IR. control
motor
driving





Figure 1.
Architecture
Core
EM6600
32KHz
Crystal Osc
ROM
2k X 16Bit
RAM
96 X 4Bit
Power
Supply
VLD 3 Levels
8-Bit Event
Count/Timer
Interrupt
Controller
Port A
Power on
Reset
0
2
1
3
V
DD
Clk
Port B
0
2
1
3
Port C
0
2
1
3
Port D
0
2
1
3
Port E
0
2
1
3
High Drive
Outputs
V
REG
V
SS
Watchdog
Timer
3 Tone
Buzzer
Prescaler
Data
Buzzer
Serial Write
Buffer
Figure 2. Pin Configuration
(TS)SOP-28
EM6680
P
B2
P
B3
P
E1
T
EST
Q
OUT
Q
IN
V
SS
8
9
10
11
12
13
14
20
19
18
17
16
15
27
26
25
24
23
22
28
21
P
A0
P
A1
P
A2
P
A3
1
2
3
4
5
6
7
P
E0
P
B0
P
B1
P
D0
P
E2
P
C3
P
C2
P
C1
P
C0
S
TB/
R
ST
V
DD
V
REG
R
ESET
P
E3
P
D3
P
D2
P
D1
EM6607
P
B3
T
EST
Q
OUT
Q
IN
V
SS
8
9
10
11
12
16
15
14
13
23
22
21
20
19
18
24
17
P
A0
P
A1
P
A2
P
A3
1
2
3
4
5
6
7
P
B0
P
B1
P
B2
P
C3
P
C2
P
C1
P
C0
S
TB/
R
ST
V
DD
V
REG
R
ESET
P
D3
P
D2
P
D1
P
D0
EM6607
(TS)SOP-24
EM MICROELECTRONIC -
MARIN SA
R
EM6607
Copyright 2005, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6607 at a glance
Power Supply
- Low Voltage, low power architecture
including internal voltage regulator
- 1.2V ... 3.3 V battery voltage
- 1.8
A in active mode
- 0.5
A in standby mode
- 0.1
A in sleep mode @ 1.5V, 32kHz, 25 C
- 32 kHz Oscillator or external clock
RAM
- 96 x 4 bit, direct addressable
ROM
- 2048 x 16 bit metal mask programmable
CPU
- 4 bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
Main Operating Modes and Resets
- Active mode
(CPU is running)
- Standby mode
(CPU in Halt)
- Sleep mode
(No clock, Reset State)
- Initial reset on Power-On (POR)
- External reset pin
- Watchdog timer (time-out) reset
- Oscillation detection watchdog reset
- Reset with input combination on PortA
4-Bit Input PortA
- Direct input read
- Debounced or direct input selectable (reg.)
- Interrupt request on input's rising or falling edge, selectable by
register.
- Pull-down or Pull-up selectable by metal mask
- Software test variables for conditional jumps
- PA3 input for the event counter
- Reset with input combination on PortA (metal option)
4-Bit Input/Output PortB
- Separate input or output selection by register
- Pull-up, Pull-down or none, selectable by metal mask if used as
Input
- Buzzer output on PB0 (24-pin) / PE0 (28-pin)
4-Bit Input/Output PortC
- Input or Output port as a whole port
- Debounced or direct input selectable (reg.)
- Interrupt request on input's rising or falling edge, selectable by
register.
- Pull-up, pull-down or none, selectable by
metal mask if used as input
- CMOS or N-channel open drain mode











4-Bit Input/Output PortD
- Input or Output port as a whole port
- Pull-up, Pull-down or none, selectable by metal mask if
used as Input
- CMOS or N-channel open drain mode
- Serial Write Buffer clock and data output
4-Bit Input/Output PortE
- Separate input or output selection by register
- Pull-up, Pull-down or none, selectable by metal mask if
used as Input

Serial (output) Write Buffer
- max. 256 bits long clocked with 16/8/2/1kHz
- automatic send mode
- interactive send mode : interrupt request
when buffer is empty
Buzzer Output
- if used output on PB0 (24 pin) or PE0 (28 pin)
- 3 tone buzzer - 1kHz, 2kHz, 2.66kHz/4kHz (TBC)
Prescaler
-
32kHz output possible on the STB/RST pin
-
15 stage system clock divider down to 1 Hz
- 3 interrupt requests: 1Hz/8Hz/32Hz
- Prescaler reset (from 8kHz to 1Hz)
8-bit Timer / Event Counter
-
8-bit auto-reload count-down timer
- 6 different clocks from prescaler
- or event counter from the PA3 input
- parallel load
- interrupt request when comes to 00 hex.

Supply Voltage Level Detector
- 3 software selectable levels (1.3V, 2.0V,
2.3V or user defined between 1.3V and 3.0V)
- Busy flag during measure
- Active only on request during measurement to reduce
power consumption
Interrupt Controller
-
9 external interrupt sources: 4 from PortA, 4 from PortC.
- 3 internal interrupt sources, prescaler, timer and Serial
Write Buffer
- Each interrupt request is individually selectable
- Interrupt request flag is cleared automatically on register
read
R
EM6607
Copyright 2005, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
Table of Contents
1
PIN DESCRIPTION FOR EM6607
0H
5
2
OPERATING MODES
1H
7
2.1
A
CTIVE
M
ODE
2H
7
2.2
STANDBY
M
ODE
3H
7
2.3
SLEEP
MODE
4H
7
3
POWER SUPPLY
5H
8
4
RESET
6H
9
4.1
O
SCILLATION DETECTION CIRCUIT
7H
9
4.2
R
ESET
P
IN
8H
9
4.3
I
NPUT PORT
(PA0..PA3)
RESET
9H
10
4.4
W
ATCHDOG
T
IMER
RESET
10H
10
4.5
S
OFTWARE
P
OWER
-O
N
-R
ESET
11H
10
4.6
CPU
S
TATE AFTER
RESET
12H
11
4.7
POR
WITH
P
OWER
-C
HECK
R
ESET
13H
11
5
OSCILLATOR
14H
12
5.1
P
RESCALER
15H
12
6
WATCHDOG TIMER
16H
12
7
INPUT AND OUTPUT PORTS
17H
13
7.1
P
ORT
A
18H
13
7.1.1
PortA registers
19H
14
7.2
P
ORT
B
20H
15
7.2.1
PortB registers
21H
15
7.3
P
ORT
C
22H
16
7.3.1
PortC registers
23H
16
7.4
P
ORT
D
24H
18
7.4.1
PortD registers
25H
18
7.5
P
ORT
E
26H
19
7.5.1
PortE registers
27H
19
8
BUZZER
28H
20
8.1
B
UZZER
R
EGISTER
29H
20
9
TIMER/EVENT COUNTER
30H
21
9.1
T
IMER
/C
OUNTER REGISTERS
31H
22
10
INTERRUPT CONTROLLER
32H
23
10.1
I
NTERRUPT CONTROL REGISTERS
33H
23
11
SUPPLY VOLTAGE LEVEL DETECTOR (SVLD)
34H
25
12
SERIAL WRITE BUFFER SWB
35H
26
12.1
SWB
A
UTOMATIC SEND MODE
36H
28
12.2
SWB
I
NTERACTIVE SEND MODE
37H
29
13
STROBE / RESET OUTPUT
38H
30
14
TEST AT EM - ACTIVE SUPPLY CURRENT TEST
39H
30
15
METAL MASK OPTIONS
40H
31
15.1.1
Power-Check Level Option
41H
32
15.1.2
PortA reset Option, see paragraph 3.3
42H
32
15.1.3
SVLD levels Option, see paragraph 10.0 SVLD
43H
32
16
PERIPHERAL MEMORY MAP
44H
33
17
TEMPERATURE AND VOLTAGE BEHAVIOURS
45H
36
17.1
IDD
C
URRENT
(T
YPICAL
)
46H
36
17.2
P
ULL
-
DOWN RESISTANCE
(T
YPICAL
)
47H
37
17.3
O
UTPUT
C
URRENTS
(T
YPICAL
)
48H
38
18
ELECTRICAL SPECIFICATIONS
49H
40
18.1
A
BSOLUTE MAXIMUM RATINGS
50H
40
18.2
S
TANDARD
O
PERATING
C
ONDITIONS
51H
40
18.3
H
ANDLING
P
ROCEDURES
52H
40
18.4
DC
CHARACTERISTICS
-
P
OWER
S
UPPLY
P
INS
53H
40
18.5
DC
CHARACTERISTICS
-
I
NPUT
/O
UTPUT
P
INS
54H
42
18.6
DC
CHARACTERISTICS
-
S
UPPLY
V
OLTAGE
D
ETECTOR
L
EVELS
55H
43
18.7
O
SCILLATOR
56H
43
18.8
I
NPUT
T
IMING CHARACTERISTICS
57H
43
19
PAD LOCATION DIAGRAM
58H
44
20
PACKAGE DIMENSIONS
59H
45
21
ORDERING INFORMATION
60H
47
21.1
P
ACKAGE
M
ARKING
61H
47
21.2
C
USTOMER
M
ARKING
62H
47

Table of Figures
Figure 1. Architecture
63H
1
Figure 2. Pin Configuration
64H
1
Figure 3. Typical Configuration: V
DD
1.4V up to 3.3V
65H
6
Figure 4. Typical Configuration: V
DD
1.2V up to 1.8V
66H
6
Figure 5. Mode Transition Diagram
67H
7
Figure 6. System reset generation
68H
9
Figure 7. Port A
69H
14
Figure 8. Port B
70H
15
Figure 9. Port C
71H
17
Figure 10. Port D
72H
18
Figure 11. Port E
73H
19
Figure 12. Timer / Event Counter
74H
21
Figure 13. Interrupt Request generation
75H
24
Figure 14. Serial write buffer
76H
27
Figure 15. Automatic Serial Write Buffer transmission
77H
28
Figure 16. Interactive Serial Write Buffer transmission
78H
29
Figure 17. Dimensions of SOP24 Package SOIC
79H
45
Figure 18. Dimensions of TSSOP24 Package
80H
45
Figure 19. Dimensions of SOP28 Package SOIC
81H
46
Figure 20. Dimensions of TSSOP28 Package
82H
46
R
EM6607
Copyright 2005, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
Table of Tables
Table 1.
IntRq register
83H
7
Table 2. Watchdog register - WD
84H
8
Table 3. Internal state in Active, Stand-by and Sleep mode
85H
8
Table 4. PortA Inputs RESET options (metal Hardware option)
86H
10
Table 5. Watchdog-Timer Option (software option)
87H
10
Table 6. Software Power-On-Reset
88H
10
Table 7.
Initial Value after RESET
89H
11
Table 8. Prescaler interrupts source
90H
12
Table 9. Prescaler control register - PRESC
91H
12
Table 10. Watchdog register - WD
92H
12
Table 11. Input / Output Ports Overview
93H
13
Table 12. Option register - Option
94H
13
Table 13. PortA input status register - PortA
95H
14
Table 14. PortA Interrupt request register - IRQpA
96H
14
Table 15. PortA interrupt mask register - MportA
97H
14
Table 16. PortB input/output status register - PortB
98H
15
Table 17. PortB Input/Output control register - CIOportB
99H
15
Table 18. Ports A&C Interrupt
100H
16
Table 19. PortC input/output register - PortC
101H
16
Table 20. PortC Interrupt request register - IRQpC
102H
16
Table 21. PortC interrupt mask register - MportC
103H
16
Table 22. Option2 register - Option2
104H
17
Table 23. PortD Input/Output register - PortD
105H
18
Table 24. Ports control register - CPIOB
106H
18
Table 25. PortE Input/Output status register - PortE
107H
19
Table 26. PortE Input/Output control register - CIOPortE
108H
19
Table 27. Buzzer control register - BEEP
109H
20
Table 28. Buzzer output pad allocation
110H
20
Table 29. PB0 & PE0 function used with BUen and BuzzerPE0
control bits
111H
20
Table 30. Timer Clock Selection
112H
22
Table 31. Timer control register - TimCtr
113H
22
Table 32. LOW Timer Load/Status register - LTimLS (4 low bits)
114H
22
Table 33. HIGH Timer Load/Status register - HTimLS (4 high bits)
115H
22
Table 34. PA3 counter input selection register - PA3cnt
116H
22
Table 35. PA3 counter input selection
117H
22
Table 36. Main Interrupt request register - IntRq (Read Only)*
118H
23
Table 37. Register - CIRQD
119H
24
Table 38. SVLD Level selection
120H
25
Table 39. SVLD control register - SVLD
121H
25
Table 40. SWB clock selection
122H
26
Table 41. SWB clock selection register - ClkSWB
123H
26
Table 42. PortD status
124H
26
Table 43. SWB buffer register - SWbuff
125H
27
Table 44. SWB Low size register - LowSWB
126H
27
Table 45. SWB High size register HighSWB
127H
27
Table 46. input/output Ports
128H
31
Table 47. PortB Hi Current Drive capability
129H
31
R
EM6607
Copyright 2005, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
1
Pin Description for EM6607

Pin Nb
24 pin
Pin Nb
28 pin
Pin Name
Function
Remarks
1
1
port A, 0
input 0 port A
interrupt request; tvar 1
2
2
port A, 1
input 1 port A
interrupt request; tvar 2
3
3
port A, 2
input 2 port A
interrupt request; tvar 3
4
4
port A, 3
input 3 port A
interrupt request; event counter input
-
5
port E, 0
input / output 0 port E
buzzer output in 28 pin package
5
6
port B, 0
input / output 0 port B
buzzer output in 24 pin package
6
7
port B, 1
input / output 1 port B
7
8
port B, 2
input / output 2 port B
8
9
port B, 3
input / output 3 port B
-
10
port E, 1
input / output 1 port E
9
11
test
test input terminal
for EM test purpose only (internal pull-down)
10 12
Q
out
/osc 1
crystal terminal 1
11 13 Q
in
/osc 2
crystal terminal 2 (input)
Can accept trimming capacitor tw. V
SS
12 14 V
SS
negative power supply terminal
13
15
STB/RST
strobe / reset status
C reset state + port B, C, D write
14
16
port C, 0
input / output 0 port C
interrupt request
15
17
port C, 1
input / output 1 port C
interrupt request
16
18
port C, 2
input / output 2 port C
interrupt request
17
19
port C, 3
input / output 3 port C
interrupt request
-
20
port E, 2
input / output 2 port E
18
21
port D, 0
input / output 0 port D
SWB Serial Clock Output
19
22
port D, 1
input / output 1 port D
SWB Serial Data Output
20
23
port D, 2
input / output 2 port D
21
24
port D, 3
input / output 3 port D
-
25
port E, 3
input / output 3 port E
22 26 RESET
reset
terminal
Active high (internal pull-down)
23 27 V
REG
internal voltage regulator
Needs typ. 100nF capacitor tw. V
SS
24 28 V
DD
positive power supply terminal
Table 1.
Pin Description