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Электронный компонент: H6006A2SO8B

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R



H6006

Copyright 2004, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
Failsafe Watchdog

Description
The H6006 is a monolithic low power CMOS device
combining a programmable digital timer and a series of
voltage comparators on the same chip. The device is
specially convenient for Watch-Dog functions such as
microprocessor and supply voltage monitoring. The
watchdog part is designed to be used in all applications
where it is important that after the occurrence of a
malfunction the microprocessor system is stopped to avoid
further damage. The timeout warning signal ( TO ) can be
used to try to reactivate the system before halting it. The
voltage monitoring part provides double security by
combining both unregulated voltage and regulated voltage
monitoring simultaneously. The H6006 initializes the power-
on reset after V
IN
reached V
SH
and V
DD
raises above 3.5 V. If
V
IN
drops below V
SL
, the H6006 gives an advanced warning
signal for register saving and if the voltage drops further
below V
RL
, RES goes active. The H6006 functions at any
supply voltage down to 1.5 V and is therefore particularly
suited for start-up and shut-down control of microprocessor
systems
Features
Failsafe watchdog function: timeout warning after 1st
timeout period, reset after 2nd timeout period, reset
remains active to avoid further failures
Standard timeout period and power-on reset time
(10 ms), externally programmable if required
V
IN
monitoring with 3 standard or programmable trigger
voltages for: power-on reset initialization, advanced
power-fail warning ( SAVE ), reset at power-down ( RES )
V
DD
monitoring: power-on reset initialization enabled
only if V
DD
3.5 V
Internal voltage reference
Works down to 1.5 V supply voltage
Push-pull or Open drain outputs
Low current consumption
Available for normal and extended temperature range
SO8 package
Applications
Microprocessor and microcontroller systems
Point of sales equipment
Telecom products
Automotive subsystems
Typical Operating Configuration
Pin Assignment

EM MICROELECTRONIC -
MARIN SA
Voltage
Regulator
5 V
H6006
GND
Fig. 1
Micro-
processor
I/O
V
DD
TO
SAVE
RES
V
IN
TCL
V
SS
INT
NMI
RES
SO8
V
DD
H6006
Fig. 2
V
IN
TCL
RC
V
SS
TO
SAVE
RES
R



H6006

Copyright 2004, EM Microelectronic-Marin SA
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Absolute Maximum Ratings
Parameter
Symbol Conditions
Voltage V
DD
to V
SS
V
DD
-0.3 to +8 V
Voltage at any pin to V
SS
V
MIN
-0.3
Voltage at any pin to V
DD
(except
V
IN
)
V
MAX
+0.3
Voltage at V
IN
to V
SS
V
INMAX
+15
V
Current at any output
I
MAX
10 mA
Storage temperature
T
STO
-65...
+150
C
Table 1
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond
specified operating conditions may affect device reliability or
cause malfunction.
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component.
Unless otherwise specified, proper operation can only occur
when all terminal voltages are kept within the supply voltage
range. Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Parameter
Symbol Min. Typ Max. Units
Operating
temperature
Industrial
T
AI
-40 +85
C
Supply voltage
V
DD
1.5 5.5 V
Comparator input
voltage
Version A2, A3,
B2,B3
V
IN
0 V
DD
V
Version B1
V
IN
0 12 V
RC-oscillator
programming
(see Fig. 15)
External capacitance
C1
100
nF
External resistance
R1
10
k
Table 2
Electrical Characteristics
V
DD
= 5.0 V, T
A
= -40 to +85
C, unless otherwise specified
Parameter Symbol
Test
Conditions Min.
Typ.
Max.
Units
V
DD
activation threshold
V
ON
T
A
= 25
C 3
3.5
V
V
DD
deactivation threshold
V
OFF
T
A
= 25
C
V
ON
- 1.5
V
Supply current
I
DD
RC open, TCL= 5 V, V
IN
= 0 V
50
140
A
Input V
IN
,, TCL
Leakage current
I
IP
V
SS
V
IP
V
DD
;
T
A
= 85
C
0.005
1
A
Input current on pin V
IN
I
IN
Version B1; V
IN
= 10 V
100
180
A
TCL input low level
V
IL
0.8 V
TCL input high level
V
IH
2.4
V
TO
, RES . SAVE Outputs
Leakage current
I
OLK
Versions A2, A3;
V
OUT
= V
DD
0
.05
1
A
Drive currents (all versions)
I
OL
V
OL
= 0.4 V
3.2
8
mA
I
OL
V
DD
= 3.5 V; V
OL
= 0.4 V
2
mA
I
OL
V
DD
= 1.6 V; V
OL
= 0.4 V
80
A
Drive currents
I
OH
V
OH
= 4.0 V
3.2
8
mA
(versions B1, B2, B3)
1)
I
OH
V
DD
= 3.5 V; V
OH
2.8 V
2
mA
I
OH
V
DD
= 1.6 V; V
OH
= V
DD
-0.4 80
A
1)
Versions: An = open drain outputs; Bn = push-pull outputs
Table 3
V
IN
Surveillance
Voltage thresholds at T
A
= 25
C
Version
1)
Comparator
Reference
Input Resistance
R
VIN
Thresholds
Threshold
Tolerance
Ratio
Tolerance
3)
B1 V
DD
100k
9.00 8.00 7.00
2)
5%
+2%
A2, B2
V
DD
~100M
2.25 2.00 1.75
2)
5%
+2%
A3, B3
Band-gap reference
~100M
2.00 1.95 1.90
10%
+2%
1)
Versions: An = open drain outputs; Bn = push-pull outputs
2)
at V
DD
= 5 V
3)
Threshold ratio as V
SH
/V
SL
or V
SL
/V
RL
Table 4
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H6006

Copyright 2004, EM Microelectronic-Marin SA
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Timing Characteristics
V
DD
= 5.0 V, T
A
=
-40 C to +85 C, unless otherwise specified
Parameter Symbol
Test
Conditions Min.
Typ.
Max.
Units
Propagation delays
TCL to output pins
T
DIDO
250 500 ns
V
IN
to output pins
T
AIDO
Excluding debounce time T
DB
4
10
s
Logic transition times on all
output pins
T
TR
Load 10 k
, 100 pF
30
100 ns
Timeout period
T
TO
RC open, unshielded , T
A
=25
C
6 10 16 ms
T
TO
RC open, unshielded (not tested)
4.5
20
ms
T
TCL
input pulse width
T
TCL
150 ns
Power-on reset debounce
T
DB
T
TO/32
ms
Table 5
Timing Waveforms
Voltage Reaction: V
DD
Monitoring
Voltage Reaction: V
IN
Monitoring
V
ON

V
OFF
V
DD
V
IN
monitoring enabled
Fig. 3
V
SH
V
SL
V
RL
0
SAVE
Conditions:
V
DD
> V
ON
No timeout
V
IN
T
TO
T
TO
T
DB
T
DB
Timer
Start
Power-on
Reset
Timer
Stop
Timer
Start
Power-on
Reset
No Power-on
Reset
(as V
IN
> V
RL
)
Fig. 4
RES
R



H6006

Copyright 2004, EM Microelectronic-Marin SA
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Timer Reaction
Combined Voltage and Timer Reaction
Block Diagram
______
TCL
T
TCL
T
TO
Conditions:
V
IN
> V
RL
after
power-up sequence.
Timer
Reset
Timer
Reset
Timer
Reset
TO
Timeout
RES
Timeout
Fig. 5
TO
RES
T
TO
T
TO
V
IN
V
SH
T
DB
SAVE
T
TO
Power-on
Reset
TO
Timeout
RES
Timeout
TO
Timeout
Timer
Stop
Timer
Reset
Fig. 6
V
SL
V
RL
RES
TO
TCL
T
TO
T
TO
T
TO
OSC
Timer
TCL
TO
Save
Control
RES
Reset
Control
SAVE
Band-Gap
Reference
V
IN
1
2
V
DD
V
SH
V
SL
V
RL
V
SS
3
Fig. 7
RC
Version Connections
B1
A2, B2
A3, B3
1 and 3
1
2
R



H6006

Copyright 2004, EM Microelectronic-Marin SA
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Pin Description
Pin Name Function
1 V
IN
Voltage monitoring input
2
TCL
Timer clear input signal
3
RC
RC oscillator tuning input
4 V
SS
GND
terminal
5
RES Reset
output
6
SAVE Save
output
7
TO
Timer output signal
8 V
DD
Positive supply voltage terminal
Table 6
Functional Description
Supply Lines
The circuit is powered through the V
DD
and V
SS
pins. It
monitors both its own V
DD
supply and a voltage applied to the
V
IN
input.
V
DD
Monitoring
During power-up the V
IN
monitoring is disabled and RES and
SAVE stay active low as long as V
DD
is below V
ON
(3.5 V). As
soon as V
DD
reaches the V
ON
level, the state of the outputs
depend on the watchdog timer and the volt-age at V
IN
relative
to the thresholds (see Fig. 3 and 4). If the supply voltage V
DD
falls back below V
OFF
(1.5 V) the watchdog timer and the V
IN
monitoring are disabled and the outputs SAVE and RES are
active low. The V
DD
line should be free of spikes.
V
IN
Monitoring
The analog voltage comparators compare the voltage applied
to V
IN
(typically connected to the input of the voltage regulator)
with the stabilized supply voltage V
DD
(versions B1, A2, B2) or
with the bandgap voltage (versions A3, B3) (see Fig. 7). At
power-up, when V
DD
reached V
ON
and V
IN
reaches the V
SH
level, the SAVE output goes high, and the timer starts
running, setting RES high after the time T
TO
(see Fig. 4). If V
IN
falls below V
SL
, the SAVE output goes low and stays low until
V
IN
rises again above V
SH
. If V
IN
falls below the voltage V
RL
, the
RES output will go low and the on-chip timer will stop. When
V
IN
rises again above V
SH
, the timer will initiate a power-up
sequence. The RES output may however be influenced
independently of the voltage V
IN
by the timer action, see
section "Combined Voltage and Timer Action". Monitoring the
rough DC side of the regulator as shown in Fig. 12 is the only
way to have advanced warning at power-down. Spikes on V
IN
should be filtered if they are likely to drop below V
SL.
The combination of V
IN
and V
DD
monitoring provide high
system security: if V
IN
rises much faster than V
DD
, then the
device starts the power-on sequence only when V
DD
reached
V
ON
(Fig. 3). Short circuits on the regulated supply voltage can
be detected.
Voltage Thresholds on V
IN
The H6006 is available with 3 different sets of thresholds
:
Version B1: with internal voltage divider, resulting in
thresholds for direct monitoring of the unregulated voltage
without external components.











Version A2, B2: for monitoring of all unregulated voltage,
where custom programming is required. Fixed resistor
values can be used for programming.

Version A3, B3:
for monitoring of regulated voltage, where
no unregulated voltage is available (the tolerance is
10 %,
see Table 4. For tighter tolerances, trimming can be used,
see Fig. 10).

Voltage
Regulator
any voltage
5 V

V
IN






V
SS

V
DD
H6006 A2, B2
Note : the internal threshold levels are 2.25 / 2.00 / 1.75 V
at V
DD
= 5 V (thresholds dependent on V
DD
)
R
VIN
= ~ 100 M
.
Fig. 9
SAVE
RES
Voltage
Regulator
> 9 V
5 V
V
IN











V
SS
V
DD
H60
06 B1
Note:
The threshold levels are 9/8/7 V normally.These
are divided internally by 4 to give internal thres-
holds of 2.25 / 2 / 1.75 V. V
DD
= 5 V (thresholds
dependent on V
DD
). R
VIN
= ~ 100 k
.
Fig. 8
SAVE
RES
5 V
10%
V
IN


V
SS

V
DD
H6006 A3, B3
Note: the internal threshold levels are 2.00 / 1.95 / 1.90 V
(thresholds dependent on the internal bandgap
reference) R
VIN
= ~ 100 M
.
Fig. 10
SAVE
RES