EM MICROELECTRONIC--MARIN SA

V6173

Accurate Voltage Window Surveillance,

Software Monitoring and Chip Select

Features

Standby mode, maximum current 35

Reset output guaranteed for V

voltage

down to 1.2 V

Comparator for voltage monitoring,
voltage reference 1.17 V

1.5

voltage reference accuracy at + 25

voltage reference accuracy for

40 to +85

Programmable reset voltage monitoring

Voltage window, high threshold 5.9 V

Programmable power-on reset (POR) delay

Watchdog with programmable time window

guarantees a minimum time and a maximum time

between software clearing of the watchdog

Time base accuracy

System enable (EN) output offers added security

3 chip select feed-thru circuit controlled by EN

TTL / CMOS compatible

40 to +85

C temperature range

DIP14 and SO14 packages

Description

The V6173 offers a high level of integration by voltage

monitoring and software monitoring in a 14 lead

package. A comparator monitors the voltage applied at

the V

input comparing it with an internal 1.17 V

reference. The power-on reset function is initialized after

reaches 1.17 V and takes the reset output inactive

after T

POR

depending of external resistance. The reset

output goes active low when the V

voltage is less than

1.17 V or when V

is higher than 5.9 V. The RES and EN

outputs are guaranteed to be in a correct state for a

supply voltage as low as 1.2 V. The watchdog function

monitors software cycle time and execution. If the

software clears the watchdog too quickly (incorrect cycle

time) or too slowly (incorrect execution), it will cause the

system to be reset. The system enable output prevents

critical control functions being activated until software

has successfully cleared the watchdog three times. Such

a security could be used to prevent motor controls being

energized on repeated resets of a faulty system.

Applications

Industrial electronics

Cellular telephones

Security systems

Battery powered products

Automotive electronics

Typical Operating Configuration

Pin Assignment

TCL

Fig. 1

V6173

RES

GND

100 nF

IN3

IN2

IN1

OUT3

OUT2

OUT1

TCL

RES

R
V

Fig. 2

DIP14 / SO14

V6173

OUT3

OUT2

OUT1

IN3

IN2

IN1

V6173

Absolute Maximum Ratings

Parameter

Symbol Conditions

Maximum voltage at V

Minimum voltage at V

Max. voltage at any signal pin

Min. voltage at any signal pin

Storage temperature

Electrostatic discharge max. to

MIL-STD-883C method 3015

Max. soldering conditions

DDmax

DDmin

MAX

MIN

STO

Smax

+ 8 V

0.3 V

+ 0.3 V

0.3 V

-65 to+150

1000 V

250

C x 10 s

Table 1

Stresses above these listed maximum ratings may cause

permanent damage to the device. Exposure beyond

specified operating conditions may affect device

reliability or cause malfunction.

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, anti-static
precautions must be taken as for any other CMOS

component. Unless otherwise specified, proper

operation can only occur when all terminal voltages are

kept within the supply voltage range. Unused inputs

must always be tied to a defined logic voltage level.

Operating Conditions

Parameter

Symbol Min. Typ. Max. Units

Operating temperature

Supply voltage

& guaranteed

Comparator input

voltage

RC-oscillator

programming

-40

1.2

+85

1000

Table 2

A 100 nF decoupling capacitor is required on the

supply voltage V

for stability.

RES must be pulled up externally to V

event if it is

unused.
(Note: RES and EN are used as inputs by EM test.)

Electrical Characteristics

5.5 V, C = 100 nF, T

= -40 to +85

C, unless otherwise specified

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Supply current in standby mode

Supply current

RES, EN and CS

OUT1/2/3

Output Low Voltage

EN and CS

OUT1/2/3

Output High Voltage

TCL , V

and CS

IN1/2/3

TCL and CS

IN1/2/3

Input Low Level

TCL and CS

IN1/2/3

Input High Level

Leakage current TCL input
V

input resistance

Comparator reference

Comparator hysteresis

Level detector of V

Hysteresis

VIN

REF

HY1

HIGH

HIDH

HY2

EXT

= don't care, TCL = V

= 0 V

EXT

= 100 k

, I/Ps at V

O/Ps 1 M

to V

= 4.5 V, I

= 20 mA

= 4.5 V, I

= 8 mA

= 2.0 V, I

= 4 mA

= 1.2 V, I

= 0.5 mA

= 4.5 V, I

1 mA

= 2.0 V, I

100

= 1.2 V, I

5.5 V

TCL

= +25

20 to +70

= +25

40 to +70

3.5

1.8
1.0

2.0

1.148

1.123
1.123

5.78

5.60

0.4
0.2

0.2

0.06

4.1

1.9
1.1

0.05

100

1.170

5.95

100

0.4

0.4
0.2

0.8

1.200

1.218
1.222

6.12

6.30

V
V

The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator

Table3

reference voltage plus the comparator hysteresis (see Fig. 6).

The level detector of V

HIGH

) is the level when V

is rising. The level detector when V

is falling equals V

HIGH

minus

the hysteresis (V

HY2

) (see Fig. 6).

RES

V6173

Standby versus Temperature at V

= 5.5 V

Timing Characteristics

= 5.0 V

, C = 100 nF, T

40 to

C, unless otherwise specified

Parameter

Symbol

Test Conditions

Min.

Typ.

Max. Units

Propagation delays:

to Output Pins
CS

INx

to CS

OUTx

at rising edge

INx

to CS

OUTx

at falling edge

sensitivity

Logic Transition Times on all Output Pins

Power-on Reset delay
Watchdog Time

Open Window Percentage
Closed Window Time

Open Window Time

Watchdog Reset Pulse

Input Pulse Width

DIDO

CSH

CSL

SEN

POR

OWP
T

WDR

TCL

Load 10 k

, 50 pF

EXT

= 118 k

EXT

= 118 k

EXT

= 118 k

EXT

= 118 k

EXT

= 118 k

90
90

150

250
125

100
100

0.2 T

0.8 T

0.4 T

/ 40

2.5

500
200

150

100

110
110

ns
ns

Table 4

Timing Waveforms

Watchdog Timeout Period

TCL

= T

POR

closed window

open window

Watchdog

timer reset

Condition:
R

EXT

= 115 k

OWP

20%

+ OWP

+ 20%

100

120

Fig. 4

t [ms]

24
22

[

Fig. 3

V6173

Pin Description

Pin Name

Function

OUT3

OUT2

OUT1

IN1

IN2

IN3

Push-pull active low chip select output 3

Push-pull active low chip select output 2

Push-pull active low chip select output 1

Push-pull active low enable output

Open drain active low reset output.

must be pulled up to V

even

if unused

Watchdog timer clear input signal

GND terminal

No connection

Voltage supply

EXT

input for RC oscillator tuning

Voltage comparator input

Chip select input 1

Chip select input 2

Chip select input 3

Table 5

Functional Description

Monitoring

The power-on reset and the power-down reset are

generated as a response to the external voltage level on

the V

input. The external voltage level is typically

obtained from a voltage divider as shown in Fig. 10. The

user defines an external voltage divider to set the

desired threshold level for power-on reset and power-

down reset in his system. The internal comparator

reference voltage is typically 1.17 V.

At power-up the reset output (RES)

is held low (see Fig.

6). When V

becomes greater than V

REF

, the RES output

is held low for an additional power-on reset (POR) delay

which is equal to the watchdog time T

(typically 100

ms with an external resistor of 115 k

connected at R

pin). The POR delay prevents repeated toggling of RES

even if V

and the INPUT voltage drops out and

recovers. The POR delay allows the microprocessor's

crystal oscillator to start and stabilize and ensures

correct recognition of the reset signal to the

microprocessor.

The RES output goes active low generating the power-

down reset whenever V

falls below V

REF

. The sensitivity

or reaction time of the internal comparator to the voltage

level on V

is typically 5

Voltage Window

The reset output (RES) is inactive when V

is higher than

REF

and when V

is lower than V

HIGH

. If V

is less than

REF

or V

higher than V

HIGH

, the reset output goes active

low (see Fig. 6).

Timer Programming

The on-chip oscillator needs an external resistor R

EXT

connected between the R pin and V

(see Fig.

10). It

allows the user to

adjust the power-on reset (POR)

delay, watchdog time T

and with this also the closed

and open time windows as well as the watchdog reset

pulse width (T

/40).

With R

EXT

= 115 k

, the typical delays are:

- Power-on reset delay: T

POR

is 100 ms

- Watchdog time:

is 100 ms

- Closed window:

is 80 ms

- Open window:

is 40 ms

- Watchdog reset:

WDR

is 2.5 ms

Note the current consumption increases as the

frequency increases.

Watchdog Timeout Period Description

The watchdog timeout period is divided into two parts, a

"closed" window and an "open" window (see

Fig. 4) and

defined by two parameters, T

and the Open Window

Percentage (OWP).

The closed window starts just after the watchdog timer

resets and is defined by T

= T

OWP(T

The open window starts after the closed time window

finishes and lasts till T

+ OWP(T

). The open window

time is defined by T

= 2 x OWP(T

For example if T

= 100 ms (actual value) and OWP =

20% this means the closed window lasts during first

the 80 ms (T

= 80 ms = 100 ms

0.2 (100 ms)) and

the open window the next 40 ms (T

= 2 x 0.2 (100 ms)

= 40 ms). The watchdog can be serviced between 80

ms and 120 ms after the timer reset. However as the

time base is

10% accurate, software must use the

following calculation for servicing signal TCL during the

open window:

Related to curves (Fig. 11 to Fig. 21), especially Fig. 20

and Fig. 21, the relation between T

and R

EXT

could

easily be defined. Let us take an example describing the

variations due to production and temperature:

1. Choice, T

= 26 ms.

2. Related to Fig. 21, the coefficient (T

to R

EXT

) is 1.125

where R

EXT

is in k

and T

in ms.

3. R

EXT

(typ.) = 26 x 1.125 = 29.3 k

4. 26 ms at +25

(26

10% = 23.4 ms) (26 + 10% = 28.6 ms)

(23.4

5% = 22.2 ms) (28.6 + 5% = 30.0 ms)

min.: (30.0

20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)

Typical TCL period of

(24.0 + 26.7) / 2 = 25.4 ms

The ratio between T

= 26 ms and the (TCL period) =

25.4 ms is 0.975.

EN
RES

RES

TCL

V6173

Then the relation over the production and the full

temperature range is, TCL period = 0.975 x T

or TCL period = , as typical value.

a) While PRODUCTION value unknown for the custo-

mer when R

EXT

118 k

b) While operating TEMPERATURE range

+85

5. If you fixed a TCL period = 26 ms

EXT

= 30 k

If during your production the T

time can be

measured, at T

= +25

C and the

C can adjust

the

TCL period, then

the TCL period range will be much

larger for the full operating temperature.

Timer Clearing and RES Action

The watchdog circuit monitors the activity of the

processor. If the user's software does not send a pulse

to the TCL input within the programmed open window

timeout period, a short watchdog RES pulse is

generated which is equal to T

/40 = 2.5 ms typically

(see Fig. 7).

With the open window constraint, new security is added

to conventional watchdogs by monitoring both software

cycle time and execution. Should software clear the

watchdog too quickly (incorrect cycle time) or too slowly

(incorrect execution), it will cause the system to be reset.

If the software is stuck in a loop which includes the

routine to clear the watchdog, a conventional watchdog

will not reset the system even though the software is

malfunctioning; the V6173 will generate a system reset

because the watchdog is cleared too quickly.

If no TCL pulse is applied before the closed and open

windows expire, RES will start to generate square waves

of period (T

+ T

WDR

). The watchdog will remain

in this state until the next TCL falling edge appears

during an open window, or until a fresh power-up

sequence. The system enable output, EN, can be used

to prevent critical control

functions being activated in the

event of the system going into this failure mode (see

section "Enable

EN Output").

The RES output must be pulled up to V

even if the

output is not used by the system (see Fig. 10).

Combined Voltage and Timer Action

The combination of voltage and timer actions is

illustrated by the sequence of events shown in Fig. 8. On

power-up, when the voltage at V

reaches V

REF

, the

power-on reset, POR, delay is initialized and holds RES

active for the time of the POR delay. A TCL pulse will

have no effect until this power-on reset delay is

completed. After the POR delay has elapsed, RES goes

inactive and the watchdog timer starts acting. If no TCL

pulse occurs, RES goes active low for a short time T

WDR

after each closed and open window period. A TCL pulse

coming during the open window clears the watchdog

timer. When the TCL pulse occurs too early (during the

closed window), RES goes active and a new timeout

sequence starts. A voltage drop below the V

REF

level for

longer than

typically 5

s, overrides the timer and

immediately forces RES active and EN inactive. Any

further TCL pulse has no effect until the next power-up

sequence has completed.

Enable

EN Output

The system enable output, EN, is inactive always when

RES is active and remains inactive after a RES pulse

until the watchdog is serviced correctly 3 consecutive

times (ie. the TCL pulse must come in the open

window). After three consecutive services of the

watchdog

with TCL during the open window, the EN

goes active low.

A malfunctioning system would be repeatedly reset by

the watchdog. In a conventional system critical motor

controls could be energized each time reset goes

inactive (time allowed for the system to restart) and in

this way the electrical motors driven by the system could

function out of control. The V6173 prevents the above

failure mode by using the EN output to disable the motor

controls until software has successfully cleared the

watchdog three times (ie. the system has correctly

restarted after a reset condition)

0.975 x R

EXT

1.125

26 x 1.125

0.975

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: V6173

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: V6173