Document Outline

• S1D13706 TECHNICAL MANUAL
  • COMPREHENSIVE SUPPORT TOOLS
    • Documentation
    • Evaluation/Demonstration Board
  • Application Engineering Support
    • Application Engineering Support
• Product Brief
  • FEATURES
  • System Block Diagram
  • DESCRIPTION
    • Memory Interface
    • CPU Interface
    • Display Support
    • Clock Source
    • Display Modes
    • Power Down Modes
    • Operating Voltage
    • Package
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 Features
    • 2.1 Integrated Frame Buffer
    • 2.2 CPU Interface
    • 2.3 Display Support
    • 2.4 Display Modes
    • 2.5 Display Features
    • 2.6 Clock Source
    • 2.7 Miscellaneous
  • 3 Typical System Implementation Diagrams
    • Figure 31: Typical System Diagram (Generic #1 Bus)
    • Figure 32: Typical System Diagram (Generic #2 Bus)
    • Figure 33: Typical System Diagram (Hitachi SH-4 Bus)
    • Figure 34: Typical System Diagram (Hitachi SH-3 Bus)
    • Figure 35: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
    • Figure 36: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)
    • Figure 37: Typical System Diagram (Motorola REDCAP2 Bus)
    • Figure 38: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 �DragonBall� Bus)
  • 4 Pins
    • 4.1 Pinout Diagram - TQFP15 - 100pin
      • Figure 41: Pinout Diagram - TQFP15 - 100pin (S1D13706F00A)
    • 4.2 Pinout Diagram - CFLGA - 104pin
      • Figure 42: Pinout Diagram - CFLGA - 104pin (S1D13706B00A)
      • Table 41: CFLGA Pin Mapping
    • 4.3 Pinout Diagram - Die Form
      • Figure 43: Pinout Diagram - Die Form (S1D13706D00A)
      • Table 42: Pinout Assignments - Die Form (S1D13706D00A)
    • 4.4 Pin Descriptions
      • 4.4.1 Host Interface
        • Table 43: Host Interface Pin Descriptions
      • 4.4.2 LCD Interface
        • Table 44: LCD Interface Pin Descriptions
      • 4.4.3 Clock Input
        • Table 45: Clock Input Pin Descriptions
      • 4.4.4 Miscellaneous
        • Table 46: Miscellaneous Pin Descriptions
      • 4.4.5 Power And Ground
        • Table 47: Power And Ground Pin Descriptions
    • 4.5 Summary of Configuration Options
      • Table 48: Summary of Power-On/Reset Options
    • 4.6 Host Bus Interface Pin Mapping
      • Table 49: Host Bus Interface Pin Mapping
    • 4.7 LCD Interface Pin Mapping
      • Table 410: LCD Interface Pin Mapping
  • 5 D.C. Characteristics
    • Table 51: Absolute Maximum Ratings
    • Table 52: Recommended Operating Conditions
    • Table 53: Electrical Characteristics for VDD = 3.3V typical
  • 6 A.C. Characteristics
    • 6.1 Clock Timing
      • 6.1.1 Input Clocks
        • Figure 61: Clock Input Requirements
        • Table 61: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
        • Table 62: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
        • Table 63: Clock Input Requirements for CLKI2
      • 6.1.2 Internal Clocks
        • Table 64: Internal Clock Requirements
    • 6.2 CPU Interface Timing
      • 6.2.1 Generic #1 Interface Timing
        • Figure 62: Generic #1 Interface Timing
        • Table 65: Generic #1 Interface Timing
      • 6.2.2 Generic #2 Interface Timing (e.g. ISA)
        • Figure 63: Generic #2 Interface Timing
        • Table 66: Generic #2 Interface Timing
      • 6.2.3 Hitachi SH-4 Interface Timing
        • Figure 64: Hitachi SH-4 Interface Timing
        • Table 67: Hitachi SH-4 Interface Timing
      • 6.2.4 Hitachi SH-3 Interface Timing
        • Figure 65: Hitachi SH-3 Interface Timing
        • Table 68: Hitachi SH-3 Interface Timing
      • 6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000)
        • Figure 66: Motorola MC68K #1 Interface Timing
        • Table 69: Motorola MC68K #1 Interface Timing
      • 6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030)
        • Figure 67: Motorola MC68K #2 Interface Timing
        • Table 610: Motorola MC68K #2 Interface Timing
      • 6.2.7 Motorola REDCAP2 Interface Timing
        • Figure 68: Motorola REDCAP2 Interface Timing
        • Table 611: Motorola REDCAP2 Interface Timing
      • 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328)
        • Figure 69: Motorola DragonBall Interface with DTACK Timing
        • Table 612: Motorola DragonBall Interface with DTACK Timing
      • 6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328)
        • Figure 610: Motorola DragonBall Interface without DTACK# Timing
        • Table 613: Motorola DragonBall Interface without DTACK Timing
    • 6.3 LCD Power Sequencing
      • 6.3.1 Passive/TFT Power-On Sequence
        • Figure 611: Passive/TFT Power-On Sequence Timing
        • Table 614: Passive/TFT Power-On Sequence Timing
      • 6.3.2 Passive/TFT Power-Off Sequence
        • Figure 612: Passive/TFT Power-Off Sequence Timing
        • Table 615: Passive/TFT Power-Off Sequence Timing
    • 6.4 Display Interface
      • Figure 613: Panel Timing Parameters
      • Table 616: Panel Timing Parameter Definition and Register Summary
      • 6.4.1 Generic STN Panel Timing
        • Figure 614: Generic STN Panel Timing
      • 6.4.2 Single Monochrome 4-Bit Panel Timing
        • Figure 615: Single Monochrome 4-Bit Panel Timing
        • Figure 616: Single Monochrome 4-Bit Panel A.C. Timing
        • Table 617: Single Monochrome 4-Bit Panel A.C. Timing
      • 6.4.3 Single Monochrome 8-Bit Panel Timing
        • Figure 617: Single Monochrome 8-Bit Panel Timing
        • Figure 618: Single Monochrome 8-Bit Panel A.C. Timing
        • Table 618: Single Monochrome 8-Bit Panel A.C. Timing
      • 6.4.4 Single Color 4-Bit Panel Timing
        • Figure 619: Single Color 4-Bit Panel Timing
        • Figure 620: Single Color 4-Bit Panel A.C. Timing
        • Table 619: Single Color 4-Bit Panel A.C. Timing
      • 6.4.5 Single Color 8-Bit Panel Timing (Format 1)
        • Figure 621: Single Color 8-Bit Panel Timing (Format 1)
        • Figure 622: Single Color 8-Bit Panel A.C. Timing (Format 1)
        • Table 620: Single Color 8-Bit Panel A.C. Timing (Format 1)
      • 6.4.6 Single Color 8-Bit Panel Timing (Format 2)
        • Figure 623: Single Color 8-Bit Panel Timing (Format 2)
        • Figure 624: Single Color 8-Bit Panel A.C. Timing (Format 2)
        • Table 621: Single Color 8-Bit Panel A.C. Timing (Format 2)
      • 6.4.7 Single Color 16-Bit Panel Timing
        • Figure 625: Single Color 16-Bit Panel Timing
        • Figure 626: Single Color 16-Bit Panel A.C. Timing
        • Table 622: Single Color 16-Bit Panel A.C. Timing
      • 6.4.8 Generic TFT Panel Timing
        • Figure 627: Generic TFT Panel Timing
      • 6.4.9 9/12/18-Bit TFT Panel Timing
        • Figure 628: 18-Bit TFT Panel Timing
        • Figure 629: TFT A.C. Timing
        • Table 623: TFT A.C. Timing
      • 6.4.10 160x160 Sharp �Direct� HR-TFT Panel Timing (e.g. LQ031B1DDxx)
        • Figure 630: 160x160 Sharp �Direct� HR-TFT Panel Horizontal Timing
        • Table 624: 160x160 Sharp �Direct� HR-TFT Horizontal Timing
        • Figure 631: 160x160 Sharp �Direct� HR-TFT Panel Vertical Timing
        • Table 625: 160x160 Sharp �Direct� HR-TFT Panel Vertical Timing
      • 6.4.11 320x240 Sharp �Direct� HR-TFT Panel Timing (e.g. LQ039Q2DS01)
        • Figure 632: 320x240 Sharp �Direct� HR-TFT Panel Horizontal Timing
        • Table 626: 320x240 Sharp �Direct� HR-TFT Panel Horizontal Timing
        • Figure 633: 320x240 Sharp �Direct� HR-TFT Panel Vertical Timing
        • Table 627: 320x240 Sharp �Direct� HR-TFT Panel Vertical Timing
      • 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
        • Figure 634: 160x240 Epson D-TFD Panel Horizontal Timing
        • Table 628: 160x240 Epson D-TFD Panel Horizontal Timing
        • Figure 635: 160x240 Epson D-TFD Panel GCP Horizontal Timing
        • Table 629: 160x240 Epson D-TFD Panel GCP Horizontal Timing
        • Figure 636: 160x240 Epson D-TFD Panel Vertical Timing
        • Table 630: 160x240 Epson D-TFD Panel Vertical Timing
      • 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
        • Figure 637: 320x240 Epson D-TFD Panel Horizontal Timing
        • Table 631: 320x240 Epson D-TFD Panel Horizontal Timing
        • Figure 638: 320x240 Epson D-TFD Panel GCP Horizontal Timing
        • Table 632: 320x240 Epson D-TFD Panel GCP Horizontal Timing
        • Figure 639: 320x240 Epson D-TFD Panel Vertical Timing
        • Table 633: 320x240 Epson D-TFD Panel Vertical Timing
  • 7 Clocks
    • 7.1 Clock Descriptions
      • 7.1.1 BCLK
        • Table 71: BCLK Clock Selection
      • 7.1.2 MCLK
        • Table 72: MCLK Clock Selection
      • 7.1.3 PCLK
        • Table 73: PCLK Clock Selection
        • Table 74: Relationship between MCLK and PCLK
      • 7.1.4 PWMCLK
        • Table 75: PWMCLK Clock Selection
    • 7.2 Clock Selection
      • Figure 71: Clock Selection
    • 7.3 Clocks versus Functions
      • Table 76: S1D13706 Internal Clock Requirements
  • 8 Registers
    • 8.1 Register Mapping
    • 8.2 Register Set
      • Table 81: S1D13706 Register Set
    • 8.3 Register Descriptions
      • 8.3.1 Read-Only Configuration Registers
      • 8.3.2 Clock Configuration Registers
        • Table 82: MCLK Divide Selection
        • Table 83: PCLK Divide Selection
        • Table 84: PCLK Source Selection
      • 8.3.3 Look-Up Table Registers
      • 8.3.4 Panel Configuration Registers
        • Table 85: Panel Data Width Selection
        • Table 86: Active Panel Resolution Selection
        • Table 87: LCD Panel Type Selection
      • 8.3.5 Display Mode Registers
        • Table 88: Inverse Video Mode Select Options
        • Table 89: LCD Bit-per-pixel Selection
        • Figure 81: Display Data Byte/Word Swap
        • Table 810: SwivelViewTM Mode Select Options
      • 8.3.6 Picture-in-Picture Plus (PIP+) Registers
        • Table 811: 32-bit Address Increments for Color Depth
        • Table 812: 32-bit Address Increments for Color Depth
        • Table 813: 32-bit Address Increments for Color Depth
        • Table 814: 32-bit Address Increments for Color Depth
      • 8.3.7 Miscellaneous Registers
      • 8.3.8 General IO Pins Registers
      • 8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers
        • Figure 82: PWM Clock/CV Pulse Block Diagram
        • Table 815: PWM Clock Control
        • Table 816: CV Pulse Control
        • Table 817: PWM Clock Divide Select Options
        • Table 818: CV Pulse Divide Select Options
        • Table 819: PWMOUT Duty Cycle Select Options
  • 9 Frame Rate Calculation
  • 10 Display Data Formats
    • Figure 101: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
  • 11 Look-Up Table Architecture
    • 11.1 Monochrome Modes
      • 1 Bit-per-pixel Monochrome Mode
        • Figure 111: 1 Bit-per-pixel Monochrome Mode Data Output Path
      • 2 Bit-per-pixel Monochrome Mode
        • Figure 112: 2 Bit-per-pixel Monochrome Mode Data Output Path
      • 4 Bit-per-pixel Monochrome Mode
        • Figure 113: 4 Bit-per-pixel Monochrome Mode Data Output Path
      • 8 Bit-per-pixel Monochrome Mode
        • Figure 114: 8 Bit-per-pixel Monochrome Mode Data Output Path
      • 16 Bit-Per-Pixel Monochrome Mode
    • 11.2 Color Modes
      • 1 Bit-Per-Pixel Color
        • Figure 115: 1 Bit-Per-Pixel Color Mode Data Output Path
      • 2 Bit-Per-Pixel Color
        • Figure 116: 2 Bit-Per-Pixel Color Mode Data Output Path
      • 4 Bit-Per-Pixel Color
        • Figure 117: 4 Bit-Per-Pixel Color Mode Data Output Path
      • 8 Bit-per-pixel Color Mode
        • Figure 118: 8 Bit-per-pixel Color Mode Data Output Path
      • 16 Bit-Per-Pixel Color Mode
  • 12 SwivelView�
    • 12.1 Concept
    • 12.2 90 SwivelView�
      • Figure 121: Relationship Between The Screen Image and the Image Refreshed in 90� SwivelView.
      • 12.2.1 Register Programming
    • 12.3 180 SwivelView�
      • Figure 122: Relationship Between The Screen Image and the Image Refreshed in 180� SwivelView.
      • 12.3.1 Register Programming
    • 12.4 270 SwivelView�
      • Figure 123: Relationship Between The Screen Image and the Image Refreshed in 270� SwivelView.
      • 12.4.1 Register Programming
  • 13 Picture-in-Picture Plus (PIP+)
    • 13.1 Concept
      • Figure 131: Picture-in-Picture Plus with SwivelView disabled
    • 13.2 With SwivelView Enabled
      • 13.2.1 SwivelView 90
        • Figure 132: Picture-in-Picture Plus with SwivelView 90 enabled
      • 13.2.2 SwivelView 180
        • Figure 133: Picture-in-Picture Plus with SwivelView 180 enabled
      • 13.2.3 SwivelView 270
        • Figure 134: Picture-in-Picture Plus with SwivelView 270 enabled
  • 14 Big-Endian Bus Interface
    • 14.1 Byte Swapping Bus Data
      • 14.1.1 16 Bpp Color Depth
        • Figure 141: Byte-swapping for 16 Bpp
      • 14.1.2 1/2/4/8 Bpp Color Depth
        • Figure 142: Byte-swapping for 1/2/4/8 Bpp
  • 15 Power Save Mode
    • Table 151: Power Save Mode Function Summary
  • 16 Mechanical Data
    • Figure 161: Mechanical Data 100pin TQFP15 (S1D13706F00A)
    • Figure 162: Mechanical Data 104pin CFLGA (S1D13706B00A)
  • 17 References
  • 18 Sales and Technical Support
• Programming Notes and Examples
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Initialization
    • Table 21: Example Register Values
  • 3 Memory Models
    • 3.1 Display Buffer Location
    • 3.2 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)
      • Figure 31: Pixel Storage for 1 Bpp in One Byte of Display Buffer
    • 3.3 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)
      • Figure 32: Pixel Storage for 2 Bpp in One Byte of Display Buffer
    • 3.4 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)
      • Figure 33: Pixel Storage for 4 Bpp in One Byte of Display Buffer
    • 3.5 Memory Organization for 8 Bpp (256 Colors/64 Gray Shades)
      • Figure 34: Pixel Storage for 8 Bpp in One Byte of Display Buffer
    • 3.6 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)
      • Figure 35: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer
  • 4 Look-Up Table (LUT)
    • 4.1 Registers
      • 4.1.1 Look-Up Table Write Registers
      • 4.1.2 Look-Up Table Read Registers
    • 4.2 Look-Up Table Organization
      • Table 41: Look-Up Table Configurations
      • 4.2.1 Gray Shade Modes
        • Table 42: Suggested LUT Values for 1 Bpp Gray Shade
        • Table 43: Suggested LUT Values for 4 Bpp Gray Shade
        • Table 44: Suggested LUT Values for 4 Bpp Gray Shade
      • 4.2.2 Color Modes
        • Table 45: Suggested LUT Values for 1 bpp Color
        • Table 46: Suggested LUT Values for 2 bpp Color
        • Table 47: Suggested LUT Values to Simulate VGA Default 16 Color Palette
        • Table 48: Suggested LUT Values to Simulate VGA Default 256 Color Palette
  • 5 Power Save Mode
    • 5.1 Overview
    • 5.2 Registers
      • 5.2.1 Power Save Mode Enable
      • 5.2.2 Memory Controller Power Save Status
    • 5.3 Enabling Power Save Mode
    • 5.4 Disabling Power Save Mode
  • 6 LCD Power Sequencing
    • 6.1 Enabling the LCD Panel
    • 6.2 Disabling the LCD Panel
  • 7 SwivelView�
    • 7.1 Registers
      • Table 71: SwivelView Enable Bits
    • 7.2 Examples
    • 7.3 Limitations
      • 7.3.1 SwivelView 0 and 180
      • 7.3.2 SwivelView 90 and 270
  • 8 Picture-In-Picture Plus
    • 8.1 Concept
      • Figure 81: Picture-in-Picture Plus with SwivelView disabled
    • 8.2 Registers
      • Table 81: 32-bit Address Increments for Color Depth
      • Table 82: 32-bit Address Increments for Color Depth
      • Table 83: 32-bit Address Increments for Color Depth
      • Table 84: 32-bit Address Increments for Color Depth
    • 8.3 Picture-In-Picture-Plus Examples
      • 8.3.1 SwivelView 0 (Landscape Mode)
        • Figure 82: Picture-in-Picture Plus with SwivelView disabled
      • 8.3.2 SwivelView 90
        • Figure 83: Picture-in-Picture Plus with SwivelView 90 enabled
      • 8.3.3 SwivelView 180
        • Figure 84: Picture-in-Picture Plus with SwivelView 180 enabled
      • 8.3.4 SwivelView 270
        • Figure 85: Picture-in-Picture Plus with SwivelView 270 enabled
    • 8.4 Limitations
      • 8.4.1 SwivelView 0 and 180
      • 8.4.2 SwivelView 90 and 270
  • 9 Identifying the S1D13706
  • 10 Hardware Abstraction Layer (HAL)
    • 10.1 API for 13706HAL
      • Table 101: HAL Functions
    • 10.2 Initialization
      • 10.2.1 General HAL Support
      • 10.2.2 Advance HAL Functions
      • 10.2.3 Surface Support
      • 10.2.4 Register Access
      • 10.2.5 Memory Access
      • 10.2.6 Color Manipulation
      • 10.2.7 Virtual Display
      • 10.2.8 Drawing
      • 10.2.9 Register/Display Memory
    • 10.3 Porting LIBSE to a new target platform
      • Figure 101: Components needed to build 13706 HAL application
      • 10.3.1 Building the LIBSE library for SH3 target example
  • 11 Sample Code
• Register Summary
• 13706CFG Configuration Program
  • Table of Contents
  • 13706CFG
    • S1D13706 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13706CFG Configuration Tabs
      • General Tab
      • Preferences Tab
      • Clocks Tab
      • Panel Tab
      • Panel Power Tab
      • Registers Tab
    • 13706CFG Menus
      • Open...
      • Save
      • Save As...
      • Configure Multiple
      • Export
      • Enable Tooltips
      • ERD on the Web
      • About 13706CFG
    • Comments
• 13706SHOW Demonstration Program
  • 13706SHOW
    • S1D13706 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13706SHOW Examples
      • Using 13706SHOW For Demonstration
    • Comments
• 13706PLAY Diagnostic Utility
  • 13706PLAY
    • S1D13706 Supported Evaluation Platforms
    • Installation
    • Usage
    • Commands
    • 13706PLAY Example
    • Scripting
    • Comments
• 13706BMP Demonstration Program
  • 13706BMP
    • S1D13706 Supported Evaluation Platforms
    • Installation
    • Usage
    • Display Surfaces
      • Table 1: Display Surfaces
    • 13706BMP Examples
    • Comments
• Windows� CE 2.x Display Drivers
  • WINDOWS� CE 2.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
    • Comments
• Wind River WindML v2.0 Display Drivers
  • Wind River WindML v2.0 DISPLAY DRIVERS
    • Building a WindML v2.0 Display Driver
      • 1. Create a working directory and unzip the WindML display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Build the WindML v2.0 library.
      • 7. Open the S1D13706 workspace.
      • 8. Add support for single line comments.
        • a. In the Tornado �Workspace Views� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 9. Compile the VxWorks image.
      • 10. Copy the VxWorks file to the diskette.
      • 11. Start the VxWorks demo.
• Wind River UGL v1.2 Display Drivers
  • Wind River UGL v1.2 Display Drivers
    • Building a UGL v1.2 Display Driver
      • 1. Create a working directory and unzip the UGL display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Open the S1D13706 workspace.
      • 7. Add support for single line comments.
        • a. In the Tornado �Workspace� window, click on the �Builds� tab.
        • b. Expand the �8bpp Builds� (or �16bpp Builds�) view by clicking on the �+� next to it. The expan...
        • c. Select the �C/C++ compiler� tab to display the command switches used in the build. Remove the ...
      • 8. Compile the VxWorks image.
      • 9. Copy the VxWorks file to the diskette.
      • 10. Start the VxWorks demo.
• Linux Console Driver
  • Linux Console Driver
    • Building the Console Driver for Linux Kernel 2.2.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory.
      • 4. Modify s1d13706.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
    • Building the Console Driver for Linux Kernel 2.4.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...
      • 4. Modify s1d13706.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
• QNX Photon v2.0 Display Driver
  • QNX Photon v2.0 Display Driver
    • Building the Photon v2.0 Display Driver
      • Unpack the Graphics Driver Development Kit Archive
      • Configure the Driver
      • Build the Driver
      • Installing the Driver
      • Run the Driver
    • Comments
• Windows� CE 3.x Display Drivers
  • WINDOWS� CE 3.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
      • Resource Management Issues
    • Comments
• S1D13XXX 32-Bit Windows Device Driver Installation Guide
  • S1D13XXX 32-Bit Windows Device Driver Installation Guide
    • Driver Requirements
    • Installation
      • Windows NT Version 4.0
      • Windows 2000
      • Windows 98/ME
      • Windows 95 OSR2
      • Previous Versions of Windows 95
• S5U13706B00C Rev. 1.0 Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Features
  • 3 Installation and Configuration
    • 3.1 Configuration DIP Switches
      • Figure 31: Configuration DIP Switch (SW1) Location
      • Table 31: Configuration DIP Switch Settings
    • 3.2 Configuration Jumpers
      • Table 32: Jumper Summary
      • Figure 32: Configuration Jumper (JP1) Location
      • Figure 33: Configuration Jumper (JP2) Location
      • Figure 34: Configuration Jumper (JP3) Location
      • Figure 35: Configuration Jumper (JP4) Location
      • Figure 36: Configuration Jumper (JP5) Location
      • Figure 37: Configuration Jumper (JP6) Location
      • Figure 38: Configuration Jumper (JP7) Location
  • 4 CPU Interface
    • 4.1 CPU Interface Pin Mapping
      • Table 41: CPU Interface Pin Mapping
    • 4.2 CPU Bus Connector Pin Mapping
      • Table 42: CPU Bus Connector (H3) Pinout
      • Table 43: CPU Bus Connector (H4) Pinout
  • 5 LCD Interface Pin Mapping
    • Table 51: LCD Signal Connector (H1)
    • Table 52: Extended LCD Signal Connector (H2)
  • 6 Technical Description
    • 6.1 PCI Bus Support
    • 6.2 Direct Host Bus Interface Support
    • 6.3 S1D13706 Embedded Memory
    • 6.4 Manual/Software Adjustable LCD Panel Positive Power Supply (VDDH)
      • Table 61: Controlling the MAX754
    • 6.5 Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD)
      • Table 62: Controlling the MAX749
    • 6.6 Software Adjustable LCD Backlight Intensity Support Using PWM
    • 6.7 Passive/Active LCD Panel Support
      • 6.7.1 Buffered LCD Connector
      • 6.7.2 Extended LCD Connector
  • 7 Clock Synthesizer and Clock Options
    • Figure 71: Symbolic Clock Synthesizer Connections
    • 7.1 Clock Programming
  • 8 References
    • 8.1 Documents
    • 8.2 Document Sources
  • 9 Parts List
    • Table 91: Parts List
  • 10 Schematics
    • Figure 101: S1D13706B00C Schematics (1 of 6)
    • Figure 102: S1D13706B00C Schematics (2 of 6)
    • Figure 103: S1D13706B00C Schematics (3 of 6)
    • Figure 104: S1D13706B00C Schematics (4 of 6)
    • Figure 105: S1D13706B00C Schematics (5 of 6)
    • Figure 106: S1D13706B00C Schematics (6 of 6)
  • 11 Board Layout
    • Figure 111: S5U13706B00C Board Layout
  • 12 Technical Support
    • 12.1 EPSON LCD Controllers (S1D13706)
• Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the TMPR3905/12
    • 2.1 The Toshiba TMPR3905/12 System Bus
      • 2.1.1 Overview
      • 2.1.2 Card Access Cycles
        • Figure 21: Toshiba 3905/12 PC Card Memory/Attribute Cycle
        • Figure 22: Toshiba 3905/12 PC Card IO Cycle
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 Toshiba TMPR3905/12 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: S1D13706 to TMPR3905/12 Direct Connection
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 Memory Mapping and Aliasing
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13706)
    • 7.2 Toshiba MIPS TMPR3905/12 Processor
• Interfacing to the PC Card Bus
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PC Card Bus
    • 2.1 The PC Card System Bus
      • 2.1.1 PC Card Overview
      • 2.1.2 Memory Access Cycles
        • Figure 21: PC Card Read Cycle
        • Figure 22: PC Card Write Cycle
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 PC Card to S1D13706 Interface
    • 4.1 Hardware Connections
      • Figure 41: Typical Implementation of PC Card to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13706)
    • 7.2 PC Card Standard
• Power Consumption
  • 1 S1D13706 Power Consumption
    • 1.1 Conditions
      • Table 11: S1D13706 Total Power Consumption in mW
  • 2 Summary
• Interfacing to the NEC VR4102 / VR4111 Microprocessors
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4102/VR4111
    • 2.1 The NEC VR41XX System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 VR4102/VR4111 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of VR4102/VR4111 to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 NEC VR4102/VR4111 Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD Controllers (S1D13706)
    • 7.2 NEC Electronics Inc.
• Interfacing to the NEC VR4181A� Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4181A
    • 2.1 The NEC VR4181A System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Signals
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 VR4181A to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of VR4181A to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 NEC VR4181A Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD Controllers (S1D13706)
    • 7.2 NEC Electronics Inc.
• Interfacing to the Motorola MPC821 Microprocessor
  • Document Number: X31B-G-009-02
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MPC821
    • 2.1 The MPC8XX System Bus
    • 2.2 MPC8XX Bus Overview
      • 2.2.1 Normal (Non-Burst) Bus Transactions
        • Figure 21: Power PC Memory Read Cycle
        • Figure 22: Power PC Memory Write Cycle
      • 2.2.2 Burst Cycles
    • 2.3 Memory Controller Module
      • 2.3.1 General-Purpose Chip Select Module (GPCM)
        • Figure 23: GPCM Memory Devices Timing
      • 2.3.2 User-Programmable Machine (UPM)
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 MPC821 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MPC821 to S1D13706 Interface
    • 4.2 MPC821ADS Evaluation Board Hardware Connections
      • Table 41: List of Connections from MPC821ADS to S1D13706 
    • 4.3 S1D13706 Hardware Configuration
      • Table 42: Summary of Power-On/Reset Configuration Options
      • Table 43: CLKI to BCLK Divide Selection
    • 4.4 Register/Memory Mapping
    • 4.5 MPC821 Chip Select Configuration
    • 4.6 Test Software
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13706)
    • 7.2 Motorola MPC821 Processor
• Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MCF5307
    • 2.1 The MCF5307 System Bus
      • 2.1.1 Overview
      • 2.1.2 Normal (Non-Burst) Bus Transactions
        • Figure 21: MCF5307 Memory Read Cycle
        • Figure 22: MCF5307 Memory Write Cycle
      • 2.1.3 Burst Cycles
    • 2.2 Chip-Select Module
      • Figure 23: Chip Select Module Outputs Timing
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 MCF5307 To S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MCF5307 to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 Register/Memory Mapping
    • 4.4 MCF5307 Chip Select Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13706)
    • 7.2 Motorola MCF5307 Processor
• Connecting to the Sharp HR-TFT Panels
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Connecting to the Sharp LQ039Q2DS01 HR-TFT
    • 2.1 External Power Supplies
      • 2.1.1 Gray Scale Voltages for Gamma Correction
        • Figure 21: Sharp LQ039Q2DS01 Gray Scale Voltage (V0-V9) Generation
      • 2.1.2 Digital/Analog Power Supplies
      • 2.1.3 DC Gate Driver Power Supplies
        • Figure 22: Panel Gate Driver DC Power Supplies
      • 2.1.4 AC Gate Driver Power Supplies
        • Figure 23: Panel Gate Driver AC Power Supplies
    • 2.2 HR-TFT MOD Signal
      • Figure 24: HR-TFT Power-On/Off Sequence Timing
      • Table 21: HR-TFT Power-On/Off Sequence Timing
    • 2.3 S1D13706 to LQ039Q2DS01 Pin Mapping
      • Table 22: S1D13706 to LQ039Q2DS01 Pin Mapping
  • 3 Connecting to the Sharp LQ031B1DDxx HR-TFT
    • 3.1 External Power Supplies
      • 3.1.1 Gray Scale Voltages for Gamma Correction
        • Figure 31: Sharp LQ031B1DDxx Gray Scale Voltage (V0-V9) Generation
      • 3.1.2 Digital/Analog Power Supplies
      • 3.1.3 DC Gate Driver Power Supplies
      • 3.1.4 AC Gate Driver Power Supplies
    • 3.2 HR-TFT MOD Signal
    • 3.3 S1D13706 to LQ031B1DDxx Pin Mapping
      • Table 31: S1D13706 to LQ031B1DDxx Pin Mapping
  • 4 Test Software
  • 5 References
    • 5.1 Documents
    • 5.2 Document Sources
  • 6 Technical Support
    • 6.1 EPSON LCD Controllers (S1D13706)
    • 6.2 Sharp HR-TFT Panel
• Interfacing to the Motorola MC68030 Microprocessor
  • Document Number: X31B-G-013-02
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Motorola MC68030 Bus Interface
    • 2.1 Overview
    • 2.2 Dynamic Bus Sizing
      • Table 21: SIZ Signal Encoding
      • Table 22: DSACK Decoding
    • 2.3 Asynchronous / Synchronous Bus Operation
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 MC68030 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MC68030 to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13706)
    • 7.2 Motorola MC68030 Processor
• Connecting to the Epson D-TFD Panels
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 External Power Supplies
    • 2.1 VDDH and VDD - Horizontal and Vertical Analog Voltages
      • Figure 21: VDDH and VDD Voltage Generation
    • 2.2 VEEY - LCD Panel Drive Voltage for Vertical Power Supplies - Brightness Reference
      • Figure 22: VEE Switching Power Supply
      • Figure 23: Temperature Compensated VEEY
    • 2.3 VCC - Horizontal Logic Power Supply
      • Figure 24: VCC Power Supply
    • 2.4 Swing Power Supply for the Vertical Drive (V0Y) and Logic (VCCY / V5Y) Voltages
      • Figure 25: Swing Power Supply for Vertical System Voltages
      • Table 21: Swing Power Supply Values
    • 2.5 Level Shift and Clamp Circuit for Vertical Logic Control Signals
      • Figure 26: Logic for Vertical Control Signals
  • 3 S1D13706 to D-TFD Panel Pin Mapping
    • 3.1 LCD Pin Mapping for Horizontal Connector (LF37SQT and LF26SCT)
      • Table 31: LCD Pin Mapping for Horizontal Connector: Pins for Horizontal Driver
    • 3.2 LCD Pin Mapping for Y Connector (LF37SQT)
      • Table 32: LCD Pin Mapping for Y Connector: Pins for Y - Driver (LF37SQT)
    • 3.3 LCD Pin Mapping for Y Connector (LF26SCT)
      • Table 33: LCD Pin Mapping for Y Connector: Pins for Y - Driver (LF26SCT)
  • 4 Power-On/Off Sequence
    • Figure 41: D-TFD Power-On/Off Sequence Timing
    • Table 41: D-TFD Power-On/Off Sequence Timing
  • 5 GCP Data Signal
    • 5.1 GCP Data Structure
      • Figure 51: GCP Data
    • 5.2 Programming GCP Data
      • Table 51: GCP Data Bit Chain Values for LF37SQT and LF26SCT
  • 6 Test Software
  • 7 References
    • 7.1 Documents
    • 7.2 Document Sources
  • 8 Technical Support
    • 8.1 EPSON LCD Controllers (S1D13706)
• Interfacing to the Motorola RedCap2 DSP With Integrated MCU
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the REDCAP2
    • 2.1 The REDCAP2 System Bus
    • 2.2 Overview
    • 2.3 Bus Transactions
      • Figure 21: REDCAP2 Memory Read Cycle
      • Figure 22: REDCAP2 Memory Write Cycle
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 REDCAP2 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of REDCAP2 to S1D13706 Interface
    • 4.2 Hardware Connections
      • Table 41: List of Connections from REDCAP2 ADM to S5U13706B00C
    • 4.3 S1D13706 Hardware Configuration
      • Table 42: Summary of Power-On/Reset Options
    • 4.4 Register/Memory Mapping
    • 4.5 REDCAP2 Chip Select Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13706)
    • 7.2 Motorola REDCAP2 Processor
• Interfacing to 8-bit Processors
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to an 8-bit Processor
    • 2.1 The Generic 8-bit Processor System Bus
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 8-Bit Processor to S1D13706 Interface
    • 4.1 Hardware Connections
      • Figure 41: Typical Implementation of 8-bit Processor to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13706)
• Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor
  • Document Number: X31B-G-016-02
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MC68VZ328
    • 2.1 The MC68VZ328 System Bus
    • 2.2 Chip-Select Module
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signals
  • 4 MC68VZ328 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MC68VZ328 to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
      • 4.2.1 Register/Memory Mapping
      • 4.2.2 MC68VZ328 Chip Select and Pin Configuration
        • Table 43: WS Bit Programming
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13706)
    • 7.2 Motorola MC68VZ328 Processor
• Integrating the CFLGA 104-pin Chip Scale Package
  • Table of Contents
  • List of Figures
  • 1 Introduction
  • 2 Package Description
  • 3 Routing
    • 3.1 Perimeter Pads
      • Figure 31: Example Perimeter Pad Routing
    • 3.2 Inner Pads
      • Figure 32: Example Inner Pad Routing
  • 4 References
    • 4.1 Documents
    • 4.2 Document Sources
  • 5 Technical Support
    • 5.1 EPSON LCD Controllers (S1D13706)
• Interfacing to the Intel StrongARM SA-1110 Microprocessor
  • Document Number: X31B-G-019-02
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the StrongARM SA-1110 Bus
    • 2.1 The StrongARM SA-1110 System Bus
      • 2.1.1 StrongARM SA-1110 Overview
      • 2.1.2 Variable-Latency IO Access Overview
      • 2.1.3 Variable-Latency IO Access Cycles
        • Figure 21: SA-1110 Variable-Latency IO Read Cycle
        • Figure 22: SA-1110 Variable-Latency IO Write Cycle
  • 3 S1D13706 Host Bus Interface
    • 3.1 Host Bus Interface Pin Mapping
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Host Bus Interface Signal Descriptions
  • 4 StrongARM SA-1110 to S1D13706 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of SA-1110 to S1D13706 Interface
    • 4.2 S1D13706 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Configuration Options
      • Table 42: CLKI to BCLK Divide Selection
    • 4.3 StrongARM SA-1110 Register Configuration
      • Table 43: RDFx Parameter Value versus CPU Maximum Frequency
    • 4.4 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13706)
    • 7.2 Intel StrongARM SA-1110 Processor