SRM20V100LLMX

A0 to A16
WE
OE

CS1, CS2
I/O1 to I/O8
V

Address Input
Write Enable
Output Enable

Chip Select
Data I/O
Power Supply (2.7V to 3.6V)
Power Supply (0V)

N. C.

No connection

A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

CS1

I/O Buffer

Column Gate

Memory Cell Array

1024

128

1024

128

I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8

A13

A15
A16

A14

CS2

Address Buffer

X Decoder

Decoder

Chip

Control

CS1, CS2

Chip

Control

OE, WE

A11

A10

CS1

A13

I/08

I/07

CS2

I/06

A15

I/05

I/04

N.C.

A16

I/03

A14

I/02

A12

I/01

A12

I/01

A14

I/02

A16

I/03

N.C.

I/04

A15

I/05

CS2

I/06

I/07

A13

I/08

CS1

A10

A11

(SOP6)

(TSOP/Slim-TSOP)

SRM20V100LLMT

N.C. 1

A15

A16

CS2

A14

A12

A13

A11

A10

CS1

I/08

I/07

I/01

I/06

I/02

I/05

I/03

I/04

(TSOP-R1/Slim-TSOP-R1)

SRM20V100LLTX/KX

SRM20V100LLRX/YX

1M-Bit Static RAM

PF805-04

SRM20V100LLMX

DESCRIPTION

The SRM20V100LLMX

is an 131,072 words

8-bit asynchronous, static, random access memory on a monolithic

CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. And --25 to 85

C operating temperature range makes it ideal for portable equipment.

The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the
input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity.

FEATURES

Wide temperature range ..... 25 to 85

Fast Access time ................. SRM20V100LLMX

70ns (Max.)

Low supply current .............. standby: 0.6

A (Typ.): LL Version

0.3

A (Typ.): SL Version

operation: 8mA/1MHz (Typ.)

Completely static ................. No clock required

Supply voltage..................... 2.7V to 3.6V

TTL compatible inputs and outputs

3-state output with wired-OR capability

Non-volatile storage with back-up batteries

Package ...... SRM20V100LLMX

SOP6-32pin (plastic)

SRM20V100LLTX

TSOP (

)-32pin (plastic)

SRM20V100LLRX

TSOP (

)-32pin-R1 (plastic)

SRM20V100LLKX

Slim-TSOP (

)-32pin (plastic)

SRM20V100LLYX

Slim-TSOP (

)-32pin-R1 (plastic)

BLOCK DIAGRAM

PIN DESCRIPTION

Low Voltage

Operation

Products

Low Supply Voltage

Wide Temperature Range

Low Supply Current

Access Time 70ns (2.7V)

131,072 Words

8-Bit Asynchronous

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

DC RECOMMENDED OPERATING CONDITIONS

Supply voltage

Input voltage

Input/Output voltage

Power dissipation

Operating temperature

Storage temperature

Soldering temperature and time

I/O

opr

stg

sol

0.5 to 4.6

0.5 to V

+0.3

0.5 to V

+0.3

0.5

25 to 85

65 to 150

260

C, 10s (at lead)

Parameter

Symbol

Ratings

Unit

= 0V)

VI, VI/O (Min.) = 3.0V (Pulse width is 50ns)

= 0V, Ta = 25 to 85

Parameter

Input voltage

Supply voltage

Symbol

Conditions

If pulse width is less than 50ns, it is 3.0V

Min.

2.7

2.2

0.3

Typ.

3.0

Max.

3.6

+0.3

0.4

Unit

Parameter

Symbol

Conditions

Unit

Input leakage

High level output voltage

Low level output voltage

Operating supply current

Average operating current

DDS

DDO

= 2.7 to 3.6V, V

= 0V, Ta = 25 to 85

DDA

Typical values are measured at Ta=25

C and V

=3.0V

=0 to V

CS1 = V

or CS2 = V

Standby supply current

DDS1

DDA1

CS1 = CS2

--0.2V

or CS2

0.2V

= V

, V

I/O

= 0mA, t

cyc

= Min.

= V

, V

I/O

= 0mA, t

cyc

= 1

= V

, V

I/O

= 0mA

Min.

Typ.

Max.

2.4

--0.2

0.6

0.3

1.0

0.4

0.2

3V, I

= 2.0mA

= 100

3V, I

= 2.0mA

= 100

(f = 1MHz, Ta = 25

Parameter

Symbol

Address Capacitance

Input Capacitance

I/O Capacitance

ADD

I/O

Min.

Typ.

Max.

Unit

Conditions

ADD

=0V

I/O

=0V

Output leakage

CS1 = V

or CS2 = V

or WE = V

or OE = V

, V

= 0 to V

ELECTRICAL CHARACTERISTICS

DC Electrical Characteristics

Terminal Capacitance

SRM20V100LLMX

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

--
--
--
--

Min.

Max.

70
70
70
40

Parameter

Symbol

Conditions

= 2.7V to 3.6V, V

= 0V, Ta = 25 to 85

Read cycle time
Address access time
Chip select1 access time
Chip select2 access time
Output enable access time
Chip select1 output set time
Chip select1 output floating
Chip select2 output set time
Chip select2 output floating
Output enable output set time
Output enable output floating
Output hold time

ACC

ACS1

ACS2

CLZ1

CHZ1

CLZ2

CHZ2

OLZ

OHZ

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

70
60
60
60

Min.

Max.

--
--
--
--
--
--
--
--
--

Parameter

Symbol

Conditions

= 2.7V to 3.6V, V

= 0V, Ta = 25 to 85

Write cycle time
Chip select time1
Chip select time2
Address enable time
Address setup time
Write pulse width
Address hold time
Input data setup time
Input data hold time
WE Output floating
WE Output setup time

CW1

CW2

WHZ

+3V

1.0k

920

I/O

=5pF (Includes Jig Capacitance)

+3V

1.0k

920

I/O

=100pF (Includes Jig Capacitance)

1 Test Conditions

1. Input pulse level: 0.4V to 2.4V

2. t

= t

= 5ns

3. Input and output timing reference

levels : 1.5V

4. Output load C

= 100pF

2 Test Conditions

1. Input pulse level : 0.4V to 2.4V

2. t

= t

= 5ns

3. Input timing reference levels: 1.5V

4. Output timing reference levels:

200mV (the level displaced from

stable output voltage level)

5. Output load C

= 5pF

AC Electrical Characteristics

Read Cycle

Write Cycle

Note : 1. During read cycle time, WE is to be "H" level.

2. During write cycle time that is controlled by CS1 or CS2, Output Buffer is in high impedance state, whether OE level is "H" or "L".

3. During write cycle time that is controlled by WE, Output Buffer is high impedance state if OE is "H" level.

4. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals.

Write Cycle (3) (WE Control)

Address

CS1

CS2

Dout

Din

WHZ

Write Cycle (2) (CS2 Control)

Address

CS1

CS2

Dout

Din

CW2

CLZ2

WHZ

Read Cylcle

Address

CS1

CS2

Dout

Write Cycle (1) (CS1 Control)

Address

CS1

CS2

Dout

Din

CW1

WHZ

CLZ1

CHZ1

ACS2

CLZ2

CHZ2

OHZ

OLZ

ACC

ACS1

CLZ1

Timing chart

when retaining data in standby mode, supply voltage can be lowered with in a certain range. But read or write cycle

cannot be performed while the supply voltage is low.

DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Data retention Supply voltage

Data retention current

Chip select data hold time

DDR

CDR

2.0

3.6

= 0V, Ta = 25 to 85

Operation recovery time

= 2.7V

CS1 = CS2

--0.2V

or CS2

0.2V

Ta = 25

0.5

0.25

CS2

CDR

DDR

2.0V

CS2

0.2V

Data hold mode

Data retention timing (CS1 Control)

2.7V

CS1

CDR

DDR

2.0V

CS1

--0.2V

Data hold mode

2.7V

Data retention timing (CS2 Control)

SRM20V100LLMX

Reading data

Data is able to be read when the address is set while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H".

Since DATA I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any

other objective, then access time apparently is able to be cut down.

Writing data

There are the following four ways of writing data into the memory.

(1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1.

(2) Hold CS1 = "L", WE = "L" ,set addresses and give "H"pulse to CS2.

(3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE.

(4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2.

Anyway, data on the Data I/O terminals are latched up into the SRM20V100LLMX

at the end of the period that

CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of

CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided.

Standby mode

When CS1 is "H" or CS2 is "L" level, the SRM20V100LLMX

is in the standby mode which has retaining data

operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or

"L". When CS1 and CS2 level are in the range over V

-0.2V, CS2 level is in the range under 0.2V, in the

SRM20V100LLMX

there is almost no current flow except through the high resistance parts of the memory.

FUNCTIONS

Truth Table

X : "H" or "L"

CS1

CS2

DATA I/O

Mode

DDS,

DDS1

DDS,

DDS1

DDO

Hi-Z

Input data

Output data

Hi-Z

Unselected

Write

Read

Output disable

PACKAGE DIMENSIONS

Unit : mm

(inch)

Plastic SOP6-32pin

1.27

(0.05)

20.45

0.1

(0.805 )

11.295

0.1

(
0.445

)

+0.003 0.004

0.4

0.1

(0.016 )

+0.003

0.004

3.1

max

(
0.122

max

)

+0.004

0.003

0.2

(
0.008

)

1.42

(0.056)

0.15

0.05

(0.006 )

+0.001

0.002

20.85

max

(0.82

max

)

14.135

0.3

(
0.556

)

+0.012 0.011

2.7

0.1

(
0.106

)

+0.004 0.003

0.8

0.2

(0.031 )

+0.008

0.007

Plastic TSOP (

) -32pin

Unit : mm

(inch)

INDEX

18.4

0.2

(0.724 )

+0.008

0.007

0.2

(
0.315

0.007

)

0.2

(0.787 )

+0.008

0.007

0.5

0.1

(0.02 )

+0.003

0.004

0.15

(0.006 )

+0.002

0.003

0.5

(0.02)

1.27

max

(
0.05

max

)

0.2

0.1

(0.008 )

+0.003

0.004

(
0.039

)

+0.07

0.075

0.8

0.2

(0.031 )

+0.008

0.007

Unit : mm

(inch)

Plastic Slim-TSOP (

) -32pin

Plastic TSOP (

) -32pin-R1

Unit : mm

(inch)

Unit : mm

(inch)

Plastic Slim-TSOP (

) -32pin-R1

18.4

0.2

(0.724 )

+0.008

0.007

0.2

(
0.315

0.007

)

0.2

(0.787 )

+0.008

0.007

0.5

0.1

(0.02 )

+0.003

0.004

0.15

(0.006 )

+0.002

0.003

0.5

(0.02)

1.27

max

(
0.05

max

)

0.2

0.1

(0.008

)

+0.003

0.004

(
0.039

)

+0.07

0.075

0.8

0.2

(0.031 )

+0.008

0.007

INDEX

11.8

0.1

(

0.465

0.003

)

0.2

(

0.315

0.007

)

13.4

0.3

(

0.528

0.011

)

0.5

0.1

(

0.02

)

+0.003

0.004

0.15

(

0.006

)

+0.002

0.003

0.5

(

0.02

)

1.27

max

(

0.05

max

)

0.2

0.1

(

0.008

)

+0.003

0.004

(

0.039

)

+0.07

0.075

0.8

0.2

(

0.031

)

+0.008

0.007

11.8

0.1

(

0.465

0.003

)

0.2

(

0.315

0.007

)

13.4

0.3

(

0.528

0.011

)

0.5

0.1

(

0.02

)

+0.003

0.004

0.15

(

0.006

)

+0.002

0.003

0.5

(

0.02

)

1.27

max

(

0.05

max

)

0.2

0.1

(

0.008

)

+0.003

0.004

(

0.039

)

+0.07

0.075

0.8

0.2

(

0.031

)

+0.008

0.007

INDEX

SRM20V100LLMX

CHARACTERISTICS CURVES

1.7

1.6

1.5

1.4

1.3

1.2

1.1

0.9

0.8

0.7

0.6

40 20

WRITE

= 3.0V

READ, WRITE

READ

Ta (

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Frequency (MHz)

1/t

, 1/t

1.6

1.5

1.4

1.3

1.2

1.1

0.9

0.8

0.7

0.6

2.4

2.7

3.3

3.6

3.9

(V)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

0.5

1.5

2.5

3.5

(V)

Normalized I

DDA

--Ta

Normalized I

DDA

--V

Normalized I

DDA

--Frequency

Normalized I

DDS1

--V

Normalized I

--V

100

0.1

0.01

Ta (

100

0.1

3.9

3.6

3.3

2.7

2.4

(V)

Normalized I

DDS1--

= 3.0V

Ta = 25

= 3.0V

WRITE

READ

Ta = 25

READ, WRITE

WRITE

READ

Ta = 25

= 3.0V

IC Marketing & Engineering Group
4218 Hino, Hinoshi, Tokyo 191, JAPAN
Phone: 0425875816

FAX: 0425875624

International Marketing Department I (Europe & U. S. A.)
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425875812

FAX: 0425875564

International Marketing Department II (Asia)
421-8 Hino, Hino-shi, Tokyo 191, JAPAN
Phone: 0425875814

FAX: 0425875110

ELECTRONIC DEVICE MARKETING DEPARTMENT

First issue Oct. 1995, printed Feb. 1997 in Japan T

NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted
by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of
International Trade and Industry or other approval from another government agency.

SRM20V100LLMX

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

0.2

0.4

0.6

0.8

(V)

Normalized t

ACS1

--Ta

ACC

ACS2

Normalized t

ACS1

--V

ACC

ACS2

Normalized t

ACS1

--C

ACC

ACS2

Normalized I

DDR

--Ta

Normalized I

--V

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

Ta (

1.3

1.25

1.2

1.15

1.1

1.05

0.95

0.9

0.85

0.8

(V)

3.9

3.6

3.3

2.7

2.4

= 3.0V

Ta = 25

= 3.0V

2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1

0.9
0.8
0.7
0.6
0.5

100

200

300

400

(pF)

100

0.1

0.01

40 20

Ta (

Ta = 25

= 3.0V

=2.7V

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SRM20V100LLRX7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SRM20V100LLRX7