1
PBL 402 15
January 2001
Preliminary
RF Transceiver circuit for the Digital
Enhanced Cordless Telecommunications
(DECT) system
PBL 402 15
Description.
The PBL 402 15 is a complete RF transceiver to be used in the Digital Enhanced
Cordless Telecommunications ( DECT ) system. It is designed to interface to various
base-band controllers.
The circuit contains transmit and receive functions that share integrated high stability
VCOs and a phase locked loop function ( PLL ). All functionality is controlled through a
3-wire bus interface with optional hard wire lines.
The receive section comprises of a low noise image reject down conversion to the
first intermediate frequency, an external channel filter, a second down convertion to a
second intermediate frequency, an integrated channel pass filter, a high gain limiting
amplifier, a received signal strenght indicator with DC compensation loop, a self aligned
frequency discriminator and a preamble based data slicer.
The transmit section comprises of a signal gate and a pre-power amplifier. Data
transmission is achieved by direct open loop modulation of the Tx VCO.
Key features.
High Tx output power to +7dBm
Integrated PLL and high stability
VCOs
3-line serial interface bus
Minimum 2.7 V supply voltage
Low current consumption
Differential Rx input and Tx output
Flexible interface to various base-
band controllers
Exellent performance with Ericssons
power amplifier PBL403 09
Low cost
Applications:
DECT Handset and base station
Wireless local area network ( WLAN )
Wireless local loop ( WLL )
Figure 1. Block diagram.
Figure 2. Package outlook.
PBL
402 15
2
PBL 402 15
PBL402 15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
EN
REF
VccPLL
GND
VccCP
NC
NC
680 pF
C1
C0
6.8nF
R0
3.9k
C2
100nF
VccVCO
Regulated supply
Vcc
GND
DTx
MOD
SHold
2nF
C3
DRx
DSL
RSSI
VccFM
Vcc
GND
C18 22nF
L1
140nH *
C7 68pF *
C6 68pF *
GND
VccIF
MS lines 2
MS lines 3
MS lines 1
LD
IF - SAW filter
+
+
_
_
in
out
L0
180nH *
C4 11pF *
C5 11pF *
GND
GND
C10 8pF
C8 1pF
C11 8pF
C9
L4
8.2nH
L3
5.6nH
L2 5.6nF
RxEN
TxEN
ST
CK
D
GATE
GND
GND
GND
L6 4.7nH
L5 4.7nH
C13 1pF
C12 1pF
+in
-in
+out
-out
Vcc
Gate
C16
10nF
C17
33pF
C14
2.2nF
C15
8pF
PA - Vcc
Consult PBL40309 for PA
output matching requirements
RF in to Rx
Feed from antenna switch.
( 50 ohms )
CP
V
TUNE
PA Gate
Can also be a balun type of solution
GND
1pF
* These components for matching are not needed if Murata filter is used
Figure 3. DECT application.
Figure 4. The European DECT band .
EUROPEAN DECT Band 1880 - 1900 MHz
Channel 0
1
2
3
4
5
6
7
8
9
10 channels
Channel spacing
1.728 MHz
TDMA ( time division multiple access )
Frequency and time division.
Frame =10 ms
24 time slots
1 slot = 416.67
s
each slot contains, a synchronisation field,
control info, data package and error control.
Frequency
Time
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
22 23
21
Base to Mobile
Mobile to Base
0
Frequency MHz
1881.792
1883.520
1885.248
1886.976
1888.704
1890.432
1892.160
1893.888
1895.616
1897.344
A-word
CNT_A
1
2
3
4
5
6
7
8
9
10
3
PBL 402 15
1
2
3
4
5
6
7
8
9
10
11
12
13 14
36
35
34
33
32
31
30
29
28
27
26
25
REF
VccPLL
GndPLL
VccCP
CP
GndCP
VTUNE
GndVCO
NC
NC
VccVCO
EN
GndRF
RX+
RX-
GndRF
PA Gate
IFOUT+
IFOUT-
LD
VccIF
GndIF
IFIN+
IFIN-
GndFM
DTX
MOD
SHOLD
DRX
DSL
VccFM
RSSI
VccRSSI
CAP+
CAP-
GndRSSI
RXEN
DIE
TXEN
ST
CK
D
GA
TE
VccRF
GndRF
TX+
TX-
GndRF
15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
Figure 5. Pinning configuration.
Pin Descriptions:
Refer to pin configuration.
Pin number
Name Function Schematic in/output of the pin
1
EN
Enable 3-wire interface and synthesiser.
2
REF
PLL reference clock input
3
V
CC
PLL
Voltage supply to the frequency synthesiser.
4
GndPLL
Ground connection to the frequency synthesiser.
5
GndCP
Ground connection to the charge pump.
6
CP
Charge pump output.
7
V
CC
CP
Voltage supply to the charge pump.
V
CC
PLL
EN
GndPLL
165 k
V
CC
PLL
REF
GndPLL
Clamp to GndPLL
A diode to GndCP and GndRF
A diode to GndPLL and GndVCO
V
CC
CP
CP
GndCP
Clamp to GndCP
4
PBL 402 15
Pin Descriptions (cont.):
Pin number
Name Function Schematic in/output of the pin
8
Not connected
9
Not connected
10
V
CC
VCO
Voltage supply to the VCO
11
VTUNE
Tuning voltage input for the VCO
12
GndVCO
Ground connection to the VCO
13
GndFM
Ground connection to the FM discriminator section.
14
DTX
Tx data input for either analog or logic signal.
15
MOD
Apply modulation. The PLL is set into open loop
condition and modulation is applied to the VCO.
16
SHOLD
Slice level hold logic input. (In Tx mode this input
may also act as the MOD pin).
17
DRX
Rx data output of FM discriminator for either analog
or logic signal.(In standby mode outputs lock detect)
18
DSL
Data slice level output.
19
V
CC
FM
Voltage supply to the FM discriminator section.
20
RSSI
RSSI output of limiting strip detector chain.
N/C
Clamp to GndVCO
V
CC
VCO
VTUNE
GndVCO
A diode to GndCP and GndFM
V
CC
FM
DTX
GndFM
V
CC
FM
MOD
GndFM
Bias
V
CC
FM
SHOLD
GndFM
Bias
V
CC
FM
DRX
GndFM
V
CC
FM
DSL
GndFM
Clamp to GndFM
21
V
CC
RSSI
Voltage supply to the RSSI section.
22
CAP+
External stabilising capacitors for limiting strip
DC input offset correction loop.
23
CAP-
V
CC
RSSI
RSSI
GndRSSI
Clamp to GndRSSI
V
CC
RSSI
CAP+/CAP-
Both inputs alike
GndRSSI
5
PBL 402 15
Pin Descriptions (cont.):
Pin number
Name Function Schematic in/output of the pin
24
GndRSSI
Ground connection to the RSSI.
25
PA Gate
Output control signal for external PA power on/off.
26
IFIN-
Rx IF inputs to internal channel filtering, limiting
amplifiers,RSSI and FM discriminator. Internally
27
IFIN+
matched to 300
.
28
GndIF
Ground connection to the down IF convertor and
channel filter sections.
29
V
CC
IF
Voltage supply to the down IF convertor and
channel filter sections.
30
LD
Lock detect.
31
IFOUT-
Rx IF outputs to external adjacent channel filter.
Internally matched to 300
.
32
IFOUT+
33, 36
GndRF
Ground connection to the RF sections.
37, 40
34
RX-
RF inputs to LNA and image reject mixer.
35
RX+
Internally matched to 100
.
38
TX-
Tx outputs to external PA. Internally matched to
39
TX+
100
. Each output requires an externalchoke
to V
CC
.
41
V
CC
RF
Voltage supply to the RF sections.
42
GATE
Input to gate the Tx output power.
43
D
Serial interface, Data .
A diode to GndFM and GndIF
V
CC
RF
PA - Gate
GndRF
V
CC
IF
IFIN-/IFIN+
both inputs alike
GndIF
A diode to GndFM and GndIF
Clamp to GndIF
V
CC
RF
LD
GndRF
V
CC
RF
IFOUT-/IFOUT+
both outputs alike
GndRF
A diode to GndIF and GndPLL
V
CC
RF
RX-/RX+
both inputs alike
GndRF
V
CC
RF
TX-/TX+
Both inputs alike
GndRF
Clamp to GndRF
V
CC
PLL
GATE
GndPLL
Bias
V
CC
PLL
D
GndPLL
Bias
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