(OLWH07
M11B11664A
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3 1/15
DRAM
64 K x 16 DRAM
EDO PAGE MODE
FEATURES
y
X16
organization
y
EDO (Extended Data-Output) access mode
y
2 CAS Byte/Word Read/Write operation
y
Single
5V
(
10%) power supply
y
TTL-compatible inputs and outputs
y
256-cycle refresh in 4ms
y
Refresh
modes
: RAS only, CAS BEFORE RAS (CBR)
and HIDDEN
y
JEDEC
standard
pinout
y
Key AC Parameter
t
RAC
t
CAC
t
RC
t
PC
-25
25
8
43
10
-30
30
9
55
12
-35
35
10
65
14
-40
40
11
75
16
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (TypeII)
PRODUCT NO.
PACKING TYPE
M11B11664A-25J
M11B11664A-30J
M11B11664A-35J
M11B11664A-40J
SOJ
M11B11664A-25T
M11B11664A-30T
M11B11664A-35T
M11B11664A-40T
TSOPII
GENERAL DESCRIPTION
The M11B11664A is a randomly accessed solid state memory, organized as 65,536 x 16 bits device. It offers Extended
Data-Output , 5V(
10%) single power supply. Access time (-25,-30,-35,-40) and package type (SOJ, TSOP II) are optional
features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
1
2
3
4
5
6
7
8
9
V
C C
I/O0
I/O1
I/O2
I/O3
V
C C
I/O4
I/O5
I/O6
40
39
38
37
36
35
34
33
32
V
S S
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
S S
I/O1 1
I/O1 0
I/O9
10
11
12
13
14
15
16
17
18
19
20
I/O7
N C
N C
W E
R A S
N C
A0
A1
A2
A3
V
C C
31
30
29
28
27
26
25
24
23
22
21
I/O8
N C
C A SL
C A S H
OE
N C
A7
A6
A5
A4
V
S S
1
2
3
4
5
6
7
8
9
10
V
C C
I/O 0
I/O 1
I/O 2
I/O 3
V
C C
I/O 4
I/O 5
I/O 6
I/O 7
N C
N C
W E
RA S
N C
A0
A1
A2
A3
V
C C
40
39
38
37
36
35
34
33
32
31
V
S S
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
V
S S
I/O 1 1
I/O 1 0
I/O 9
I/O 8
N C
C AS L
C AS H
O E
N C
A7
A6
A5
A4
V
S S
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
(OLWH07
M11B11664A
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3 2/15
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTIONS
PIN NO.
PIN NAME
TYPE
DESCRIPTION
16~19,22~25
A0~A7
Input
Address Input
Row Address : A0~A7
Column Address : A0~A7
14
RAS
Input
Row Address Strobe
28
CASH
Input
Column Address Strobe / Upper Byte Control
29
CASL
Input
Column Address Strobe / Lower Byte Control
13
WE
Input
Write Enable
27
OE
Input
Output Enable
2~5,7~10,31~34,36~39
I/O0 ~ I/O15
Input / Output Data Input / Output
1,6,20
V
CC
Supply
Power, 5V
21,35,40
V
SS
Ground
Ground
11,12,15,30
NC
-
No Connect
CONTROL
LOGIC
DATA-IN BUFFER
CLOCK
GENERATOR
DATA-OUT
BUFFER
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
REFRESH
COUNTER
ROW.
ADDRESS
BUFFERS(8)
9
A0
A1
A2
A3
A4
A5
A6
A7
COLUMN
DECODER
OE
16
R
O
W
DE
CO
DE
R
256 x 256 x 16
MEMORY
ARRAY
16
SENSE AMPLIFIERS
I/O GATING
8
256 x 16
V
CC
V
SS
IO0
:
IO15
RAS
CASH
256
256
8
8
8
8
8
CASL
V
BB
GENERATOR
WE
16
(OLWH07
M11B11664A
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3 3/15
ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss ... ......-1V to +7V
Operating Temperature, T
A
(ambient) ....0 C
to +70 C
Storage Temperature (plastic) ..........-55 C
to +150 C
Power Dissipation .......................................1.0W
Short Circuit Output Current ........................50mA
Permanent device damage may occur if "Absolute
Maximum Ratings" are exceeded. This is a stress rating
only, and functional operation of the device above those
conditions indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0 C
T
A
70 C
; V
CC
= 5V
10% unless otherwise noted)
PARAMETER
CONDITIONS
SYMBOL
MIN
MAX
UNITS NOTES
Supply Voltage
V
CC
4.5
5.5
V
1
Supply Voltage
V
SS
0
0
V
Input High Voltage
V
IH
2.4
V
CC
+1
V
1
Input Low Voltage
V
IL
-1.0
0.8
V
1
Input Leakage Current
0V
V
IH
7V
I
LI
-10
10
A
Output Leakage Current
0V
V
OUT
7V
Output(s) disable
I
LO
-10
10
A
Output High Voltage
I
OH
= -5 mA
V
OH
2.4
-
V
Output Low Voltage
I
OL
= 4.2 mA
V
OL
-
0.4
V
Note : 1.All Voltages referenced to V
SS
MAX
UNITS NOTES
PARAMETER
CONDITIONS
SYMBOL
-25 -30 -35 -40
Operating Current
RAS
, CAS cycling , t
RC
=min
I
CC1
170 150 130 120
mA
1,2
TTL interface , RAS , CAS = V
IH
,
D
OUT
=High-Z
4
4
4
4
mA
Standby Current
CMOS interface, RAS , CAS
V
CC
-0.2V
I
CC2
2
2
2
2
mA
RAS
only refresh Current
t
RC
= min
I
CC3
170 150 130 120
mA
2
EDO Page Mode Current
t
PC
= min
I
CC4
170 150 130 120
mA
1,3
Standby Current
RAS
=V
IH
, CAS = V
IL
I
CC5
5
5
5
5
mA
1
CAS
Before RAS Refresh
Current
t
RC
= min
I
CC6
170 150 130 120
mA
Note : 1. ICC max is specified at the output open condition.
2. Address can be changed twice or less while RAS =V
IL .
3. Address can be changed once or less while CAS =V
IH
.
(OLWH07
M11B11664A
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3 4/15
CAPACITANCE
(Ta = 25 C
, V
CC
= 5V
10%)
PARAMETER
SYMBOL
TYP
MAX
UNIT
Input Capacitance (address)
C
I1
-
5
pF
Input Capacitance ( RAS , CASH , CASL , WE , OE )
C
I2
-
7
pF
Output capacitance (I/O0~I/O15)
C
I / O
-
10
pF
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 to 70 C
, V
CC
=5V
10%, V
SS
= 0V) (note 14)
Test Conditions
Input timing reference levels : 0V, 3V
Output reference level : V
OL
= 0.8V, V
OH
=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed t
T
= 2ns
-25
-30
-35
-40
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT Notes
Read or Write Cycle Time
t
RC
43
55
65
75
ns
Read Write Cycle Time
t
RWC
65
85
95
105
ns
EDO-Page-Mode Read or Write Cycle
Time
t
PC
10
12
14
16
ns
22
EDO-Page-Mode Read-Write Cycle
Time
t
PCM
32
37
42
47
ns
22
Access Time From RAS
t
RAC
25
30
35
40
ns
4
Access Time From CAS
t
CAC
8
9
10
11
ns
5,20
Access Time From OE
t
OAC
8
9
10
11
ns
13,20
Access Time From Column Address
t
AA
12
15
18
20
ns
Access Time From CAS Precharge
t
ACP
14
17
20
22
ns
20
RAS
Pulse Width
t
RAS
25
10,000
30
10,000
35
10,000
40
10,000
ns
RAS
Pulse Width (EDO Page Mode)
t
RASC
25 100,000 30 100,000 35 100,000 40 100,000
ns
RAS
Hold Time
t
RSH
8
9
10
11
ns
25
RAS
Precharge Time
t
RP
15
20
25
30
ns
CAS
Pulse Width
t
CAS
4
10,000
5
10,000
5
10,000
6
10,000
ns
24
CAS
Hold Time
t
CSH
21
26
30
35
ns
19
CAS
Precharge Time
t
CP
4
4
5
5
ns
6,23
RAS
to CAS Delay Time
t
RCD
10
17
10
21
10
25
10
29
ns
7,18
CAS
to RAS Precharge Time
t
CRP
5
5
5
5
ns
19
Row Address Setup Time
t
ASR
0
0
0
0
ns
Row Address Hold Time
t
RAH
5
5
5
5
ns
RAS
to Column Address Delay Time
t
RAD
8
13
8
15
8
17
8
20
ns
8
Column Address Setup Time
t
ASC
0
0
0
0
ns
18
Column Address Hold Time
t
CAH
5
5
5
5
ns
18
Column Address Hold Time (Reference
to RAS )
t
AR
22
26
30
34
ns
Column Address to RAS Lead Time
t
RAL
12
15
18
20
ns
(OLWH07
M11B11664A
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3 5/15
(Continued)
-25
-30
-35
-40
UNIT
Notes
PARAMETER
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX
Read Command Setup Time
t
RCS
0
0
0
0
ns
15,18
Read Command Hold Time Reference to CAS
t
RCH
0
0
0
0
ns
9,15,19
Read Command Hold Time Reference to RAS
t
RRH
0
0
0
0
ns
9
CAS
to Output in Low-Z
t
CLZ
3
3
3
3
ns
20
Output Buffer Turn-off Delay From CAS or RAS
t
OFF1
3
15
3
15
3
15
3
15
ns
10,17,20
Output Buffer Turn-off to OE
t
OFF2
6
8
8
8
ns
17,26
Write Command Setup Time
t
WCS
0
0
0
0
ns
11,15,18
Write Command Hold Time
t
WCH
5
5
5
5
ns
15,25
Write Command Hold Time(Reference to RAS )
t
WCR
22
26
30
34
ns
15
Write Command Pulse Width
t
WP
5
5
5
5
ns
15
Write Command to RAS Lead Time
t
RWL
7
8
9
10
ns
15
Write Command to CAS Lead Time
t
CWL
5
6
7
8
ns
15,19
Data-in Setup Time
t
DS
0
0
0
0
ns
12,20
Data-in Hold Time
t
DH
5
5
5
5
ns
12,20
Data-in Hold Time (Reference to RAS )
t
DHR
22
26
30
34
ns
RAS
to WE Delay Time
t
RWD
34
46
51
56
ns
11
Column Address to WE Delay Time
t
AWD
21
31
34
36
ns
11
CAS
to WE Delay Time
t
CWD
17
25
26
27
ns
11,18
Transition Time (rise or fall)
t
T
1.5
50
1.5
50
2.5
50
2.5
50
ns
2,3
Refresh Period (256 cycles)
t
REF
4
4
4
4
ms
RAS
to CAS Precharge Time
t
RPC
10
10
10
10
ns
CAS
Setup Time(CBR REFRESH)
t
CSR
5
10
10
10
ns
1,18
CAS
Hold Time(CBR REFRESH)
t
CHR
7
10
10
10
ns
1,19
OE
Hold Time From WE During Read-Mode-
Write Cycle
t
OEH
4
4
4
5
ns
16
OE
Low to CAS High Setup Time
t
OES
4
4
4
5
ns
OE
High Hold Time From CAS High
t
OEHC
2
2
2
2
ns
OE
Precharge Time
t
OEP
2
2
2
2
ns
OE
Setup Prior to RAS During Hidden Refresh
Cycle
t
ORD
0
0
0
0
ns
Last CAS Going Low to First CAS Returning
High
t
CLCH
4
5
5
6
ns
21
Data Output Hold After CAS Returning Low
t
COH
3
3
3
3
ns
Output Disable Delay From WE
t
WHZ
3
7
3
7
3
7
3
7
ns
Read Setup Time Reference to RAS in CBR
t
RSR
5
5
5
5
ns
Read Hold Time Reference to RAS in CBR
t
RHR
5
5
5
5
ns
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