$%
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3 1/16
M11B16161A / M11B16161SA
M11L16161A
/
M11L16161SA
DRAM
1M x 16 DRAM
EDO PAGE MODE
FEATURES
y
X16
organization
y
EDO (Extended Data-Out) access mode
y
2 CAS Byte/Word Read/Write operation
y
Single power supply :
5V
10% Vcc for 5V product
3.3V
10% Vcc for 3.3V product
y
Interface for inputs and outputs
TTL-compatible for 5V products
LVTTL-compatible for 3.3V products
y
1024-cycle refresh in 16ms
y
Refresh
modes
: RAS only, CAS BEFORE RAS (CBR)
and HIDDEN capabilities,
y
Optional self-Refresh capabilities(S-ver. Only)
y
JEDEC
standard
pinout
y
Key AC Parameter
t
RAC
t
CAC
t
RC
t
PC
-45
45
11
77
16
-50
50
13
84
20
-60
60
15
104
25
ORDERING INFORMATION - PACKAGE
42-pin 400mil SOJ
44 / 50-pin 400mil TSOP (TypeII)
PRODUCT NO.
Refresh Vcc
PACKING
TYPE
M11B16161A-45J/50J/60J
Normal
M11B16161SA-45J/50J/60J
*Self-
Refresh
5V
M11L16161A-45J/50J/60J
Normal
M11L16161SA-45J/50J/60J
Self-
Refresh
3.3V
SOJ
M11B16161A-45T/50T/60T
Normal
M11B16161SA-45T/50T/60T
*Self-
Refresh
5V
M11L16161A-45T/50T/60T
Normal
M11L16161SA-45T/50T/60T
Self-
Refresh
3.3V
TSOPII
* Ordered by special request
GENERAL DESCRIPTION
The M11B16161/M11L16161 series is a randomly accessed solid state memory, organized as 1,048,576 x 16 bits device. It
offers Extended Data-Output access mode. Single power supply (5V
10%, 3.3V
10%), access time (-45,-50,-60), self-
refresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before -
RAS
, RAS -only refresh and Hidden refresh.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
1
2
3
4
5
6
7
8
9
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
42
41
40
39
38
37
36
35
34
V
S S
I/O15
I/O14
I/O13
I/O12
V
S S
I/O11
I/O10
I/O9
10
11
12
13
14
15
16
17
18
19
20
21
I/O7
N C
N C
W E
R A S
N C
N C
A0
A1
A2
A3
V
C C
33
32
31
30
29
28
27
26
25
24
23
22
I/O8
N C
C ASL
C A S H
OE
A9
A8
A7
A6
A5
A4
V
S S
1
2
3
4
5
6
7
8
9
1 0
1 1
V
CC
I/O 0
I/O 1
I/O 2
I/O 3
V
CC
I/O 4
I/O 5
I/O 6
I/O 7
N C
N C
N C
W E
R A S
N C
N C
A0
A1
A2
A3
V
CC
V
S S
I/O1 5
I/O1 4
I/O1 3
I/O1 2
V
S S
I/O1 1
I/O1 0
I/O 9
I/O 8
N C
N C
CA SL
C A S H
OE
A9
A8
A7
A6
A5
A4
V
S S
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
$%
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3 2/16
M11B16161A / M11B16161SA
M11L16161A
/
M11L16161SA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTIONS
PIN NO.
(SOJ Package)
PIN NAME
TYPE
DESCRIPTION
17~20, 23~28
A0~A9
Input
Address Input
Row Address : A0~A9
Column Address : A0~A9
14
RAS
Input
Row Address Strobe
30
CASH
Input
Column Address Strobe / Upper Byte Control
31
CASL
Input
Column Address Strobe / Lower Byte Control
13
WE
Input
Write Enable
29
OE
Input
Output Enable
2~5,7~10,33~36,38~41
I/O0 ~ I/O15
Input / Output
Data Input / Output
1,6,21
V
CC
Supply
Power, (5V or 3.3V)
22,37,42
V
SS
Ground
Ground
11,12,15,16,32
NC
-
No Connect
CONTROL
LOGIC
DATA-IN BUFFER
CLOCK
GENERATOR
DATA-OUT
BUFFER
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
REFRESH
COUNTER
ROW.
ADDRESS
BUFFERS(10)
A0
A1
A2
A3
A4
A5
A6
A7
COLUMN
DECODER
OE
16
R
O
W
DE
CO
DE
R
1024 x 1024 x 16
MEMORY
ARRAY
16
SENSE AMPLIFIERS
I/O GATING
8
1024 x 16
V
CC
V
SS
IO0
:
IO15
RAS
CASH
1024
1024
10
10
10
10
CASL
V
BB
GENERATOR
WE
16
A8
A9
10
$%
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3 3/16
M11B16161A / M11B16161SA
M11L16161A
/
M11L16161SA
ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss
5V Product ... ......-1V to +7V
3.3V Product ... ......-0.5V to +4.6V
Operating Temperature, T
A
(ambient) ....0 C
to +70 C
Storage Temperature (plastic) ..........-55 C
to +150 C
Power Dissipation .......................................1.0W
Short Circuit Output Current ........................50mA
Permanent device damage may occur if "Absolute
Maximum Ratings" are exceeded. This is a stress rating
only, and functional operation of the device above those
conditions indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0 C
T
A
70 C
)
3.3V
5V
PARAMETER
CONDITIONS
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Supply Voltage
V
CC
3.0
3.6
4.5
5.5
V
1
Supply Voltage
V
SS
0
0
0
0
V
Input High Voltage
V
IH
2.0
V
CC
+0.3
2.4
V
CC
+0.3
V
1
Input Low Voltage
V
IL
-1.0
0.8
-1.0
0.8
V
1
Input Leakage Current
0V
V
IN
V
IH(max)
I
LI
-10
10
-10
10
A
Output Leakage Current
0V
V
OUT
V
CC
Output(s) disable
I
LO
-10
10
-10
10
A
5V
I
OH
= -5 mA
Output High Voltage
3.3V
I
OH
= -2 mA
V
OH
2.4
-
2.4
-
V
5V
I
OL
= 4.2 mA
Output Low Voltage
3.3V
I
OL
= 2 mA
V
OL
-
0.4
-
0.4
V
Note : 1.All Voltages referenced to V
SS
MAX
PARAMETER
CONDITIONS
SYMBOL
-45
-50
-60
UNITS NOTES
Operating Current
RAS
, CAS cycling , t
RC
=min
I
CC1
150
140
130
mA
1,2
TTL interface , RAS , CAS = V
IH
,
D
OUT
=High-Z
4
4
4
mA
Standby Current
CMOS interface, RAS , CAS
V
CC
-0.2V
I
CC2
2
2
2
mA
RAS
only refresh Current
t
RC
= min
I
CC3
150
140
130
mA
2
EDO Page Mode Current
t
PC
= min
I
CC4
150
140
130
mA
1,3
CAS
Before RAS Refresh
Current
t
RC
= min
I
CC6
150
140
130
mA
Battery Backup Current
(S-ver. Only)
Standby with CBR refresh, t
RC
= 62.4us
t
RAS
300ns, D
OUT
=Hi-Z, CMOS interface
I
CC7
500
500
500
A
Self Refresh Current
(S-ver. Only)
RAS
, CAS
0.2V, D
OUT
=Hi-Z, CMOS
interface
I
CC8
500
500
500
A
Note : 1. I
CC
max is specified at the output open condition.
2. Address can be changed twice or less while RAS =V
IL .
3. Address can be changed once or less while CAS =V
IH
.
$%
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3 4/16
M11B16161A / M11B16161SA
M11L16161A
/
M11L16161SA
CAPACITANCE
(Ta = 25 C
, V
CC
= 5V
10% or 3.3V
10%)
PARAMETER
SYMBOL
TYP
MAX
UNIT
Input Capacitance (address)
C
I1
-
5
pF
Input Capacitance ( RAS , CASH , CASL , WE , OE )
C
I2
-
7
pF
Output capacitance (I/O0~I/O15)
C
I / O
-
10
pF
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 to 70 C
, V
CC
=5V
10% or 3.3V
10%, V
SS
= 0V) (note 14)
Test Conditions
Input timing reference levels : 0.8V, 2.4V (for 5V power supply), 0.8V, 2.0V (for 3.3V power supply)
Output reference level : V
OL
= 0.8V, V
OH
=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed t
T
= 2ns
-45
-50
-60
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT Notes
Read or Write Cycle Time
t
RC
77
84
104
ns
Read Write Cycle Time
t
RWC
97
110
135
ns
EDO-Page-Mode Read or Write Cycle
Time
t
PC
16
20
25
ns
22
EDO-Page-Mode Read-Write Cycle
Time
t
PCM
53
58
68
ns
22
Access Time From RAS
t
RAC
45
50
60
ns
4
Access Time From CAS
t
CAC
11
13
15
ns
5,20
Access Time From OE
t
OAC
11
13
15
ns
13,20
Access Time From Column Address
t
AA
22
25
30
ns
Access Time From CAS Precharge
t
ACP
25
28
33
ns
20
RAS
Pulse Width
t
RAS
45
10,000
50
10,000
60
10,000
ns
RAS
Pulse Width (EDO Page Mode)
t
RASC
45
100,000
50
100,000
60
100,000
ns
RAS
Hold Time
t
RSH
6
7
10
ns
25
RAS
Precharge Time
t
RP
28
30
40
ns
CAS
Pulse Width
t
CAS
6
10,000
7
10,000
10
10,000
ns
24
CAS
Hold Time
t
CSH
35
37
40
ns
19
CAS
Precharge Time
t
CP
6
7
10
ns
6,23
RAS
to CAS Delay Time
t
RCD
10
34
11
37
14
45
ns
7,18
CAS
to RAS Precharge Time
t
CRP
5
5
5
ns
19
Row Address Setup Time
t
ASR
0
0
0
ns
Row Address Hold Time
t
RAH
6
7
10
ns
RAS
to Column Address Delay Time
t
RAD
8
23
9
25
12
30
ns
8
Column Address Setup Time
t
ASC
0
0
0
ns
18
Column Address Hold Time
t
CAH
6
7
10
ns
18
Column Address Hold Time (Reference
to RAS )
t
AR
40
44
55
ns
Column Address to RAS Lead Time
t
RAL
23
25
30
ns
Column Address setup to CAS
precharge
t
ACH
10
11
13
ns
$%
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2001
Revision : 1.3 5/16
M11B16161A / M11B16161SA
M11L16161A
/
M11L16161SA
(Continued)
-45
-50
-60
UNIT
Notes
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Read Command Setup Time
t
RCS
0
0
0
ns
15,18
Read Command Hold Time Reference to CAS
t
RCH
0
0
0
ns
9,15,19
Read Command Hold Time Reference to RAS
t
RRH
0
0
0
ns
9
CAS
to Output in Low-Z
t
CLZ
0
0
0
ns
20
Output Buffer Turn-off Delay From CAS or RAS
t
OFF1
0
11
0
13
0
15
ns
10,17,20
Output Buffer Turn-off to OE
t
OFF2
0
11
0
13
0
15
ns
17,26
Write Command Setup Time
t
WCS
0
0
0
ns
11,15,18
Write Command Hold Time
t
WCH
6
7
10
ns
15,25
Write Command Hold Time(Reference to RAS )
t
WCR
40
44
55
ns
15
Write Command Pulse Width
t
WP
6
7
10
ns
15
Write Command to RAS Lead Time
t
RWL
11
13
15
ns
15
Write Command to CAS Lead Time
t
CWL
6
7
10
ns
15,19
Data-in Setup Time
t
DS
0
0
0
ns
12,20
Data-in Hold Time
t
DH
6
7
10
ns
12,20
Data-in Hold Time (Reference to RAS )
t
DHR
40
44
55
ns
RAS
to WE Delay Time
t
RWD
57
67
79
ns
11
Column Address to WE Delay Time
t
AWD
34
42
49
ns
11
CAS
to WE Delay Time
t
CWD
23
30
34
ns
11,18
Transition Time (rise or fall)
t
T
1
50
1
50
1
50
ns
2,3
Refresh Period (1024 cycles)
t
REF
16
16
16
ms
Refresh Period (1024 cycles) Self Refresh
t
REF
64
64
64
ms
RAS
to CAS Precharge Time
t
RPC
5
5
5
ns
CAS
Setup Time(CBR REFRESH)
t
CSR
5
5
5
ns
1,18
CAS
Hold Time(CBR REFRESH)
t
CHR
10
10
10
ns
1,19
OE
Hold Time From WE During Read-Mode-Write
Cycle
t
OEH
6
7
10
ns
16
OE
Low to CAS High Setup Time
t
OES
5
5
5
ns
OE
High Hold Time From CAS High
t
OEHC
2
2
2
ns
OE
Precharge Time
t
OEP
2
2
2
ns
OE
Setup Prior to RAS During Hidden Refresh
Cycle
t
ORD
0
0
0
ns
Last CAS Going Low to First CAS Returning High
t
CLCH
6
7
10
ns
21
Data Output Hold After CAS Returning Low
t
COH
3
3
3
ns
Output Disable Delay From WE
t
WHZ
0
11
0
13
0
15
ns
Self Refresh RAS Low Pulse width
t
RASS
100
100
100
us
27,28
Self Refresh RAS High Precharge Time
t
RPS
77
84
104
ns
27,28
Self Refresh CAS Hold Time
t
CHS
-50
-50
-50
ns
27,28
Read Setup Time Reference to RAS in CBR/SR
t
RSR
0
0
0
ns
27,28
Read Hold Time Reference to RAS in CBR/SR
t
RHR
6
7
10
ns
27,28
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