ChipFind - документация

Электронный компонент: M21L216128A-12T

Скачать:  PDF   ZIP
$%
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 1/14
SRAM
128 K x 16 SRAM
HIGH SPEED CMOS SRAM
FEATURES
ORDERING INFORMATION
T
Fast access times : 10, 12, and 15ns
T
Fast OE access times : 5, 6, and 7ns
T
Single +3.3V
0.3V power supply
T
Fully static -- no clock or timing strobes necessary
T
All inputs and outputs are TTL-compatible
T
Three state outputs
T
Center power and ground pins for greater noise immunity
T
Easy memory expansive with CE and OE options
T
Automatic CE power down
T
+LJKSHUIRUPDQFH ORZSRZHU FRQVXPSWLRQ &026
WULSOHSRO\ GRXEOHPHWDO SURFHVV
44-pin 400mil SOJ
44-pin 400mil TSOP (TypeII)
PRODUCT NO.
Acess Time
(ns)
PACKING
TYPE
M21L216128A-10J
SOJ
M21L216128A-10T
10
TSOP
M21L216128A-12J
SOJ
M21L216128A-12T
12
TSOP
M21L216128A-15J
SOJ
M21L216128A-15T
15
TSOP
GENERAL DESCRIPTION
The M21L216128A is a high speed, low power
asynchronous SRAM containing 2,097,152 bits and
organized as 131,072 by 16 bits, it is produced by high
performance CMOS process.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enable ( CE ), separate byte
enable controls ( LB and HE ) and output enable ( OE ) with this
organization.
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
1
2
3
4
5
6
7
8
9
A4
A3
A2
A1
A0
C E
D Q1
D Q2
D Q3
44
43
42
41
40
39
38
37
36
A5
A6
A7
OE
H B
LB
DQ 1 6
DQ 1 5
DQ 1 4
10
11
12
13
14
15
16
17
18
19
20
21
22
D Q 4
V C C
G N D
D Q 5
D Q 6
D Q 7
D Q 8
W E
A1 6
A1 5
A1 4
A1 3
A1 2
35
34
33
32
31
30
29
28
27
26
25
24
23
DQ 1 3
G N D
V C C
DQ 1 2
DQ 1 1
DQ 1 0
D Q9
N C
A8
A9
A10
A11
N C
1
2
3
4
5
6
7
8
9
1 0
1 1
A 4
A 3
A 2
A 1
A 0
C E
D Q 1
D Q 2
D Q 3
D Q 4
V C C
G N D
D Q 5
D Q 6
D Q 7
D Q 8
W E
A 1 6
A 1 5
A 1 4
A 1 3
A 1 2
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
A 5
A 6
A 7
O E
H B
L B
D Q 1 6
D Q 1 5
D Q 1 4
D Q 1 3
G N D
V C C
D Q 1 2
D Q 1 1
D Q 1 0
D Q 9
N C
A8
A9
A 1 0
A 1 1
N C
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
$%
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 2/14
Block Diagram
512 X 4096
MEMORY ARRAY
DQ9
Pin Descriptions
Pin No.
Symbol
Description
1 - 5, 18 - 22,
24-27, 42 - 44
A0 - A16
Address Inputs
6
CE
Chip Enable Input
7 - 10, 13 - 16,
29 - 32, 35 - 38
DQ1 - DQ16
Data Inputs/Outputs
17
WE
Write Enable Input
39
LB
Lower Byte Enable Input (DQ1 to DQ8)
40
HB
Higher Byte Enable Input (DQ9 to
DQ16)
41
OE
Output Enable Input
11, 33
VCC
Power
12, 34
GND
Ground
23, 28
NC
No Connection
$%
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 3/14
ABSOLUTE MAXIMUM RATINGS *
Voltage on V
CC
Supply Relative to Vss ... ......-0.5V to +4.6V
V
IN
......................................................-0.5V to V
CC
+1.0V
Operating Temperature, Topr ....................... 0 C
to +70 C
Storage Temperature (plastic) ...................-55 C
to +125 C
Junction Temperature ..........................................+125 C
Power Dissipation ...................................................1.0W
Short Circuit Output Current ....................................50mA
*Stresses greater than those listed under Absolute
Maximum. Ratings may permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS
(All Temperature Ranges ; V
CC
= 3.3V
0.3V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS NOTES
Input High (Logic 1) Voltage
V
IH
2.2
V
CC
+0.5
V
1,2
Input Low (Logic 0) Voltage
V
II
-0.5
0.8
V
1,2
Input Leakage Current
0V
V
IN
V
CC
I
LI
-10
10
A
Output Leakage Current
Output(s) disable
0V
V
OUT
V
CC
I
LO
-5
5
A
Output High Voltage
I
OH
= -4.0 mA
V
OH
2.4
V
1
Output Low Voltage
I
OL
= 8.0 mA
V
OL
0.4
V
1
Supply Voltage
V
CC
3.0
3.6
V
1
MAX
DESCRIPTION
CONDITIONS
SYMBOL
-10
-12
-15
UNITS
NOTES
Power Supply
Current : Operating
Device selected; CE
V
IL
; V
CC
=MAX;
f=f
MAX
; outputs open
I
CC
190
160
130
mA
3
TTL Standby
CE
V
IH
; V
CC
=MAX; f=f
MAX
I
SB1
35
30
25
mA
CMOS Standby
1
CE
V
CC
-0.2; V
CC
= MAX;
all other inputs
GND +0.2 or
V
CC -
0.2;
all inputs static ; f=0
I
SB2
10
10
10
mA
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
MAX
UNITS NOTES
Input Capacitance
C
I
6
pF
4
Input/Output Capacitance(DQ)
T
A
=
C
25
; f=1 MHz
V
CC
=3.3V
C
I/O
8
pF
4
$%
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 4/14
AC ELECTRICAL CHARACTERISTICS
(Note 5)(All Temperature Ranges; V
CC
=3.3V
0.3V)
-10
-12
-15
Notes
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Read Cycle
Read Cycle Time
t
RC
10
12
15
ns
Access access time
t
AA
10
12
15
ns
Chip Enable access time
t
ACE
10
12
15
ns
Output hold from address change
t
OH
3
4
4
ns
Chip Enable to output in Low-Z
t
CLZ
3
4
4
ns
4,7
Chip disable to output in High-Z
t
CHZ
5
6
7
ns
4,6,7
Output Enable access time
t
OE
5
6
7
ns
Output Enable to output in Low-Z
t
OLZ
0
0
0
ns
Output Disable to output in High-Z
t
OHZ
5
6
7
ns
4,6
Byte Enable access time
t
BE
6
7
8
ns
Byte Enable to output in Low-Z
t
BLZ
0
0
0
ns
4,7
Byte disable to output in High-Z
t
BHZ
5
6
7
ns
4,6,7
Write Cycle
Write cycle time
t
WC
10
12
15
ns
Chip Enable to end of write
t
CW
8
8
9
ns
Address valid to end of write, with
OE
HIGH
t
AW
8
8
9
ns
Address setup time
t
AS
0
0
0
ns
Address hold from end of write
t
WR
0
0
0
ns
Write pulse width
t
WP2
10
10
11
ns
Write pulse width, with OE HIGH
t
WP1
8
8
9
ns
Data setup time
t
DW
5
6
7
ns
Data hold time
t
DH
0
0
0
ns
Write disable to output in Low-Z
t
OW
3
4
5
ns
4,7
Byte Enable to output in High-Z
t
WHZ
5
6
7
ns
4,6,7
Byte Enable to end of write
t
BW
8
8
9
ns
$%
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 5/14
TRUTH TABLE
MODE
CE
WE
OE
LE
HE
DQ1-DQ8
DQ9-DQ16
POWER
LOW BYTE READ (DQ1-DQ8)
L
H
L
L
H
Q
HIGH-Z
ACTIVE
HIGH BYTE READ (DQ9-DQ16)
L
H
L
H
L
HIGH-Z
Q
ACTIVE
WORD READ (DQ1-DQ16)
L
H
L
L
L
Q
Q
ACTIVE
LOW BYTE WRITE (DQ1-DQ8)
L
L
X
L
H
D
HIGH-Z
ACTIVE
HIGH BYTE WRITE (DQ9-DQ16)
L
L
X
H
L
HIGH-Z
D
ACTIVE
WORD WRITE (DQ1-DQ16)
L
L
X
L
L
D
D
ACTIVE
L
X
X
H
H
HIGH-Z
HIGH-Z
ACTIVE
OUTPUT DISABLE
L
H
H
X
X
HIGH-Z
HIGH-Z
ACTIVE
STANDBY
H
X
X
X
X
HIGH-Z
HIGH-Z
STANBY
AC TEST CONDITIONS
Input plus levels
0V to 3.0V
Input rise and fail times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
DQ
351
DQ
5pF
Z0 =50
30pF
50
3.3V
317
Vt=1.5V
Fig.1 OUTPUT LOAD EQUIVALENT
Fig.2 OUTPUT LOAD EQUIVALENT