256K x 8
Radiation Hardened
Static RAM MCM 5 V

201A072
225A837

BAE SYSTEMS · 9300 Wellington Road · Manassas, Virginia 20110-4122

Product Description

Radiation

· Fabricated with Bulk CMOS 0.5 µm Process

· Total Dose Hardness through 1x10

rad(Si)

· Neutron Hardness through 1x10

N/cm

· Dynamic and Static Transient Upset Hardness

through 1x10

rad(Si)/s

· Soft Error Rate of < 1x10

-11

Upsets/Bit-Day

· Dose Rate Survivability through 1x10

rad(Si)/s

· Latchup Free

Features

Other

· Read/Write Cycle Times

30 ns (-55°C to 125°C)

· SMD Number 5962H99541

· Asynchronous Operation

· CMOS or TTL Compatible I/O

· Single 5 V ±10% Power Supply

· Low Operating Power

· Packaging Options

· 40-Lead Dual Flat Pack (0.855" x 0.710")

General Description

The 256K x 8 radiation hardened static RAM is
composed of two 128K x 8 SRAM memory die
assembled in a single, double-sided ceramic
substrate. Each die is a high performance
131,072 word x 8-bit static random access
memory with industry-standard functionality. It
is fabricated with BAE SYSTEMS' radiation
hardened technology and is designed for use in
systems operating in radiation environments.
The RAM operates over the full military
temperature range and requires a single 5 V
±10% power supply. The RAM is available with
either TTL or CMOS compatible I/O. Power
consumption is typically less than 40 mW/MHz
in operation, and less than 20 mW in the low
power disabled mode. The RAM read operation
is fully asynchronous, with an associated
typical access time of 19 nanoseconds.

BAE SYSTEMS' enhanced bulk CMOS
technology is radiation hardened through the
use of advanced and proprietary design, layout,
and process hardening techniques.

Functional Diagram for Top and Bottom SRAMs

Signal Definitions

A: 0-16

DQ: 0-7

(Bottom)

(Top)

Address input pins that select a particular

eight-bit word within the memory array.

Bi-directional data pins that serve as data

outputs during a read operation and as data
inputs during a write operation.

Negative chip select, when at a low level,

allows normal read or write operation. When at
a high level, S1 or S2 forces the SRAM to a
precharge condition, holds the data output
drivers in a high impedance state and disables
the data input buffers only. If this signal is not
used, it must be connected to GND.

Negative write enable, when at a low level, activates a

write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.

Negative output enable, when at a high level holds the

data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S1
or S2, W, and E. If this signal is not used it must be
connected to GND.

Chip enable, when at a high level allows normal

operation. When at a low level, E forces the SRAM to a
precharge condition, holds the data output drivers in a
high impedance state and disables all the input buffers
except the S1 or S2 input buffer. If this signal is not
used, it must be connected to V

Notes:

1) V

for don't care (X) inputs = V

or V

2) When G = high, I/O is high-Z.

3) To dissipate the minimum amount of
standby power when in standby mode:
S1 = S2 = V

. All other input levels may

float.

Truth Table

A1 - A2

A9 - A16

S1; S2

DQ0-DQ7

A4-A8

Top/Bottom Decoder

Block Address Decoder

L/R Side/Block

Row Address Decoder

((256 x 32) x 2 x 4) x 8 x 2

Memory Cell Array

8 Bit Word Input/Output

Column Address Decoder

Note:

1) All package leads are common for

top and bottom SRAM devices
except S1 for bottom SRAM and
S2 for top SRAM.

Mode

Inputs

(1),(2)

High

Low

High

Low

High

Low

High

Low

High

Low

I/O

Data-In

Data-Out

High-Z

Data-In

Data-Out

Power

Active

Standby

Active

Write1

Standby

(3)

Write2

High

Low

Notes:

Note:

1)All voltages referenced to GND.

Power shall be applied to the device only in the following

sequences to prevent damage due to excessive currents:

· Power-Up Sequence: GND, V

, Inputs

· Power-Down Sequence: Inputs, V

, GND

Absolute Maximum Ratings

Recommended Operating Conditions

Power Sequencing

Minimum

+4.5

0.0

-55

-0.3

0.0

+2.0

+3.5

Units

Volt

Celsius

Volt

Supply Voltage

Parameters

(1)

Supply Voltage Reference

Case Temperature

Input Logic "Low" - CMOS

Input Logic "Low" - TTL

Input Logic "High" - TTL

Input Logic "High" - CMOS

Symbol

GND

Maximum

+5.5

0.0

+125

+1.5

+0.8

Minimum

-70°C

-55°C

-0.5 V

(Class II)

Storage Temperature Range (Ambient)

Applied Conditions

(1)

Operating Temperature Range (T

case

)

Positive Supply Voltage

Input Voltage

(2)

Output Voltage

(2)

Power Dissipation

(3)

Lead Temperature (Soldering 5 sec)

Electrostatic Discharge Sensitivity

(4)

Maximum

+150°C

+125°C

+7.0 V

+ 0.5 V

2.0 W

+250°C

+ 0.5 V

1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.

2) Maximum applied voltage shall not exceed +7.0 V.

3) Guaranteed by design; not tested.

4) Class as defined in MIL-STD-883, Method 3015.

300

± 10%

2.8V

50 pF ± 10%

Output Load Circuit

DC Electrical Characteristics

1) Typical operating conditions: -55°C

case

+125°C; 4.5 V

5.5 V; unless otherwise specified.

2) S1 or S2 high, W high, or E low must occur while address transitions.
3) Guaranteed by design and verified by periodic characterization.

Notes:

Device Type

Limits

All

Minimum

4.0

2.5

-10

- 0.5 V

3.5

2.0

Test

Supply Current
(Cycling Selected)

Supply Current
(Cycling De-Selected)

Supply Current
(Standby)

Data Retention Current

Data Retention Voltage

Input Leakage

Output Leakage

out

High Level Output Voltage

Low Level Output Voltage

High Level Input Voltage

Low Level Input Voltage

Symbol

DD1

DD2

DD3

(2)

ILK

OLK

CMOS Engineering

Level + TTL

All CMOS (Except

Engineering Level)

CMOS Engineering

Level + TTL

All CMOS (Except

Engineering Level)

All (Except

Engineering Level)

Engineering Level

All (Except

Engineering Level)

Engineering Level

All (Except

Engineering Level)

Engineering Level

All (Except

Engineering Level)

Maximum

0.05

1.5

0.8

0.5

2.0

4.0

8.0

4.0

8.0

182

186

Units

µA

Engineering Level

S2 = V

and S1 = GND) or

Test Conditions

(1)

= 2.5 V

= V

0 V

5.5 V

By Design/
Verified By
Characterization

= -200 µA

= -4 mA

= 200 µA

CMOS

TTL

0 V

OUT

5.5 V

By Design/
Verified By
Characterization

= 8 mA

F = 0 MHz

E = GND

S1 = S2 = V

F = F

MAX

= 1/t

AVAV(min)

E = GND

S1 = S2 = V

F = F

MAX

= 1/t

AVAV(min)

E = V

No Output Load

S1 = V

and S2 = GND)

(3)

Read Cycle AC Timing Characteristics

(1)

Notes:

Device Type

Units

Test

Read Cycle Time

Chip Select to Output Active

Output Enable to Output Active

Chip Enable to Output Active

Address Access Time

Chip Select Access Time

Chip Enable Access Time

Chip Select to Output Disable

Chip Disable to Output Disable

Output Hold After Address Change

Output Enable to Output Disable

Chip Select1 to Chip Select2

(3)

Chip Select2 to Chip Select1

(3)

Output Enable Access Time

Minimum or

Maximum

Minimum

Maximum

Minimum

Maximum

Minimum

Maximum

X3X CMOS, TTL

X3X

X43 CMOS

X41, 2, 4 - 7 CMOS, X43 TTL

X4X

All

Limits

All

Symbol

AVAV

(2)

AVQV

SLQV

EHQV

GLQV

SLQX

EHQX

GLQX

SHQZ

AHQX

ELQZ

GHQZ

S1HS2L

S2HS1L

1) Test conditions: input switching levels V

= 0.5 V/V

- 0.5 V (CMOS), V

= 0 V/3 V (TTL), input rise

and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics
table, capacitive output loading = 50 pF. For C

= 50 pF, derate access times by 0.02 ns/pF (typical).

-55°C

case

+125°C; 4.5 V

5.5 V; unless otherwise specified.

2) Cycle time per individual die.
3) Parameter is guaranteed but not tested. Parameter is the sum of t

SLQX

and t

SHQZ

; both of these parameters

are tested.

Note:

1) Test conditions: input switching levels V

= 0.5 V/V

- 0.5 V (CMOS), V

= 0 V/3 V (TTL), input rise and

fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics table,
capacitive output loading = 50 pF. -55°C

case

+125°C; 4.5 V

5.5 V; unless otherwise specified.

Write Cycle AC Timing Characteristics

(1)

AVAV

AVWH

SLWH

EHWH

WLWH

WHDX

AVWL

WHAX

WLQZ

WHQX

WHWL

DVWH

Symbol

Device Type

Test

Write Cycle Time

Data Setup to End of Write

Data Hold After End of Write

Address Setup to End of Write

Chip Select to End of Write

Chip Enable to End of Write

Address Hold After End of Write

Write Enable to Output Disable

Address Setup to Start of Write

Output Active After End of Write

Write Disable Pulse Width

Write Pulse Width Access Time

Minimum or

Maximum

Minimum

Maximum

Minimum

All

Units

Limits

X3X CMOS, TTL

All CMOS

X3X CMOS, TTL

All CMOS

All CMOS and X4X TTL

X43 CMOS

X4X TTL

X43 CMOS

X41, 2, 4 - 7 CMOS, X43 TTL

X3X TTL

X41, 2, 4 - 7 CMOS, X43 TTL

All TTL

X3X TTL

Dynamic Electrical Characteristics

Select1 to Select2 Timing Diagram

S1HS2L

S2HS1L

Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (S1 or S2), or
chip enable (E) (refer to Read Cycle Timing diagram). To
perform a valid read operation, both chip select and output
enable (G) must be low and chip enable and write enable
(W) must be high. The output drivers can be controlled
independently by the G signal. Consecutive read cycles can
be executed with S1 or S2 held continuously low, and with E
held continuously high, and toggling the addresses.

For an address-activated read cycle, S1 or S2 and E must
be valid prior to or coincident with the activating address
edge transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid t

AVQV

time following the latest

occurring address edge transition. The minimum address
activated read cycle time is t

AVAV

. When the RAM is

operated at the minimum address-activated read cycle time,
the data outputs will remain valid on the RAM I/O until t

AXQX

time following the next sequential address transition.

To control a read cycle with S1 or S2, all addresses and E
must be valid prior to or coincident with the enabling S1 or
S2 edge transition. Address or E edge transitions can occur
later than the specified setup times to S1 or S2; however,
the valid data access time will be delayed. Any address
edge transition, that occurs during the time when S1 or S2 is
low, will initiate a new read access, and data outputs will not
become valid until t

AVQV

time following the address edge

transition. Data outputs will enter a high impedance state
t

SHQZ

time following a disabling S1 or S2 edge transition.

To control a read cycle with E, all addresses and S1 or S2
must be valid prior to or coincident with the enabling E edge
transition. Address or S1 or S2 edge transitions can occur
later than the specified setup times to E; however, the valid
data access time will be delayed. Any address edge
transition that occurs during the time when E is high will
initiate a new read access, and data outputs will not become
valid until t

AVQV

time following the address edge transition.

Data outputs will enter a high impedance state t

ELQZ

time

following a disabling E edge transition.

Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable (W),
chip select (S1 or S2), or chip enable (E) edge transitions
(refer to Write Cycle Timing diagrams). To perform a write
operation, both W and S1 or S2 must be low, and E must
be high. Consecutive write cycles can be performed with
W or S1 or S2 held continuously low, or E held
continuously high. At least one of the control signals must
transition to the opposite state between consecutive write
operations.

The write mode can be controlled via three different
control signals: W, S1 or S2, and E. All three modes of
control are similar except the S1 or S2 and E controlled
modes actually disable the RAM during the write recovery
pulse. Only the W controlled mode is shown in the table
and diagram on the previous page for simplicity.
However, each mode of control provides the same write
cycle timing characteristics. Thus, some of the parameter
names referenced below are not shown in the write cycle
table or diagram, but indicate which control pin is in
control as it switches high or low.

To write data into the RAM, W and S1 or S2 must be held
low and E must be held high for at least t

WLWH

SLSH

EHEL

time. Any amount of edge skew between the signals can
be tolerated and any one of the control signals can initiate
or terminate the write operation. For consecutive write
operations, write pulses must be separated by the
minimum specified t

WHWL

SHSL

ELEH

time. Address inputs

must be valid at least t

AVWL

AVSL

AVEH

time before the

enabling W/S1 or S2/E edge transition, and must remain
valid during the entire write time. A valid data overlap of
write pulse width time of t

DVWH

DVSH

DVEL

, and an address

valid to end of write time of t

AVWH

AVSH

AVEL

also must be

provided for during the write operation. Hold times for
address inputs and data inputs with respect to the
disabling W/S1 or S2/E edge transition must be a
minimum of t

WHAX

SHAX

ELAX

time and t

WHDX

SHDX

ELDX

time,

respectively. The minimum write cycle time is t

AVAV

Radiation Characteristics

Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after a total ionizing radiation dose of 1x10

rad(Si). All

electrical and timing performance parameters will remain
within specifications after rebound at V

= 5.5 V and T =

125°C extrapolated to ten years of operation. Total dose
hardness is assured by wafer level testing of process monitor
transistors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations
have been made between 10 keV X-rays applied at a dose
rate of 1x10

rad(Si)/min at T = 25°C and gamma rays (Cobalt

60 source) to ensure that wafer level X-ray testing is
consistent with standard military radiation test environments.

Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining stored
data during and after exposure to a transient ionizing radiation
pulse of

50 ns duration up to 1x10

rad(Si)/s, when applied

under recommended operating conditions. To ensure validity
of all specified performance parameters before, during, and
after radiation (timing degradation during transient pulse
radiation is

10%), stiffening capacitance can be placed on

the package between the package (chip) V

and GND with

the inductance between the package (chip) and stiffening
capacitance kept to a minimum. If there are no operate-
through or valid stored data requirements, typical de-coupling
capacitors should be mounted on the circuit board as close as
possible to each device.

The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse of

50 ns

duration up to 1x10

rad(Si)/s, when applied under

recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must
accommodate these effects.

Neutron Radiation
The SRAM will meet any functional or timing specification
after a total neutron fluence of up to 1x10

-2

applied

under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.

Soft Error Rate
The SRAM has a soft error rate (SER) performance of
<1x10

-11

upsets/bit-day, under recommended operating

conditions. This hardness level is defined by the Adams
90% worst case cosmic ray environment.

Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions.

Radiation Hardness Ratings

(1),(2)

Notes:
1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan.
2) Device electrical characteristics are guaranteed for post irradiation levels at 25°C.
3) 90% worst case particle environment, geosynchronous orbit, 0.025'' of aluminum shielding.

Specification set using the CREME code upset rate calculation method with a 2 µm epi thickness.

4) Immune for LET

120 MeV/mg/cm

Conditions

Characteristics

Total Dose

Single Event Upset

(3)

Prompt Dose Upset

Single Event Induced Latchup

Survivability

Single Event Upset

(3)

Neutron Fluence

Units

rad(Si)

Upsets/Bit-Day

rad(Si)/s

Immune

(4)

rad(Si)/s

Upsets/Bit-Day

N/cm

Maximum

1E - 10

1E - 11

Symbol

RTD

SEU2

RPRU

SEL

SEU1

RNF

Minimum

1E + 06

1E + 09

1E + 12

1E + 14

20 - 50 ns Pulse Width
T

case

= 25°C and 125°C

MIL-STD-883, TM 1019.5
Condition A

20 - 50 ns Pulse Width
T

case

= 125°C

-55°C

case

80°C

-55°C

case

125°C

-55°C

case

125°C

*Input rise and fall times <5 ns

Tester AC Timing Characteristics

Radiation Hardness Assurance

Reliability

BAE SYSTEMS' reliability starts with an overall product
assurance system that utilizes a quality system involving all
employees including operators, process engineers and
product assurance personnel. An extensive wafer lot
acceptance methodology, using in-line electrical data as well
as physical data, assures product quality prior to assembly. A
continuous reliability monitoring program evaluates every lot
at the wafer level, utilizing test structures as well as product
testing. Test structures are placed on every wafer, allowing
correlation and checks within-wafer, wafer-to-wafer, and from
lot-to-lot.

Reliability attributes of the CMOS process are characterized
by testing both irradiated and non-irradiated test structures.
The evaluations allow design model and process changes to
be incorporated for specific failure mechanisms, i.e., hot
carriers, electromigration, and time dependent dielectric
breakdown. These enhancements to the operation create a
more reliable product.

The process reliability is further enhanced by accelerated
dynamic life tests of both irradiated and non-irradiated test
structures. Screening and testing procedures from the
customer are followed to qualify the product.

A final periodic verification of the quality and reliability of the
product is validated by a TCI (Technology Conformance
Inspection).

BAE SYSTEMS has two QML screen levels (Q and V) to meet
full compliant space applications. For limited performance and
evaluation situations, BAE SYSTEMS offers an engineering
screen level.

Screening Levels

BAE SYSTEMS provides a superior quality level of radiation
hardness assurance for our products. The excellent product
quality is sustained via the use of our qualified QML operation
which requires process control with statistical process control,
radiation hardness assurance procedures and a rigid
computer controlled manufacturing operation monitoring and
tracking system.

The BAE SYSTEMS technology is built with resistance to
radiation effects. Our product is designed to exhibit < 1e

-11

fails/bit-day in a 90% worst case geosynchronous orbit under
worst case operating conditions. Total dose hardness is
assured by irradiating test structures on every lot and total
dose exposure with Cobalt 60 testing performed quarterly on
TCI lots to assure the product is meeting the QML radiation
hardness requirements.

TTL I/O Configuration

CMOS I/O Configuration

3 V

- 0.4 V

3.4 V

0.4 V

2.4 V

1.5 V

High Z

High Z = 2.9 V

0 V

1.5 V

. . . . . . . . . . . . . . .

. . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . .

. . . . .

. . . . . . . .

. . . .

0.5 V

Input

Levels*

Output

Sense

Levels

3.4 V

0.4 V

2.4 V

High Z

High Z = 2.9 V

- 0.4 V

- 0.5 V

Pin Listing

Standard Screening Procedure

Stress Methodology

There are two methods of burn-in defined. For "Static" burn-in,
all possible addresses are written with a logic "1" for half of the
burn-in duration and a logic "0" for the remaining half. For
"Dynamic" burn-in, all possible addresses are written with
alternating high and low data.

All I/O pins specified in the static and dynamic burn-in pin lists
are driven through individual series resistors (1.6K

±10%).

The burn-in circuit diagram is shown at right.

Voltage Levels
· Vin(0): 0.0 V to + 0.4 V

= Low level for all programmed signals

·Vin(1): + 5.4 V to + 6.0 V

= High level for all programmed signals

· V1: + 5.5 V (-0% / +10%)

All V

pins are tied to this level

·Vsx: Float or GND

All GND pins are tied to this level

C1 = 0.1 µF (±10%)
R = 1.6K

(±10%)

DQ0

DIN

DQ7

A16

256K x 8

SRAM

The dynamic
burn-in pin listing
is shown at right.
F = square wave,
100 KHz to
1.0 MHz.

Sample

Alternate Method Used

Die Traceability

MIL-STD-883, TM 2010

5.5 V, 125°C, 144 Hours

Meets Group A

< 5% Fallout

MIL-STD-883, TM 2009

Wafer Lot Acceptance

Serialization

Destructive Bond Pull

Internal Visual

Temperature Cycle

Constant Acceleration

PIND

Radiography

Electrical Test

Dynamic Burn-In

Electrical Test

Static Burn-In

Final Electrical

PDA

Fine and Gross Leak

External Visual

Comments

Flow

QML Level

Burn-In Circuit

Input

A12

A13

A14

A15

A16

Input

A4
A5

Signal

F/2

F/4

F/8

F/16

F/32
F/64

Signal

F/8192

F/16384

F/32768

F/65536

F/131072
F/262144

Input

A6
A7

A10
A11

Signal

F/128

F/256

F/512

F/1024

F/2048
F/4096

Input

Signal

F/524288

(0) First Half

(1) Second Half

(0) First Half

(1) Second Half

1) Part mark per device specification.
2) ``QML'' may not be required per device specification.
3) Dimensions are in inches.
4) Lead cross-section: .008"W x .006" Th, lead pitch: .025",

lead plating: 100 uin, au over 100 uin, ni over Kovar.

5) Unless otherwise specified, all tolerances are ± .005."

Notes:

Cleared for Public Domain Release

BAE SYSTEMS · 9300 Wellington Road · Manassas, Virginia 20110-4122

BAE SYSTEMS reserves the right to make changes to any
products herein to improve reliability, function or design. BAE
SYSTEMS does not assume liability arising out of the
application or use of any product or circuit described herein,
neither does it convey any license under its patent rights nor the
rights of others.

BAE SYSTEMS
An ISO 9001, AS9000, ISO 14001,
and SEI CMM Level 4 Company
9300 Wellington Road, Manassas, VA 20110-4122
866-530-8104
http://www.baesystems-iews.com/space/

0039_256K_8_SRAM.ppt

Packaging

40-Lead Dual Flat Pack Pinout

The 256K x 8 SRAM is offered in a custom 40-lead dual FP.
All packages are constructed of multilayer ceramic (AI

)

and feature internal power and ground planes.

Optional capacitors can be mounted to the package to
maximize supply noise decoupling and increase board
packing density. These capacitors attach directly to the
internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire and
package, both of which are critical in a transient radiation
environment. All NC pins must be connected to either V

GND or an active driver to prevent charge build up in the
radiation environment. (NC = no connect.)

A10

A15

DQ0

A14

DQ2

A11

GND

A16

A13

DQ1

A12

GND

Top

View

DQ3

DQ6

DQ4

GND

DQ7

DQ5

GND

A=1.635
B=.885 ± .008
C=.710 ± .008

H=.775
J=.048
K=.045

D=.245 ± .015
E=.135
F=.164
G=.030

Ordering Information

Screen

Designation

Package

Designation

1=40-Lead FP

1=QML VV
3=Engineering
4=QML VQ
5=QML QQ
7=Customer Specific

Speed

Designation

3 = 30 ns

4 = 40 ns;

45 ns for
Engineering
Screen

256K x 8 CMOS Memory Device MCM (5 V)
·Part Number 201A072

256K x 8 TTL Memory Device MCM (5 V)
·Part Number 225A837

A
B

(1), (2)

Lead 1

Lead 20

Lead 40

Lead 21

40-Lead Dual Flat Pack

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 201A072

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 201A072