128K x 8
Radiation Hardened
Static RAM 3.3 V
203A665
BAE SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Product Description
Radiation
Fabricated with Bulk CMOS 0.5 m Process
Total Dose Hardness through 1x10
6
rad(Si)
Neutron Hardness through 1x10
14
N/cm
2
Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
Soft Error Rate of < 1x10
-11
Upsets/Bit-Day
Dose Rate Survivability through 1x10
12
rad(Si)/s
Latchup Free
Features
Other
Read/Write Cycle Times
30 ns, 35 ns (-55 C to 125 C)
SMD Number 5962H98615
Asynchronous Operation
CMOS Compatible I/O
Single 3.3 V 5% Power Supply
Low Operating Power
Packaging Options
40-Lead Flat Pack - (0.775" x 0.650")
General Description
The 128K x 8 radiation hardened static RAM
is a high performance 131,072 word x 8-bit
static random access memory with industry-
standard functionality. It is fabricated with
BAE SYSTEMS' radiation hardened
technology and is designed for use in
systems operating in radiation
environments. The RAM operates over the
full military temperature range and requires
a single 3.3 V 5% power supply. The RAM
is available with CMOS compatible I/O.
Power consumption is typically less than 20
mW/MHz in operation, and less than 10 mW
in the low power disabled mode. The RAM
read operation is fully asynchronous, with an
associated typical access time of 30
nanoseconds.
BAE SYSTEMS' enhanced bulk CMOS
technology is radiation hardened through
the use of advanced and proprietary design,
layout, and process hardening techniques.
2
Functional Diagram
Signal Definitions
A: 0-16
DQ: 0-7
S
Address input pins that select a particular
eight-bit word within the memory array.
Bi-directional data pins that serve as data
outputs during a read operation and as data
inputs during a write operation.
Negative chip select, when at a low level,
allows normal read or write operation. When at
a high level, S forces the SRAM to a
precharge condition, holds the data output
drivers in a high impedance state and disables
the data input buffers only. If this signal is not
used, it must be connected to GND.
Negative write enable, when at a low level, activates a
write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.
Negative output enable, when at a high level holds the
data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S,
W, and E. If this signal is not used it must be connected
to GND.
Chip enable, when at a high level allows normal
operation. When at a low level, E forces the SRAM to a
precharge condition, holds the data output drivers in a
high impedance state and disables all the input buffers
except the S input buffer. If this signal is not used, it
must be connected to V
DD
.
W
G
E
Notes:
1) V
IN
for don't care (X) inputs = V
IL
or V
IH
.
2) When G = high, I/O is high-Z.
3) To dissipate the minimum amount of
standby power when in standby mode:
S= V
DD
and E = GND. All other input
levels may float.
Truth Table
A0
A1 - A2
A3
A9 - A16
W
G
S
E
DQ0-DQ7
A4-A8
Top/Bottom Decoder
Block Address Decoder
L/R Side/Block
Row Address Decoder
((256 x 32) x 2 x 4) x 8 x 2
Memory Cell Array
8 Bit Word Input/Output
Column Address Decoder
Mode
Inputs
(1),(2)
E
High
High
X
Low
S
Low
Low
High
X
W
Low
High
X
X
G
X
Low
X
X
I/O
Data-In
Data-Out
High-Z
High-Z
Power
Active
Active
Standby
Standby
Write
Read
Standby
Standby
(3)
3
Notes:
Note:
1)All voltages referenced to GND.
The substrate of this module is connected directly to Ground.
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
Power-Up Sequence: GND, V
DD
, Inputs
Power-Down Sequence: Inputs, V
DD
, GND
Absolute Maximum Ratings
Recommended Operating Conditions
Power Sequencing
Minimum
+3.14
0.0
-55
0.0
+2.2
Units
Volt
Volt
Celsius
Volt
Volt
Supply Voltage
Parameters
(1)
Supply Voltage Reference
Case Temperature
Input Logic "Low" - CMOS
Input Logic "High" - CMOS
Symbol
V
DD
GND
T
C
V
IL
V
IH
Maximum
+3.46
0.0
+125
+0.8
V
DD
Minimum
-65C
-55C
-0.5 V
-0.5 V
-0.5 V
(Class II)
Storage Temperature Range (Ambient)
Applied Conditions
(1)
Operating Temperature Range
Positive Supply Voltage
Input Voltage
(2)
Output Voltage
(2)
Power Dissipation
(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity
(4)
Maximum
+150C
+125C
+5.5 V
V
DD
+ 0.5 V
1.3 W
+250C
V
DD
+ 0.5 V
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +5.5 V.
3) Guaranteed by design; not tested.
4) Class as defined in MIL-STD-883, Method 3015.
4
1)Typical operating conditions:
-55 C
T
case
+125 C; 3.14 V
V
DD
3.46 V; unless otherwise specified.
167 10%
1.73 V
50 pF + 10%
Output Load Circuit
DC Electrical Characteristics
Note:
Symbol
Test Conditions
(1)
Device Type
Limits
Minimum
Maximum
Units
I
DD1
V
OH
F = F
MAX
= 1/t
AVAV(min)
S = V
IL
= GND
E = V
IH
= V
DD
No Output Load
S = V
IH
= V
DD
E = V
IL
= GND
F = 0 MHz
V
DD
= 2.5 V
V
DD
= V
DR
0 V
V
IN
5.5 V
By Design/
Verified By
Characterization
I
OH
= -200 A
I
OH
= -4 mA
I
OL
= 200 A
I
OL
= 8 mA
All
All
All
All
All
All
All
All
All
All
All
All
All
180
2.0
2.0
1.8
2.4
1.5
2.2
-5
-10
0.4
V
DD
- 0.1
0.05
0.8
5
10
7
10
mA
mA
mA
mA
V
V
V
A
A
pF
pF
V
V
Test
Supply Current
(Cycling Selected)
Supply Current
(Cycling De-Selected)
Supply Current
(Standby)
Data Retention Current
Data Retention Voltage
High Level Input Voltage
Low Level Input Voltage
Input Leakage
Output Leakage
C
in
C
out
High Level Output Voltage
Low Level Output Voltage
I
DD2
I
DD3
I
DR
V
OL
V
DR
V
IH
V
IL
I
ILK
I
OLK
F = F
MAX
= 1/t
AVAV(min)
S = V
IH
= V
DD
E = V
IL
= GND
0 V
V
OUT
5.5 V
By Design/
Verified By
Characterization
Note:
1)Test conditions: input switching levels 0V to V
DD
, input rise and fall times < 2.0 ns/Volt, input and output
timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C
L
=
50 pF. For C
L
> 50 pF, derate access times by 0.02 ns/pF (typical). -55 C
T
case
+125C; 3.14 V
V
DD
3.46 V; unless otherwise specified.
5
Read Cycle AC Timing Characteristics
(1)
Worst Case By Speed
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Read Cycle Time
Output Hold After Address Change
Chip Select to Output Active
Chip Enable to Output Active
Output Enable to Output Active
Address Access Time
Chip Select Access Time
Chip Enable Access Time
Chip Select to Output Disable
Chip Disable to Output Disable
Output Enable to Output Disable
Output Enable Access Time
Minimum or
Maximum
Minimum
Minimum
Minimum
Minimum
Minimum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
-x3x
30
0
0
0
30
30
30
10
12
0
-x4x
35
0
0
0
0
35
35
35
10
10
10
15
Symbol
t
AVAV
t
AVQV
t
AXQX
t
SLQV
t
SLQX
t
SHQZ
t
EHQV
t
EHQX
t
ELQZ
t
GLQV
t
GLQX
t
GHQZ
Read Cycle Timing Diagram
Valid Address
Valid Data
High Impedance
Address
E
S
G
Data
Out
t
AVAV
t
AVQV
t
SLQV
t
SLQX
t
EHQV
t
EHQX
t
GLQV
t
GLQX
t
AXQX
t
SHQZ
t
ELQZ
t
SHQZ
10
10
PDF 
ZIP