128K x 16
Radiation Hardened
Static RAM MCM 3.3 V
209A542
BAE SYSTEMS 9300 Wellington Road Manassas, Virginia 20110-4122
Product Description
Radiation
Fabricated with Bulk CMOS 0.5 m Process
Total Dose Hardness through 1x10
6
rad(Si)
Neutron Hardness through 1x10
14
N/cm
2
Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
Soft Error Rate of < 1x10
-11
Upsets/Bit-Day
Latchup Free
Features
Other
Read/Write Cycle Times
30 ns (-55 C to 125C)
SMD Number Pending
Asynchronous Operation
CMOS or TTL Compatible I/O
Single 3.3 V 5% Power Supply
Low Operating Power
Packaging Options
40-Lead Dual Flat Pack (0.855" x 0.710")
General Description
The 128K x 16 radiation hardened static
RAM is composed of two 128K x 8 SRAM
memory die assembled in a double-sided
ceramic substrate. Each die is a high
performance 131,072 word x 8-bit static
random access memory with industry-
standard functionality. It is fabricated with
BAE SYSTEMS' radiation hardened
technology and is designed for use in
systems operating in radiation
environments. The RAM operates over the
full military temperature range and requires
a single 3.3 V 5% power supply. The RAM
is available with CMOS compatible I/O.
Power consumption is typically less than 40
mW/MHz in operation, and less than 20 mW
in the low power disabled mode. The RAM
read operation is fully asynchronous, with an
associated typical access time of 19
nanoseconds.
BAE SYSTEMS' enhanced bulk CMOS
technology is radiation hardened through
the use of advanced and proprietary design,
layout, and process hardening techniques.
2
Functional Diagram
Signal Definitions
A: 0-16
DQ: 0-15
S1
Address input pins that select a particular
16-bit word within the memory array.
Bi-directional data pins that serve as data
outputs during a read operation and as
data inputs during a write operation.
Negative chip select, when at a low level,
allows normal read or write operation.
When at a high level, S1 forces the SRAM
to a precharge condition, holds the data
output drivers in a high impedance state
and disables the data input buffers only. If
this signal is not used, it must be
connected to GND.
Negative write enable, when at a low level, activates a
write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.
Negative output enable, when at a high level holds the
data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S1
and W. If this signal is not used it must be connected to
GND.
W
G
Notes:
1) V
IN
for don't care (X) inputs = V
IL
or V
IH
.
2) When G = high, I/O is high-Z.
3) To dissipate the minimum amount of
standby power when in standby mode:
S1 = V
DD
. All other input levels may float.
Truth Table
Mode
Inputs
(1),(2)
S1
Low
Low
High
X
W
Low
High
X
X
G
X
Low
X
X
I/O
Data-In
Data-Out
High-Z
High-Z
Power
Active
Active
Standby
Standby
Write
Read
Standby
Standby
(3)
A0
A1 - A2
A3
A9 - A16
W
G
S1
DQ0-DQ15
A4-A8
Top/Bottom Decoder
Block Address Decoder
L/R Side/Block
Row Address Decoder
(((256 x 32) x 2 x 4) x 8 x 2) x 2
Memory Cell Array
16 Bit Word Input/Output
Column Address Decoder
3
Notes:
Note:
1)All voltages referenced to GND.
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
Power-Up Sequence: GND, V
DD
, Inputs
Power-Down Sequence: Inputs, V
DD
, GND
Absolute Maximum Ratings
Recommended Operating Conditions
Power Sequencing
Minimum
+3.14
0.0
-55
-0.3
+2.0
Units
Volt
Volt
Celsius
Volt
Volt
Supply Voltage
Parameters
(1)
Supply Voltage Reference
Case Temperature
Input Logic "Low"
Input Logic "High"
Symbol
V
DD
GND
T
C
V
IL
V
IH
Maximum
+3.46
0.0
+125
+0.8
V
DD
Minimum
-65C
-55C
-0.5 V
-0.5 V
-0.5 V
(Class II)
Storage Temperature Range (Ambient)
Applied Conditions
(1)
Operating Temperature Range T
CASE
Positive Supply Voltage
Input Voltage
(2)
Output Voltage
(2)
Power Dissipation
(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity
(4)
Maximum
+150C
+125C
+5.5 V
V
DD
+ 0.5 V
1.25 W
+230C
V
DD
+ 0.5 V
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +5.5 V.
3) Guaranteed by design; not tested.
4) Class as defined in MIL-STD-883, Method 3015.
4
1) Typical operating conditions:
-55C
T
case
+125C; 3.14 V
V
DD
3.46 V; unless otherwise specified.
2) Guaranteed by design and verified by periodic characterization.
300 10%
2.8V
50 pF + 10%
Output Load Circuit
DC Electrical Characteristics
Note:
Symbol
Test Conditions
(1)
Device Type
Limits
Minimum
Maximum
Units
I
DD1
V
OH
F = F
MAX
= 1/t
AVAV(min)
S1 = GND
No Output Load
V
DD
= 2.5 V
0 V
V
IN
5.5 V
By Design/
Verified By
Characterization
I
OH
= -200 A
I
OH
= -4 mA
I
OL
= 200 A
I
OL
= 8 mA
All
All
All
All
All
All
All
All
All
All
All
All
360
6.0
6.0
4.0
4.0
2.0
-20
-20
0.4
V
DD
- 0.5 V
0.05
0.8
20
20
6
9
mA
mA
mA
mA
V
V
A
A
pF
pF
V
V
Test
Supply Current
(Cycling Selected)
Supply Current
(Cycling De-Selected)
Supply Current
(Standby)
Data Retention Current
High Level Input Voltage
Low Level Input Voltage
Input Leakage
Output Leakage
C
in
C
out
High Level Output Voltage
Low Level Output Voltage
I
DD2
I
DD3
I
DR
V
OL
V
IH
V
IL
I
ILK
I
OLK
S1 = V
DD
F = F
MAX
= 1/t
AVAV(min)
F = 0 MHz
S1 = V
DD
0 V
V
OUT
5.5 V
By Design/
Verified By
Characterization
(2)
(2)
Notes:
1)Test conditions: input switching levels V
IL
/V
IH
= 0.5 V/V
DD
-0.5 V (CMOS), input rise and fall times < 5 ns,
input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output
loading C
L
= 50 pF. For C
L
> 50 pF, derate access times by 0.02 ns/pF (typical). -55C
T
case
+125C;
3.14 V
V
DD
3.46 V; unless otherwise specified.
2) Cycle time per individual die.
5
Read Cycle AC Timing Characteristics
(1)
Read Cycle Timing Diagram
Valid Address
Valid Data
High Impedance
Address
S1
G
Data
Out
t
AVAV
t
AVQV
t
SLQV
t
SLQX
t
GLQV
t
GLQX
t
AXQX
t
SHQZ
t
GHQZ
Limits
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Read Cycle Time
Chip Select to Output Active
Output Enable to Output Active
Address Access Time
Chip Select Access Time
Output Hold After Address Change
Chip Select to Output Disable
Output Enable to Output Disable
Output Enable Access Time
Minimum or
Maximum
Minimum
Minimum
Minimum
Maximum
Maximum
Minimum
Maximum
Maximum
Maximum
30
0
0
30
30
0
15
15
15
Symbol
t
AVAV
(2)
t
AVQV
t
SLQV
t
SLQX
t
SHQZ
t
AXQX
t
GLQV
t
GLQX
t
GHQZ
Device Type
All
All
All
All
All
All
All
All
All
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