1
5504 DCR
Direct Conversion Receiver
DESCRIPTION
The 5504 is a low cost, high performance direct
conversion receiver (DCR) specifically designed for
digital wireless applications. The DCR architecture
provides a receiver design with fewer external
components than the conventional dual conversion
approach. The 5504 is designed to operate over an
input frequency range of 950 to 2150 MHz. The
device accepts an input signal in this frequency
range and down converts directly to baseband. The
local oscillator signal is generated by a completely
integrated phase lock loop that is fully
programmable through a standard serial port
interface.
April 2000
FEATURES
Wideband I/Q demodulator
RF input 950 to 2150 MHz
External lowpass filter
- Integrated post-filter baseband drivers
Integrated VCO and frequency synthesizer
AGC Amplifier
APPLICATIONS
Digital Satellite
VSAT Receivers
BLOCK DIAGRAM
Advanced Information
XTLP
FILN
EON
Charge
Pump
VCO
Div
32/33
Phase
Detect
Divide
10-bit
Xtal
Osc.
XTLN
Rext
Divide
11-bit
Modulo
6-bit
AGC
RFp
QO2
IO2
0
90
Serial
Port
R3 R2 R1
C1
C0
R0
2
5
2
0
VCO1
2
16
2
6
VCO0
Din
Dclk
V
N
D
1
V
N
A
6
a
V
N
A
5
V
N
A
6
b
V
N
A
4
V
P
A
3
a
V
P
A
3
b
V
P
A
4
V
P
A
5
a
V
P
A
1
V
N
A
3
b
V
N
A
3
a
Power
Splitter
I
O
1
Q
O
1
Q
i
n
I
i
n
RFn
V
P
A
5
b
V
P
A
6
V
P
D
1
V
P
D
2
T
P
1
T
P
2
RSHP
RSHN
RSLP
RSLN
V
N
A
1
V
N
S
.............
.............
5504 DCR
Direct Conversion Receiver
2
FUNCTIONAL DESCRIPTION
AGC Amplifier
The 5504 RF input can be driven differentially or
single ended. The RFp and RFn inputs are self-
biasing and are designed to be driven from a 50
Ohm source. For single-ended operation, the RFn
pin should be AC coupled to analog ground. A gain
control input, AGC, provides a 25 dB gain variation
with 0V providing minimum gain and 4V providing
maximum gain.
I/Q Mixer
The AGC amplifier drives the RF port of two identical
double balanced mixers. The LO ports of these
mixers are driven from an on-chip quadrature
network.
Low Pass Filtering and Buffering
Following each mixer, a buffer amplifier is provided
for driving an external passive low-pass filter. The
nominal output impedance for IO1 and Q01 is 50
ohms. A second high impedance buffer amplifier is
provided (IIN or QIN) for additional gain and isolation
after the filter. The figure below shows a typical filter
designed for 20 Megasymbol per second operation:
Dual VCO
The 5504 uses two VCOs to cover the entire
specified tuning range. Both VCOs use nearly
identical architecture with the only difference being
slight design modifications to optimize the range of
operation. The lower range VCO requires an
external resonator that supports a tuning range of
950 to 1473 MHz. The higher range VCO requires a
similar resonator with inductor values designed to
support the range of 1390 to 2150 MHz. A typical
lumped-element resonator circuit incorporating
varactor tuning is shown in the following figure:
Note: A separate resonator circuit is required for
each oscillator
PLL Synthesizer
The synthesizer derives its reference from a source
which can be either an externally derived clock or an
external crystal coupled to the internal oscillator.
This source drives a programmable reference divider
with 15 preset divide ratios from 2 to 320. This
divider output provides the PLL reference by driving
one input of a phase/frequency detector. The VCO
output drives a divider chain incorporating a variable
modulus prescaler and divider. The divider is
programmed by a 17-bit control word. This divider
chain output drives the other input of the
phase/frequency detector.
Loop Filter
The phase/frequency detector interface consists of
two ports, FILN and EON. The EON drives the base
of an external NPN transistor, and the FILN provides
a feedback path for the loop filter elements. The
external transistor permits VCO tune voltages of
greater than 30V and also provides the final stage of
the loop amplifier. Below is shown a typical loop
filter:
IIN/QIN
IO1/QO1
0.1 F
68pF
68pF
12pF
680nH
470nH
Vtune
10 k
47
47
10 k
BB835
12pF
12pF
L1
L2
L2
+5
29
28
32
33
High
Low
5503
C1
L1
1000pF
Q1
Vtune
+28V
10 kW
10 k
EON
FILN
0.1 F
5504 DCR
Direct Conversion Receiver
3
DCR Application Drawing
XTAL
OSC
AGC
AMP
QUAD
GEN
PLL SYNTH.
SHIFT REGISTER/
RAM
DUAL VCO
LOW
RESONATOR
HIGH
RESONATOR
PLL
LOOP
FILTER
LOW PASS
FILTER
LOW PASS
FILTER
RFP 7
RFN 6
XTALP 46
XTALN
45
47
DIN
DCLK
48
RSLN
35
RSLP
32
RSHN
RSHP
29 26
FILN
37
EON
39
17 IO2
22 QO2
IIN
18
QIN
23
QO1
21
IO1
14
ADC
ADC
DEMOD/FEC
VND1
VNA1
VNA3a
1
19
VNA3b
25
36
VPA1
VPA3a
11
+5V
15
30 31
42
4
5
VPD1
VPD2
3
2
TP1C TP2C
43 44
VNA4
41
VNA5b
9
VNA5a
8
VNS
12
Rxt
24
7.68k
PIN
ATTEN.
LNA
VPA3b AGC VPA4 VPA5a VPA5b
5504 DCR
Direct Conversion Receiver
4
PIN DESCRIPTIONS
ANALOG PINS
NAME TYPE
DESCRIPTION
RFP, RFN
I
RF inputs: balanced differential inputs to the receiver. The input signals placed on this
line are amplified with a variable gain amplifier before being passed to the I/Q
demodulator.
AGC
I
Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input
amplifier gain from minimum to maximum. The gain increase is 25 dB typical
Eon, Filn
I/O
External loop filter interface. Eon drives the base of an external common emitter
transistor. Filn is the feedback input from the loop filter capacitor.
XTLP, XTLN
I
Reference crystal input. An external crystal connected between these pins
establishes the reference frequency for the PLL synthesizer. Following this oscillator is
a programmable divider that establishes the synthesizer step size.
IO2,
QO2
O
Baseband outputs. These typically drive an A/D converter prior to digital
demodulation and processing.
IO1, QO1
O
I and Q channel outputs to external low pass filter. An external series resistor can be
connected between this output and the filter to provide the source match.
IIN, QIN
I
I and Q channel inputs from external low pass filter. These are high impedance inputs
(>5000
). The low pass filter must be designed for low input and high output
impedance.
Rxt
I
External reference resistor. This resistor is connected to ground and must be 7.68k
1%. It is used as a reference for internal bias currents.
RSHP, RSHN
I
High range VCO resonator inputs
RSLP, RSLN
I
Low range VCO resonator inputs
DIGITAL PINS
Din
I/O
I2C data. This signal is connected to the I2C internal block. An external resistor
(typically 2.2 k
) is connected between Din and Vcc for proper operation
Dclk I
I2C clock Input. Dclk should nominally be a square wave with a maximum frequency
of 400kHz. SCL is generated by the system I2C master.
5504 DCR
Direct Conversion Receiver
5
POWER PINS
VPA1, VPA3a,
VPA3b, VPA4,
VPA5a,
VPA5b, VPA6
I
Analog Vcc pins
VPD1, VPD2
I
Digital Vcc pin.
VNA1, VNA3a,
VNA3b, VNA4,
VNA6, VNA7
I
Analog ground pins.
VND1
I
Digital ground pin.
VNS
I
Substrate ground pin.
MICROCONTROLLER SERIAL INTERFACE
I
2
C REGISTERS: WRITE MODE
S address 0 A reg0 A reg1 A reg2 A reg3
5504 address
1 1 0 0 0 0 1
S: start bit
A: acknowledge bit
P: stop bit
TABLE 1: MICROCONTROLLER INTERFACE REGISTER
REGISTER 7(MSB)
6
5
4
3
2
1
0 (LSB)
0
0
2
14
2
13
2
12
2
11
2
10
2
9
2
8
1
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
1
2
16
2
15
x
R3
R2
R1
R0
3
C1
C0
test1
test0
Pdisab
vco1 vco0
x
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