Электронный компонент: 56F8157

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56F8300
16-bit Hybrid Controllers

freescale.com

56F8357/56F8157

Data Sheet
Preliminary Technical Data

MC56F8357
Rev. 8.0
10/2004

56F8357 Technical Data, Rev. 8.0

2

Freescale Semiconductor

Preliminary

Document Revision History

Version History

Description of Change

Rev 1.0

Initial Public Release

Rev 2.0

Added Package Pins to GPIO Table in

Part 8 General Purpose Input/Output (GPIO)

. Added

"Typical Min" values to

Table 10-17

. Editing grammar, spelling, consistency of language throughout

family. Updated values in Regulator Parameters

Table 10-9

; External Clock Operation Timing

Requirements

Table 10-13

; SPI Timing

Table 10-18

; ADC Parameters

Table 10-24

; and IO Loading

Coefficients at 10MHz

Table 10-25

.

Rev 3.0

Corrected

Table 4-6

Data Memory Map - changed address X:$FF0000 to X:$FFFF00

Rev 4.0

Added

Part 4.8

, added the word "access" to FM Error Interrupt in

Table 4-5

, documenting only Typ.

numbers for LVI in

Table 10-6

, updated EMI numbers and write-up in

Part 10.8

.

Rev 5.0

Updated numbers in

Table 10-7

and

Table 10-8

with more recent data. Corrected typo in

Table 10-3

in Pd characteristics.

Rev 6.0

Replace any reference to Flash Interface Unit with Flash Module; removed references to JTAG pin
DE; corrected pin number for D14 in

Table 2-2

; added note to V

CAP

pin in

Table 2-2

; corrected

thermal numbers for 160 LQFP in

Table 10-3

; removed unneccessary notes in

Table 10-12

; corrected

temperature range in

Table 10-14

; added ADC calibration information to

Table 10-24

and new graphs

in

Figure 10-22

.

Rev 7.0

Adding/clarifing notes to

Table 4-4

to help clarify independent program flash blocks and other

Program Flash modes, clarification in

Table 10-23

, corrected Digital Input Current Low (pull-up

enabled) numbers in

Table 10-5

. Removed text and Table 10-2; replaced with note to

Table 10-1

.

Rev 8.0

Added 56F8157 information; edited to indicate differences in 56F8357 and 56F8157. Reformatted for
Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of elec-
trical tables for consistency throughout the family. Clarified I/O power description in

Table 2-2

, added

note to

Table 10-7

and clarified

Section 12.3

.

Please see http://www.freescale.com for the most current Data Sheet revision.

56F8357 Technical Data, Rev. 8.0

Freescale Semiconductor

3

Preliminary

56F8357/56F8157 Block Diagram

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

PLL

Clock

Generator

EXTAL

Interrupt

Controller

4

External

Address Bus

Switch

E

x

te

r
n

al Bu

s

In

ter

f
ac

e U

n

it

2

External Data

Bus Switch

PDB
CDBR

SPI0 or

GPIOE

IPBus Bridge (IPBB)

System
Integration
Module

P
O
R

O
S
C

Decoding

Peripherals

Peripheral

Device Selects

RW
Control

IPAB

IPWDB

IPRDB

2

System Bus

R/W Control

PAB

CDBW

Clock
resets

JTAG/

EOnCE

Port

V

CAP

V

DD

V

SS

V

DDA

V

SSA

5

4

7

6

2

V

PP

2

OCR_DIS

RESET

EXTBOOT

EMI_MODE

RSTO

4

4

6

PWM Outputs

Fault Inputs

PWMA

Current Sense Inputs or GPIOC

3

4

6

PWM Outputs

Fault Inputs

PWMB

Current Sense Inputs or GPIOD

3

Quad

Timer D or

GPIOE

Quad

Timer C or

GPIOE

AD0

AD1

ADCA

4

5

FlexCAN

2

4

AD0

AD1

4

4

4

Quadrature

Decoder 1 or

Quad

Timer B or

SPI1 or GPIOC

4

Bus Control

6

2

8

7

9

XTAL

DS (CS1) or GPIOD9

PS (CS0) or GPIOD8

RD

WR

D7-15 or GPIOF0-8

D0-6 or GPIOF9-15

A8-15 or GPIOA0-7

A0-5 or GPIOA8-13

A6-7 or GPIOE2-3

VREF

ADCB

16-Bit

56800E Core

2

COP/

Watchdog

CLKO

CLKMODE

IRQB

SCI1 or

GPIOD

SCI0 or

GPIOE

Control

IRQA

6

GPIOD0-5 or CS2-7

4

GPIOB0-3 (A16-19)

1

GPIOB4 (A20,
prescaler_clock)

3

GPIOB5-7 (A21-23,
clk0-3**)

XDB2

XAB1

XAB2

PAB

PDB

CDBR

CDBW

Digital Reg

Analog Reg

Low Voltage

Supervisor

**See Table 2-2

for explanation

Data Memory

4K x 16 Flash

8K x 16 RAM

Memory

Program Memory

128K x 16 Flash

2K x 16 RAM

TEMP_SENSE

Quadrature

Decoder 0 or

Quad

Timer or /

GPIOC

* Configuration

shown for on-chip

2.5V regulator

8K x 16

Boot Flash

56F8357/56F8157 General Description

Note: Features in italics are NOT available in the 56F8157 device.

� Up to 60 MIPS at 60MHz core frequency

� DSP and MCU functionality in a unified,

C-efficient architecture

� Access up to 4MB of off-chip program and 32MB of

data memory

� Chip Select Logic for glueless interface to ROM and

SRAM

� 256KB of Program Flash

� 4KB of Program RAM

� 8KB of Data Flash

� 16KB of Data RAM

� 16KB Boot Flash

� Up to two 6-channel PWM modules

� Four 4-channel, 12-bit ADCs

� Temperature Sensor

� Up to two Quadrature Decoders

� Optional on-chip regulator

� FlexCAN module

� Two Serial Communication Interfaces (SCIs)

� Up to two Serial Peripheral Interfaces (SPIs)

� Up to four general-purpose Quad Timers

� Computer Operating Properly (COP) / Watchdog

� JTAG/Enhanced On-Chip Emulation (OnCETM) for

unobtrusive, real-time debugging

� Up to 76 GPIO lines

� 160-pin LQFP Package

56F8357 Technical Data, Rev. 8.0

4

Freescale Semiconductor

Preliminary

Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5

1.1. 56F8357/56F8157 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14

Part 2: Signal/Connection Descriptions . . . 15

2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18

Part 3: On-Chip Clock Synthesis (OCCS) . . 38

3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 40

4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 46
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 48
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory . . . . . . . . . . 75

Part 5: Interrupt Controller (ITCN) . . . . . . . . 76

5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3. Functional Description . . . . . . . . . . . . . . . . 76
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 78
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 78
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 79
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Part 6: System Integration Module (SIM) . 106

6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 107
6.4. Operation Mode Register . . . . . . . . . . . . . 108
6.5. Register Descriptions . . . . . . . . . . . . . . . . 108
6.6. Clock Generation Overview . . . . . . . . . . . 121
6.7. Power Down Modes Overview . . . . . . . . . 122
6.8. Stop and Wait Mode Disable Function . . . 122
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Part 7: Security Features . . . . . . . . . . . . . . 123

7.1. Operation with Security Enabled . . . . . . . 123
7.2. Flash Access Blocking Mechanisms . . . . 124

Part 8: General Purpose Input/Output

(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 126

8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 126
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 127
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 127

Part 9: Joint Test Action Group (JTAG) . 132

9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 132

Part 10: Specifications . . . . . . . . . . . . . . . 132

10.1. General Characteristics . . . . . . . . . . . . . . 132
10.2. DC Electrical Characteristics . . . . . . . . . . 136
10.3. AC Electrical Characteristics . . . . . . . . . . 140
10.4. Flash Memory Characteristics . . . . . . . . . 140
10.5. External Clock Operation Timing . . . . . . . 141
10.6. Phase Locked Loop Timing . . . . . . . . . . . 141
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 142
10.8. External Memory Interface Timing . . . . . . 142
10.9. Reset, Stop, Wait, Mode Select, and

Interrupt Timing . . . . . . . . . . . . . . 145

10.10. Serial Peripheral Interface (SPI) Timing . 147
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 151
10.12. Quadrature Decoder Timing . . . . . . . . . . 151
10.13. Serial Communication Interface (SCI)

Timing . . . . . . . . . . . . . . . . . . . . . 152

10.14. Controller Area Network (CAN) Timing . 153
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 153
10.16. Analog-to-Digital Converter (ADC)

Parameters . . . . . . . . . . . . . . . . . 155

10.17. Equivalent Circuit for ADC Inputs . . . . . . 158
10.18. Power Consumption . . . . . . . . . . . . . . . . 158

Part 11: Packaging . . . . . . . . . . . . . . . . . . 160

11.1. 56F8357 Package and Pin-Out

Information . . . . . . . . . . . . . . . . . . 160

11.2. 56F8157 Package and Pin-Out

Information . . . . . . . . . . . . . . . . . . 163

Part 12: Design Considerations . . . . . . . . 167

12.1. Thermal Design Considerations . . . . . . . . 167
12.2. Electrical Design Considerations . . . . . . . 168
12.3. Power Distribution and I/O Ring

Implementation . . . . . . . . . . . . . . 169

Part 13: Ordering Information . . . . . . . . . 170

Table of Contents

56F8357/56F8157 Features

56F8357 Technical Data, Rev. 8.0

Freescale Semiconductor

5

Preliminary

Part 1 Overview

1.1 56F8357/56F8157 Features

1.1.1

Hybrid Controller Core

�

Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture

�

Up to 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency

�

Single-cycle 16

�

16-bit parallel Multiplier-Accumulator (MAC)

�

Four 36-bit accumulators, including extension bits

�

Arithmetic and logic multi-bit shifter

�

Parallel instruction set with unique DSP addressing modes

�

Hardware DO and REP loops

�

Three internal address buses

�

Four internal data buses

�

Instruction set supports both DSP and controller functions

�

Controller-style addressing modes and instructions for compact code

�

Efficient C compiler and local variable support

�

Software subroutine and interrupt stack with depth limited only by memory

�

JTAG/EOnCE debug programming interface

1.1.2

Differences Between Devices

Table 1-1

outlines the key differences between the 56F8357 and 56F8157 devices.

Table 1-1 Device Differences

Feature

56F8357

56F8157

Guaranteed Speed

60MHz/60 MIPS

40MHz/40 MIPS

Program RAM

4KB

Not Available

Data Flash

8KB

Not Available

PWM

2 x 6

1 x 6

CAN

1

Not Available

Quad Timer

4

2

Quadrature Decoder

2 x 4

1 x 4

Temperature Sensor

1

Not Available

Dedicated GPIO

--

7

Document Outline

• Part 1 Overview
  • 1.1 56F8357/56F8157 Features
    • 1.1.1 Hybrid Controller Core
    • 1.1.2 Differences Between Devices
    • 1.1.3 Memory
    • 1.1.4 Peripheral Circuits
    • 1.1.5 Energy Information
  • 1.2 Device Description
    • 1.2.1 56F8357 Features
    • 1.2.2 56F8157 Features
  • 1.3 Award-Winning Development Environment
  • 1.4 Architecture Block Diagram
  • 1.5 Product Documentation
  • 1.6 Data Sheet Conventions
• Part 2 Signal/Connection Descriptions
  • 2.1 Introduction
  • 2.2 Signal Pins
• Part 3 On-Chip Clock Synthesis (OCCS)
  • 3.1 Introduction
  • 3.2 External Clock Operation
    • 3.2.1 Crystal Oscillator
    • 3.2.2 Ceramic Resonator (Default)
    • 3.2.3 External Clock Source
  • 3.3 Registers
• Part 4 Memory Map
  • 4.1 Introduction
  • 4.2 Program Map
  • 4.3 Interrupt Vector Table
  • 4.4 Data Map
  • 4.5 Flash Memory Map
  • 4.6 EOnCE Memory Map
  • 4.7 Peripheral Memory Mapped Registers
  • 4.8 Factory Programmed Memory
• Part 5 Interrupt Controller (ITCN)
  • 5.1 Introduction
  • 5.2 Features
  • 5.3 Functional Description
    • 5.3.1 Normal Interrupt Handling
    • 5.3.2 Interrupt Nesting
    • 5.3.3 Fast Interrupt Handling
  • 5.4 Block Diagram
  • 5.5 Operating Modes
  • 5.6 Register Descriptions
    • 5.6.1 Interrupt Priority Register 0 (IPR0)
      • 5.6.1.1 Reserved�Bits 15�14
      • 5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)� Bits13�12
      • 5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)� Bits 11�10
      • 5.6.1.4 Reserved�Bits 9�0
    • 5.6.2 Interrupt Priority Register 1 (IPR1)
      • 5.6.2.1 Reserved�Bits 15�6
      • 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)�Bits 5�4
      • 5.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)�Bits 3�2
      • 5.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)� Bits 1�0
    • 5.6.3 Interrupt Priority Register 2 (IPR2)
      • 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)�Bi...
      • 5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)�Bits 13�12
      • 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)�Bits 11�10
      • 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)�Bits 9�8
      • 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)�Bits 7�6
      • 5.6.3.6 Reserved�Bits 5�4
      • 5.6.3.7 External IRQ B Interrupt Priority Level (IRQB IPL)�Bits 3�2
      • 5.6.3.8 External IRQ A Interrupt Priority Level (IRQA IPL)�Bits 1�0
    • 5.6.4 Interrupt Priority Register 3 (IPR3)
      • 5.6.4.1 GPIOD Interrupt Priority Level (GPIOD IPL)�Bits 15�14
      • 5.6.4.2 GPIOE Interrupt Priority Level (GPIOE IPL)�Bits 13�12
      • 5.6.4.3 GPIOF Interrupt Priority Level (GPIOF IPL)�Bits 11�10
      • 5.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)�Bits 9�8
      • 5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)� Bits 7�6
      • 5.6.4.6 FlexCAN Error Interrupt Priority Level (FCERR IPL)� Bits 5�4
      • 5.6.4.7 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)� Bits 3�2
      • 5.6.4.8 Reserved�Bits 1�0
    • 5.6.5 Interrupt Priority Register 4 (IPR4)
      • 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)� Bits 15�14
      • 5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)� Bits 13�12
      • 5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)� Bits 11�10
      • 5.6.5.4 Reserved�Bits 9�6
      • 5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)�Bits 5�4
      • 5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)�Bits 3�2
      • 5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)�Bits 1�0
    • 5.6.6 Interrupt Priority Register 5 (IPR5)
      • 5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)�Bits 15�14
      • 5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (D...
      • 5.6.6.3 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)� Bits 11�10
      • 5.6.6.4 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)� Bits 9�8
      • 5.6.6.5 Reserved�Bits 7�6
      • 5.6.6.6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)� Bits 5�4
      • 5.6.6.7 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)� Bits 3�2
      • 5.6.6.8 SPI0 Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)� Bits 1�0
    • 5.6.7 Interrupt Priority Register 6 (IPR6)
      • 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)� Bits 15�14
      • 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)� Bits 13�12
      • 5.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)� Bits 11�10
      • 5.6.7.4 Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)� Bits 9�8
      • 5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)� Bits 7�6
      • 5.6.7.6 Reserved�Bits 5�4
      • 5.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)�Bits 3�2
      • 5.6.7.8 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (...
    • 5.6.8 Interrupt Priority Register 7 (IPR7)
      • 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)� Bits 15�14
      • 5.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)� Bits 13�12
      • 5.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)� Bits 11�10
      • 5.6.8.4 Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)�Bits 9�8
      • 5.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)�Bits 7�6
      • 5.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)�Bits 5�4
      • 5.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)�Bits 3�2
      • 5.6.8.8 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)�Bits 1�0
    • 5.6.9 Interrupt Priority Register 8 (IPR8)
      • 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)� Bits 15�14
      • 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)� Bits 13�12
      • 5.6.9.3 Reserved�Bits 11�10
      • 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)� Bits 9�8
      • 5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)� Bits 7�6
      • 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)�Bits 5�4
      • 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)�Bits 3�2
      • 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)�Bits 1�0
    • 5.6.10 Interrupt Priority Register 9 (IPR9)
      • 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)�Bits 15�14
      • 5.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)�Bits 13�12
      • 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)� Bits 11�10
      • 5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)�Bits 9�8
      • 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)�Bits 7�6
      • 5.6.10.6 ADC B Zero Crossing or Limit Error Interrupt Priority Level (ADCB_ZC IPL)�Bits 5�4
      • 5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)�Bits 3�2
      • 5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)�Bits 1�0
    • 5.6.11 Vector Base Address Register (VBA)
      • 5.6.11.1 Reserved�Bits 15�13
      • 5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)� Bits 12�0
    • 5.6.12 Fast Interrupt 0 Match Register (FIM0)
      • 5.6.12.1 Reserved�Bits 15�7
      • 5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)�Bits 6�0
    • 5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
      • 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)�Bits 15�0
    • 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
      • 5.6.14.1 Reserved�Bits 15�5
      • 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)�Bits 4�0
    • 5.6.15 Fast Interrupt 1 Match Register (FIM1)
      • 5.6.15.1 Reserved�Bits 15�7
      • 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)�Bits 6�0
    • 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
      • 5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)�Bits 15�0
    • 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)
      • 5.6.17.1 Reserved�Bits 15�5
      • 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)�Bits 4�0
    • 5.6.18 IRQ Pending 0 Register (IRQP0)
      • 5.6.18.1 IRQ Pending (PENDING)�Bits 16�2
      • 5.6.18.2 Reserved�Bit 0
    • 5.6.19 IRQ Pending 1 Register (IRQP1)
      • 5.6.19.1 IRQ Pending (PENDING)�Bits 32�17
    • 5.6.20 IRQ Pending 2 Register (IRQP2)
      • 5.6.20.1 IRQ Pending (PENDING)�Bits 48�33
    • 5.6.21 IRQ Pending 3 Register (IRQP3)
      • 5.6.21.1 IRQ Pending (PENDING)�Bits 64�49
    • 5.6.22 IRQ Pending 4 Register (IRQP4)
      • 5.6.22.1 IRQ Pending (PENDING)�Bits 80�65
    • 5.6.23 IRQ Pending 5 Register (IRQP5)
      • 5.6.23.1 Reserved�Bits 96�82
      • 5.6.23.2 IRQ Pending (PENDING)�Bit 81
    • 5.6.24 Reserved�Base + 17
    • 5.6.25 Reserved�Base + 18
    • 5.6.26 Reserved�Base + 19
    • 5.6.27 Reserved�Base + 1A
    • 5.6.28 Reserved�Base + 1B
    • 5.6.29 Reserved�Base + 1C
    • 5.6.30 ITCN Control Register (ICTL)
      • 5.6.30.1 Interrupt (INT)�Bit 15
      • 5.6.30.2 Interrupt Priority Level (IPIC)�Bits 14�13
      • 5.6.30.3 Vector Number - Vector Address Bus (VAB)�Bits 12�6
      • 5.6.30.4 Interrupt Disable (INT_DIS)�Bit 5
      • 5.6.30.5 Reserved�Bit 4
      • 5.6.30.6 IRQB State Pin (IRQB STATE)�Bit 3
      • 5.6.30.7 IRQA State Pin (IRQA STATE)�Bit 2
      • 5.6.30.8 IRQB Edge Pin (IRQB Edg)�Bit 1
      • 5.6.30.9 IRQA Edge Pin (IRQA Edg)�Bit 0
  • 5.7 Resets
    • 5.7.1 Reset Handshake Timing
    • 5.7.2 ITCN After Reset
• Part 6 System Integration Module (SIM)
  • 6.1 Overview
  • 6.2 Features
  • 6.3 Operating Modes
  • 6.4 Operation Mode Register
  • 6.5 Register Descriptions
    • 6.5.1 SIM Control Register (SIM_CONTROL)
      • 6.5.1.1 Reserved�Bits 15�7
      • 6.5.1.2 EMI_MODE (EMI_MODE)�Bit 6
      • 6.5.1.3 OnCE Enable (OnCE EBL)�Bit 5
      • 6.5.1.4 Software Reset (SW RST)�Bit 4
      • 6.5.1.5 Stop Disable (STOP_DISABLE)�Bits 3�2
      • 6.5.1.6 Wait Disable (WAIT_DISABLE)�Bits 1�0
    • 6.5.2 SIM Reset Status Register (SIM_RSTSTS)
      • 6.5.2.1 Reserved�Bits 15�6
      • 6.5.2.2 Software Reset (SWR)�Bit 5
      • 6.5.2.3 COP Reset (COPR)�Bit 4
      • 6.5.2.4 External Reset (EXTR)�Bit 3
      • 6.5.2.5 Power-On Reset (POR)�Bit 2
      • 6.5.2.6 Reserved�Bits 1�0
    • 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)
      • 6.5.3.1 Software Control Data 1 (FIELD)�Bits 15�0
    • 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)
    • 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)
    • 6.5.6 SIM Pull-up Disable Register (SIM_PUDR)
      • 6.5.6.1 Reserved�Bit 15
      • 6.5.6.2 PWMA1�Bit 14
      • 6.5.6.3 CAN�Bit 13
      • 6.5.6.4 EMI_MODE�Bit 12
      • 6.5.6.5 RESET�Bit 11
      • 6.5.6.6 IRQ�Bit 10
      • 6.5.6.7 XBOOT�Bit 9
      • 6.5.6.8 PWMB�Bit 8
      • 6.5.6.9 PWMA0�Bit 7
      • 6.5.6.10 Reserved�Bit 6
      • 6.5.6.11 CTRL�Bit 5
      • 6.5.6.12 Reserved�Bit 4
      • 6.5.6.13 JTAG�Bit 3
      • 6.5.6.14 Reserved�Bits 2-0
    • 6.5.7 CLKO Select Register (SIM_CLKOSR)
      • 6.5.7.1 Reserved�Bits 15�10
      • 6.5.7.2 Alternate GPIOB Peripheral Function for A23 (A23)�Bit 9
      • 6.5.7.3 Alternate GPIOB Peripheral Function for A22 (A22)�Bit 8
      • 6.5.7.4 Alternate GPIOB Peripheral Function for A21 (A21)�Bit 7
      • 6.5.7.5 Alternate GPIOB Peripheral Function for A20 (A20)�Bit 6
      • 6.5.7.6 Clockout Disable (CLKDIS)�Bit 5
      • 6.5.7.7 CLockout Select (CLKOSEL)�Bits 4�0
    • 6.5.8 GPIO Peripheral Select Register (SIM_GPS)
      • 6.5.8.1 Reserved�Bits 15�4
      • 6.5.8.2 GPIOC3 (C3)�Bit 3
      • 6.5.8.3 GPIOC2 (C2)�Bit 2
      • 6.5.8.4 GPIOC1 (C1)�Bit 1
      • 6.5.8.5 GPIOC0 (C0)�Bit 0
    • 6.5.9 Peripheral Clock Enable Register (SIM_PCE)
      • 6.5.9.1 External Memory Interface Enable (EMI)�Bit 15
      • 6.5.9.2 Analog-to-Digital Converter B Enable (ADCB)�Bit 14
      • 6.5.9.3 Analog-to-Digital Converter A Enable (ADCA)�Bit 13
      • 6.5.9.4 FlexCAN Enable (CAN)�Bit 12
      • 6.5.9.5 Decoder 1 Enable (DEC1)�Bit 11
      • 6.5.9.6 Decoder 0 Enable (DEC0)�Bit 10
      • 6.5.9.7 Quad Timer D Enable (TMRD)�Bit 9
      • 6.5.9.8 Quad Timer C Enable (TMRC)�Bit 8
      • 6.5.9.9 Quad Timer B Enable (TMRB)�Bit 7
      • 6.5.9.10 Quad Timer A Enable (TMRA)�Bit 6
      • 6.5.9.11 Serial Communications Interface 1 Enable (SCI1)�Bit 5
      • 6.5.9.12 Serial Communications Interface 0 Enable (SCI0)�Bit 4
      • 6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)�Bit 3
      • 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)�Bit 2
      • 6.5.9.15 Pulse Width Modulator B Enable (PWMB)�1
      • 6.5.9.16 Pulse Width Modulator A Enable (PWMA)�0
    • 6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
      • 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])�Bit 1�0
      • 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])�Bit 15�0
  • 6.6 Clock Generation Overview
  • 6.7 Power Down Modes Overview
  • 6.8 Stop and Wait Mode Disable Function
  • 6.9 Resets
• Part 7 Security Features
  • 7.1 Operation with Security Enabled
  • 7.2 Flash Access Blocking Mechanisms
    • 7.2.1 Forced Operating Mode Selection
    • 7.2.2 Disabling EOnCE Access
    • 7.2.3 Flash Lockout Recovery
    • 7.2.4 Product Analysis
• Part 8 General Purpose Input/Output (GPIO)
  • 8.1 Introduction
  • 8.2 Memory Maps
  • 8.3 Configuration
• Part 9 Joint Test Action Group (JTAG)
  • 9.1 JTAG Information
• Part 10 Specifications
  • 10.1 General Characteristics
  • 10.2 DC Electrical Characteristics
    • 10.2.1 Temperature Sense
  • 10.3 AC Electrical Characteristics
  • 10.4 Flash Memory Characteristics
  • 10.5 External Clock Operation Timing
  • 10.6 Phase Locked Loop Timing
  • 10.7 Crystal Oscillator Timing
  • 10.8 External Memory Interface Timing
  • 10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
  • 10.10 Serial Peripheral Interface (SPI) Timing
  • 10.11 Quad Timer Timing
  • 10.12 Quadrature Decoder Timing
  • 10.13 Serial Communication Interface (SCI) Timing
  • 10.14 Controller Area Network (CAN) Timing
  • 10.15 JTAG Timing
  • 10.16 Analog-to-Digital Converter (ADC) Parameters
  • 10.17 Equivalent Circuit for ADC Inputs
  • 10.18 Power Consumption
• Part 11 Packaging
  • 11.1 56F8357 Package and Pin-Out Information
  • 11.2 56F8157 Package and Pin-Out Information
• Part 12 Design Considerations
  • 12.1 Thermal Design Considerations
  • 12.2 Electrical Design Considerations
  • 12.3 Power Distribution and I/O Ring Implementation
• Part 13 Ordering Information