SC-614
Speech And Music Processor
Data sheet
2003 Sensory Inc.
P/N 80-0210-C
1
Features
Advanced, integrated speech synthesizer for
high-quality sound.
Operates up to 12.32 MHz (performs up to 12
MIPS).
Single-chip solution for up to 6.8 minutes of
speech.
External ROM interface for up to 18.8 hours of
speech.
Supports high-quality synthesis algorithms such
as MX, CX, Simple CX, LX, ADPCM, and
polyphonic music.
Simultaneous speech plus music capability.
Very low-power operation, ideal for hand-held
devices.
Low-voltage operation, sustainable by three
batteries.
Reduced power stand-by modes, less than 10
A in deep-sleep mode.
Contains 64k byte words onboard ROM (2k
words reserved).
640-word RAM.
64 I/O pins consisting of 40 general-purpose bit
configurable I/O.
8 inputs with programmable pullup resistor and
dedicated interrupt (key-scan).
16 dedicated output pins.
Direct speaker driver, 32
(PDM).
One-bit comparator with edge-detection
interrupt service.
Resistor-trimmed oscillator or 32.768 khz
crystal reference oscillator.
Serial scan port for in-circuit emulation and
diagnostics.
The SC-614 is sold in die form, or 100-pin
LQFP package.
An emulator device is available in a ceramic
package for development (SC-614-P).
Description
The SC-614 is a low-cost, mixed-signal processor that
combines a speech synthesizer, general-purpose I/O,
onboard ROM, and direct speaker-drive in a single
package. The computational unit utilizes a powerful new
DSP which gives the SC-614 unprecedented speed and
computational flexibility compared with previous devices
of its type. The SC-614 supports a variety of speech and
audio coding algorithms, providing a range of options
with respect to speech duration and sound quality.
The device consists of a micro-DSP core, embedded
program, and data memory, and a self-contained clock generation system. General-purpose periphery is
comprised of 64 bits of partially configurable I/O.
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block
includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt
processor, and several system and control registers. The core processor gives the SC-614 break-point
capability in emulation.
The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and data
memory blocks to permit simultaneous access. It is configured in 32K 17-bit words.
The total ROM space is divided into two areas:
1. The lower 2K words are reserved by Sensory for the purposes of a built-in self-test
2. The upper 30K is for user program/data
SC-614 Block Diagram
16-Bit
Microprocessor
640-words
RAM
64 KBytes
ROM
TIMER 1
TIMER 2
PLLM
10-Bit
DAC
64 I/O
COMPARATOR
SC-614
Data sheet
2
P/N 80-0210-C
2003 Sensory Inc.
The data memory is internal static RAM. The RAM is configured in 640 17-bit words. Both memories are
designed to consume minimum power at a given system clock and algorithm acquisition frequency.
A flexible clock generation system enables the software to control the clock over a wide frequency range. The
implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency
between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced
apart in 65.536 kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a
crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to
provide different levels of power management.
The periphery consists of five 8-bit wide general-purpose I/O ports, one 8-bit wide dedicated input port, and one
16-bit wide dedicated output port. The bidirectional I/O can be configured under software control as either high-
impedance inputs or as totem-pole outputs. They are controlled via addressable I/O registers. The input-only
port has a programmable pullup option (70k
minimum resistance) and a dedicated service interrupt. These
features make the input port especially useful as a key-scan interface.
A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register,
and its pin access is shared with two pins in one of the general-purpose I/O ports. Rounding out the SC-614
periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive
capability. The functional block diagram gives an overview of the SC-614 functionality.
Functional Block Diagram
Data Sheet
SC-614
2003 Sensory Inc.
P/N 80-0210-C
3
Pin Assignment
SC-614
(top view of the die)
19
20
41
42
64
1
65
85
SC-614
(100-lead LQFP)
PB1
PB2
PB3
PB4
PB5
PB6
PB7
VDD1
VSS1
PA0
PA1
PA6
PA7
PLL
OSCIN
OSCOUT
75
74
73
72
71
70
69
68
67
66
65
60
59
58
57
56
NC
NC
NC
55
54
53
PA2
64
PA3
PA4
PA5
63
62
61
VSS
52
PE0
51
26
27
28
29
30
31
32
33
41
42
43
44
45
VS
S4
VD
D
4
NC
NC
PG7
PG6
PG5
PG4
SC
A
N
C
L
K
SC
A
N
I
N
RE
SE
T_
PE
7
PE
6
34
35
36
37
38
39
40
PG3
PG2
PG1
PG0
SC
A
N
OU
T
TE
S
T
SY
N
C
46
47
48
49
50
PE
5
PE
4
PE
3
PE
2
PE
1
100
99
98
97
96
95
94
93
92
91
90
89
81
PD
0
PD
1
PD
2
PD
3
PD
4
PD
5
PD
6
PD
7
V
DD2
VS
S2
PC
0
PC
1
NC
88
87
86
85
84
83
82
PC
2
PC
3
PC
4
PC
5
PC
6
PC
7
NC
80
79
78
77
76
NC
NC
NC
NC
PB
0
VSS3/DA
NC
NC
NC
DACM
VDD3/DA
DACP
VDD
PF7
PF6
PF5
PF4
PG13
1
2
3
4
5
6
7
8
9
10
11
12
20
PF3
PF2
PF1
PF0
NC
PG15
PG14
13
14
15
16
17
18
19
PG12
PG11
PG10
PG9
PG8
21
22
23
24
25
NAME
PIN NO.
PAD NO.
I/O
DESCRIPTION
PA0 PA7
66 59
75 68
I/O Port A general-purpose I/O (1 Byte)
PB0 PB7
76 69
85 78
I/O Port B general-purpose I/O (1 Byte)
PC0 PC7
90 83
8 1
I/O Port C general-purpose I/O (1 Byte)
PD0 PD7
100 93
18 11
I/O Port D general-purpose I/O (1 Byte)
PE0 PE7
51 44
63 56
I/O Port E general-purpose I/O (1 Byte)
PF0 PF7
16 9
31 24
I Port F key-scan input (1 Byte)
PG0 PG7
37 30
49 42
PG8 PG15
25 18
39 32
O Port G dedicated output (2 Bytes)
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set.
Scan Port Control Signals
SCANIN
42
54
I Scan port data input
SCANOUT
38
50
O Scan port data output
SCANCLK
41
53
I Scan port clock
SYNC
40
52
I Scan port synchronization
TEST
39
51
I SC-614: test modes
The scan port pins must be bonded out on any SC-614 production board.
Reference Oscillator Signals
OSCOUT
56
65
O Resistor/crystal reference out
OSCIN
57
66
I Resistor/crystal reference in
PLL 58 67
O
Phase-lock-loop
filter
Digital-to-Analog Sound Output
DACP
7
22
O Digital-to-analog plus output (+)
DACM
5
20
O Digital-to-analog minus output ()
Initialization
RESET_ 43
55
I
Initialization
Power Signals
V
SS
1
, 26, 52, 67, 91 9, 19
, 40, 64, 76
- Ground
V
DD
6
, 8, 27, 68, 92 10, 21
, 23, 41, 77 - Processor power (+)
The V
SS
and V
DD
connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor
across these pins is therefore required.
SC-614
Data sheet
4
P/N 80-0210-C
2003 Sensory Inc.
Absolute Maximum Ratings
Absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
DD
(see Note 1)
0.3 to 7 V
Supply current, I
DD
(see Note 2)
35 mA
Input voltage range, V
I
(see Note 1)
0.3 to VDD + 0.3 V
Output voltage range, V
O
(see Note 1)
0.3 to VDD + 0.3 V
Storage temperature range, T
A
30
C to 125C
WARNING:
Stressing the SC-614 beyond the "Absolute Maximum
Ratings" may cause permanent damage. These are
stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended
exposure beyond the "Operating Conditions" may
affect device reliability.
NOTES: 1. Unless otherwise noted, all voltages are measured with respect to V
SS
.
2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device.
Recommended Operating Conditions
MIN
MAX
UNIT
Supply voltage (with respect to V
SS
), V
DD
3
5.2
V
CPU clock rate (as programmed), f
(CPU)
64
12,320
kHz
Load resistance between DAC
P
and DAC
M
,
R
(DAC)
32
Operating free-air temperature, T
A
Device
functionality
0
70
C
Timing Requirements
MIN
MAX
UNIT
t
(RESET)
Reset low pulse width, while V
DD
is within specified limits
100
ns
t1
(WIDTH)
Pulse width required prior to a negative transition at pin PD3, PD5, or PF0 PF7
2
1/F
CPU
t2
(WIDTH)
Pulse width required prior to a positive transition at pin PD2 or PD4
2
1/F
CPU
While these pins are being used as interrupt inputs.
t
(RESET)
t
(RESET)
Figure 1: Initialization Timing Diagram
t1
(WIDTH)
t2
(WIDTH)
t1
(WIDTH (PD3, PD5, or F port))
t2
(WIDTH (PD2, or PD4))
Figure 2: External Interrupt Pin Pulse Width Requirements t1
WIDTH
and t2
WIDTH
Data Sheet
SC-614
2003 Sensory Inc.
P/N 80-0210-C
5
DC Electrical Characteristics, T
A
= 0 to 70
C
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Positive going threshold
2.4
Negative going threshold
1.8
V
DD
= 3 V
Hysteresis
0.6
V
Positive going threshold
3.3
Negative going threshold
2.9
RESET_ Threshold
changes
V
DD
= 5.2 V
Hysteresis
0.4
V
V
DD
= 3 V
2
3
V
DD
= 4.5 V
3
4.5
V
IH
High-level input voltage
V
DD
= 5.2 V
3.5
5.2
V
V
DD
= 3 V
0
1
V
DD
= 4.5 V
0
1.5
V
IL
Low-level input voltage
V
DD
= 5.2 V
0
1.7
V
I
OH
High-level output current per pin of I/O port
V
OH
= 4 V
2
mA
I
OL
Low-level output current per pin of I/O port
V
OL
= 0.5 V
5
mA
I
OH (DAC)
High-level output DAC current
V
OH
= 4 V
10
mA
I
OL (DAC)
Low-level output DAC current
V
DD
= 4.5 V
V
OL
= 0.5 V
20
mA
I
lkg
Input leakage current
Excludes OSC
IN
1
A
I
(STANDBY)
Standby current
RESET is low
0.05
10
A
I
DD
Operating current
V
DD
= 4.5 V, F
CLOCK
= 12.32 MHz
15
mA
I
(SLEEP-deep)
V
DD
= 4.5 V, DAC off, ARM set, OSC disabled
0.05
10
I
(SLEEP-mid)
V
DD
= 4.5 V, DAC off, ARM set, OSC enabled
40
60
I
(SLEEP-light)
Supply current
V
DD
= 4.5 V, DAC off, ARM clear, OSC enabled
60
100
A
V
IO
Input offset voltage
V
DD
= 4.5 V, V
ref
= 1 to 4.25 V
25
50
mV
R
(PULLUP)
F port pullup resistance
V
DD
= 5 V
70
150
K
f
(RTO-trim)
Trim
deviation
R
RTO
= 470 K
, V
DD
= 4.5 V, T
A
= 25C,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
1% 3%
f
(RTO-volt)
Voltage
deviation
R
RTO
= 470 K
, V
DD
= 3.5 to 5.2 V, T
A
= 25C,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
1.5%
f
(RTO-temp)
Temperature deviation
R
RTO
= 470 K
, V
DD
= 4.5 V, T
A
= 0 to 70C,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
0.03 %/C
f
(RTO-res)
Resistance
deviation
V
DD
= 4.5 V, T
A
= 25C, R
(OSC)
= 470 K
at 1%,
f
RTO
= 8.192 MHz (PLL setting = 7 Ch)
1%
Operating current assumes all inputs are tied to either V
SS
or V
DD
with no input currents due to programmed pullup resistors. The DAC
output and other outputs are open circuited.
The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
Typical voltage and current measurement taken at 25
C
Cannot exceed 15 mA total per internal V
DD
pin. Port A, B share 1 internal V
DD
pin; Port C, D share 1 internal V
DD
.
External Component Absolute Values
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
R
(RTO)
RTO external resistance
T
A
= 25C, 1% tolerance
470
K
C
(PLL)
PLL external capacitance
T
A
= 25C, 10% tolerance
3300
pF
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