ChromaCast
ChromaCast
82C205
LCD Monitor Controller
Advance Information
CONFIDENTIAL
Revision 1.0
912-1000-024
7/8/99
Copyright
No part of this publication may be reproduced, transmitted, transcribed,
stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic,
mechanical, magnetic, optical, manual, or otherwise, without the prior written permission of OPTi Inc., 1440 McCarthy Blvd.
Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and
especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc.
reserves the right to revise the design and associated documentation and to make changes from time to time in the content
without obligation of OPTi Inc. to notify any person of such revisions or changes.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of
their respective holders.
OPTi Inc.
1440 McCarthy Blvd.
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
WWW: http://www.opti.com
Advance Information
82C205
912-1000-024
Page iii
Revision 2.0
Table of Contents
1.
FEATURES .........................................................................................................................................................1
2.
OVERVIEW .........................................................................................................................................................3
3.
SIGNAL DEFINITIONS .......................................................................................................................................5
3.1.
P
IN
D
IAGRAM
.................................................................................................................................................5
3.2.
P
IN
L
ISTING
....................................................................................................................................................6
3.3.
S
IGNAL
D
ESCRIPTIONS
...................................................................................................................................8
3.3.1.
Terminology/Nomenclature Conventions ..............................................................................................8
3.3.2.
CPU and System Interface....................................................................................................................8
3.3.3.
NTSC/PAL Decoder Interface ...............................................................................................................9
3.3.4.
DRAM Interface.....................................................................................................................................9
3.3.5.
Panel Interface Signals .......................................................................................................................10
3.3.6.
Power and Ground Signals .................................................................................................................10
3.4.
T
EST
M
ODE
S
IGNALS
...................................................................................................................................12
3.5.
P
OWER AND
G
ROUND
P
INS
...........................................................................................................................12
3.6.
P
OWER
U
P
S
TRAPPING
A
SSIGNMENTS
..........................................................................................................13
3.6.1.
Panel Type ..........................................................................................................................................13
3.6.2.
Register Base Address Strapping .......................................................................................................13
4.
FUNCTIONAL DESCRIPTION..........................................................................................................................15
4.1.
I
NTERNAL
B
LOCK
D
IAGRAM
...........................................................................................................................15
4.2.
M
ICRO
-C
ONTROLLER
I
NTERFACE
..................................................................................................................15
4.3.
I
NPUT
S
OURCE
.............................................................................................................................................15
4.4.
A
UTOMATIC
R
ESOLUTION
D
ETECTION
...........................................................................................................16
4.5.
TV M
ODE
.....................................................................................................................................................16
4.6.
F
ULL
S
CALE AND
C
ENTERING
O
PTIONS
.........................................................................................................16
4.7.
C
ONTRAST
/B
RIGHTNESS
C
ONTROL
...............................................................................................................16
4.8.
O
N
S
CREEN
D
ISPLAY
...................................................................................................................................16
4.9.
D
ITHERING
...................................................................................................................................................17
4.10.
V
ERSATILE
P
ANEL
S
UPPORT
.....................................................................................................................17
4.11.
C
LOCK
G
ENERATION
.................................................................................................................................17
4.12.
DRAM I
NTERFACE
....................................................................................................................................18
5.
REGISTER DESCRIPTIONS ............................................................................................................................19
5.1.
R
EVISION
R
EGISTER
.....................................................................................................................................19
5.2.
S
YSTEM
C
ONTROL
R
EGISTER
.......................................................................................................................19
Advance Information
82C205
912-1000-024
Page iv
Revision 1.0
5.3.
M
EMORY
C
ONTROL
R
EGISTERS
................................................................................................................... 19
5.4.
OSD R
EGISTERS
........................................................................................................................................ 22
5.5.
D
ITHER
R
EGISTER
S
ETTINGS
....................................................................................................................... 23
5.6.
C
APTURE
CRTC R
EGISTERS
....................................................................................................................... 23
5.7.
S
CALING
R
EGISTERS
................................................................................................................................... 25
5.8.
C
ONTRAST AND
B
RIGHTNESS
C
ONTROL
R
EGISTERS
..................................................................................... 27
5.9.
V
IDEO
I
NPUT
S
OURCE
S
ELECTION
R
EGISTERS
.............................................................................................. 27
5.10.
R
ESOLUTION
D
ETECTION
R
EGISTERS
....................................................................................................... 28
5.11.
TV D
ECODER
I
NTERFACE
R
EGISTERS
...................................................................................................... 29
5.12.
D
ISPLAY
H
ORIZONTAL
S
CALING
................................................................................................................ 30
5.13.
D
ISPLAY
CRTC R
EGISTERS
..................................................................................................................... 30
5.14.
P
ANEL
R
EGISTERS
................................................................................................................................... 33
5.15.
B
ANDWIDTH
C
ONSERVATION
R
EGISTERS
.................................................................................................. 34
5.16.
I
NTERRUPT
C
ONTROL
R
EGISTERS
............................................................................................................ 34
5.17.
CLUT A
CCESS
C
ONTROL
........................................................................................................................ 35
5.18.
ADC
AND
PLL C
ONTROL
R
EGISTERS
....................................................................................................... 35
5.19.
P
OWER
M
ANAGEMENT
R
EGISTERS
........................................................................................................... 35
5.20.
CLUT R
EGISTERS
................................................................................................................................... 36
5.21.
S
TATUS
R
EGISTERS
................................................................................................................................. 38
5.22.
I/O C
ONTROL
R
EGISTERS
........................................................................................................................ 39
6.
TIMING INFORMATION AND WAVEFORMS ................................................................................................. 40
V
ERTICAL
T
IMING FOR
TFT P
ANEL
.......................................................................................................................... 40
6.2.
H
ORIZONTAL
T
IMING FOR
TFT P
ANEL
.......................................................................................................... 41
D
ETAIL OF
P
IXEL
C
LOCK
T
IMING
............................................................................................................................. 41
6.4.
M
ICRO
-C
ONTROLLER
I
NTERFACE
................................................................................................................. 41
7.
208-PIN PQFP MECHANICAL DRAWING ...................................................................................................... 47
Advance Information
82C205
912-1000-024
Page 1
Revision 2.0
1. Features
Digital Input Support
24-bit digital input
300 Mb/sec data rate
Full Screen Image Scaling At All
Resolutions
Incoming video scaled via high quality
interpolation/decimation filters to full panel
screen size
Multiple LCD Panel Type Support
9, 12, 18, 24, 36 bit TFT panel resolution
from 640x480 up to 1280x1024
Drives Single/Multiple Pixels per Clock
90 Hz panel refresh rate for TFT
Super OSD Support
16-color OSD support
Transparent, translucent, inverted video, and
blinking color attribute support
Multi-sync support
Supports incoming video with resolutions
from 640x480 up to 1280x1024
Automatic incoming resolution detection
Horizontal frequency from 15 to 70 kHz
Vertical frequency from 40 to 85 Hz
Host Interface
Direct 8-bit micro-controller interface (8051-
compatible)
LCD TV Support
Direct video decoder interface support for
LCD TV applications
High quality scale up algorithm for TV input
VESA Compliant
DPMS for Display Power Management
FPDI-1 Flat Panel Display Interface
LVDS and PanelLink transceiver interface
for FPDI-2 (24 bpp mode)
Electrical/Physical Specification
0.35
m
process
3.3 Volt power supply
5V-tolerant I/O
208 PQF package
PDF 
ZIP