Revision: 1.0
912-3000-047
January 08, 1998
OPTi
FireBridge II
82C814
Docking Station Controller
Data Book
OPTi Inc.
888 Tasman Drive
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
www.opti.com
ii
Copyright
Copyright 1997, OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored
in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechani-
cal, magnetic, optical, chemical, manual, or otherwise, without the prior written permission of OPTi Incorporated, 888 Tasman
Drive, Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and espe-
cially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the
right to revise the design and associated documentation and to make changes from time to time in the content without obligation
of OPTi Inc. to notify any person of such revisions or changes.
Note:
Before designing contact OPTi for latest Product Alerts, Applications Notes, and Errata for this product line.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their respec-
tive holders.
82C814
Table of Contents
OPTi
912-3000-047
Page iii
Revision: 1.0
January 08, 1998
1.0 Features ............................................................................................................................ 1
2.0 Overview ........................................................................................................................... 1
3.0 Signal Definitions............................................................................................................. 2
3.1
Terminology/Nomenclature Conventions ........................................................................................2
3.2
Signal Descriptions ............................................................................................................................6
3.2.1
Host Interface PCI Signals ..................................................................................................... 6
3.2.2
Docking Control and Sense Signals ....................................................................................... 7
3.2.3
PCI Docking Interface Pins..................................................................................................... 7
3.2.4
Interrupt Interface Pins ........................................................................................................... 9
3.2.5
Power and Ground Pins ......................................................................................................... 9
3.3
Strap-Selected Interface Options ....................................................................................................10
3.4
Internal Resistors .............................................................................................................................11
4.0 Functional Description .................................................................................................. 13
4.1
OPTi Docking Station Controller Chipset.......................................................................................13
4.2
Chipset Compatibility.......................................................................................................................13
4.3
Interface Overview............................................................................................................................13
4.4
Device Type Detection Logic...........................................................................................................14
4.5
Primary PCI Bus................................................................................................................................15
4.6
PCI-to-CardBus Bridge.....................................................................................................................15
4.6.1
Configuration Cycle ..............................................................................................................15
4.6.1.1
Translation Between Type 0 and Type 1 Configuration Cycles ............................15
4.6.2
Cycle from Host to Docking Interface ...................................................................................16
4.6.3
Master Cycle from Docking Interface ...................................................................................16
4.6.4
Inability to Complete a Posted Write ....................................................................................16
4.6.5
Cycle Termination by Target ................................................................................................16
4.6.5.1
Posted Write Termination .....................................................................................16
4.6.5.2
Non-Posted Write Termination..............................................................................16
4.6.5.3
Read (Prefetched or Non-Prefetched) Termination ..............................................16
82C814
OPTi
Table of Contents (cont.)
Page iv
912-3000-047
January 08, 1998
Revision: 1.0
4.7
PCI Docking Station Operation .......................................................................................................17
4.7.1
Introduction........................................................................................................................... 17
4.7.2
Procedure ............................................................................................................................. 17
4.7.3
Initial Setup........................................................................................................................... 17
4.7.4
Action Upon Attachment of Dock.......................................................................................... 18
4.8
Status Change Service Routine ......................................................................................................19
4.8.1
Docking Event ...................................................................................................................... 19
4.8.2
Undocking Event .................................................................................................................. 19
4.8.3
Notes on Undocking ............................................................................................................. 19
4.8.4
Retest ................................................................................................................................... 19
4.8.5
PCI Clock Buffering .............................................................................................................. 20
4.9
Interrupt Support ..............................................................................................................................20
4.9.1
PCI INTx# Implementation ................................................................................................... 20
4.9.2
IRQ Driveback Logic............................................................................................................. 20
4.9.3
Compaq Serial IRQ Implementation..................................................................................... 21
4.9.3.1
Operation .............................................................................................................. 21
5.0 82C814 Register Set ...................................................................................................... 23
5.1
Register State on Device Removal..................................................................................................23
5.2
Base Register Group ........................................................................................................................23
5.3
82C814-Specific Register Group .....................................................................................................31
5.3.1
CLKRUN#............................................................................................................................. 31
5.3.2
Slot Buffer Enable, Slew Rate, and Threshold Control......................................................... 31
5.3.3
Dual ISA Buses .................................................................................................................... 31
5.4
CardBus Register Group..................................................................................................................34
5.4.1
Power Control....................................................................................................................... 34
5.5
Docking Station Window Selection Group.....................................................................................36
5.5.1
Docking Station Window Registers ...................................................................................... 36
5.5.1.1
Cycle Decoding..................................................................................................... 37
5.5.1.2
Cycle Trapping...................................................................................................... 37
5.5.1.3
ISA Window Selection........................................................................................... 37
5.6
PCI Power Management Register Group........................................................................................41
82C814
OPTi
Table of Contents (cont.)
912-3000-047
Page v
Revision: 1.0
January 08, 1998
6.0 Electrical Ratings ........................................................................................................... 43
6.1
Absolute Maximum Ratings.............................................................................................................43
6.2
DC Characteristics: VCC = 3.3V or 5.0V 5%, TA = 0C to +70C.................................................43
6.3
AC Characteristics............................................................................................................................44
6.4
AC Timing Diagrams ........................................................................................................................45
7.0 Mechanical Package Outline......................................................................................... 47
Appendix A
IRQ Driveback Protocol ................................................................................. 49
A.1
Driveback Cycle Format...................................................................................................................49
A.2
Edge vs Level Mode, IRQ Polarity...................................................................................................50
A.3
Host Handling of IRQ Driveback Information.................................................................................50
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