FireLink 1394 OHCI
Link Controller
82C881
Preliminary Data Book
CONFIDENTIAL
Revision 1.0
912-2000-031
December 13, 1999
Copyright
Copyright 1999 OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored
in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic,
mechanical, magnetic, optical, manual, or otherwise, without the prior written permission of OPTi Inc., 1440 McCarthy Blvd.
Milpitas, CA 95035.
Disclaimer
OPTi Inc. makes no representations or warranties with respect to the design and documentation herein described and
especially disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves
the right to revise the design and associated documentation and to make changes from time to time in the content without
obligation of OPTi Inc. to notify any person of such revisions or changes.
Trademarks
OPTi and OPTi Inc. are registered trademarks of OPTi Inc. All other trademarks and copyrights are the property of their
respective holders.
OPTi Inc.
1440 McCarthy Blvd.
Milpitas, CA 95035
Tel: (408) 486-8000
Fax: (408) 486-8001
WWW: http://www.opti.com
FireLink 1394 OHCI
82C881
912-2000-031
Page i
Revision: 1.0
T
ABLE
OF
C
ONTENTS
1.0
FEATURES ......................................................................................................................................................................1
2.0
OVERVIEW ......................................................................................................................................................................1
3.0
SIGNAL DEFINITIONS ....................................................................................................................................................3
3.1
T
ERMINOLOGY
/N
OMENCLATURE
C
ONVENTIONS
..................................................................................................................3
3.2
N
UMERICAL
P
IN
C
ROSS
-R
EFERENCE
L
IST
.........................................................................................................................5
3.3
S
TRAPPING
O
PTIONS
.......................................................................................................................................................6
3.3.1
Test Mode Selection (Pins 77, 78) .......................................................................................................................6
3.3.2
Serial EEPROM Presence Detect (Pin 5).............................................................................................................6
3.4
S
IGNAL
D
ESCRIPTIONS
....................................................................................................................................................7
3.4.1
PCI Bus Interface Signals.....................................................................................................................................7
3.4.2
PHY-Link Interface Signal Set ..............................................................................................................................9
3.4.3
Miscellaneous Signals ........................................................................................................................................10
4.0
FUNCTIONAL DESCRIPTION.......................................................................................................................................11
4.1
F
UNCTIONAL
B
LOCK
D
ESCRIPTION
..................................................................................................................................11
4.1.1
PCI Interface ......................................................................................................................................................11
4.1.2
DMA Control Block .............................................................................................................................................13
4.1.3
Serial EEPROM Interface...................................................................................................................................13
4.1.4
Arbiter.................................................................................................................................................................14
4.1.5
Register Block ....................................................................................................................................................14
4.1.6
FIFO Block .........................................................................................................................................................14
4.1.7
Link Block ...........................................................................................................................................................15
4.2
S
ERIAL
EEPROM I
NTERFACE
........................................................................................................................................16
4.2.1
Read Operations from the Serial EEPROM........................................................................................................16
4.2.2
Write operations to the Serial EEPROM.............................................................................................................16
4.2.3
Related PCICFG Registers ................................................................................................................................17
4.2.4
Serial EEPROM MAP .........................................................................................................................................18
5.0
REGISTER DESCRIPTIONS .........................................................................................................................................19
5.1
OHCI
AND
B
US
M
ANAGEMENT
C
ONTROL AND
S
TATUS
R
EGISTERS
....................................................................................19
5.2
FIFO C
ONFIGURATION
R
EGISTERS
.................................................................................................................................19
5.2.1
Tx FIFO-Related Registers.................................................................................................................................20
5.2.2
Rx FIFO-Related Registers ................................................................................................................................21
5.3
PCI C
ONFIGURATION
R
EGISTERS
...................................................................................................................................23
FireLink 1394 OHCI
82C881
912-2000-031
Revision: 1.0
Page ii
5.3.1
PCI Configuration Space (PCICFG 00h to 3Fh) ................................................................................................ 23
5.4
P
OWER
M
ANAGEMENT
R
EGISTERS
................................................................................................................................. 25
5.5
T
IMING
I
NFORMATION
.................................................................................................................................................... 28
6.0
ELECTRICAL RATINGS............................................................................................................................................... 29
7.0
MECHANICAL PACKAGE............................................................................................................................................ 31
8.0
TEST MODES ............................................................................................................................................................... 33
9.0
APPENDIX A................................................................................................................................................................. 35
9.1
A
CRONYMS AND
D
EFINITIONS
........................................................................................................................................ 35
9.2
R
EFERENCES
............................................................................................................................................................... 35
10.0
APPENDIX B................................................................................................................................................................. 37
10.1
FIFO P
ROGRAMMING
................................................................................................................................................... 37
10.1.1
Programming Notes........................................................................................................................................... 37
10.1.2
Important User Defined Values.......................................................................................................................... 37
10.1.3
Current Default Configuration Values ................................................................................................................ 37
10.2
D
EBUG
F
EATURES
........................................................................................................................................................ 38
10.2.1
Reading/Writing Tx FIFO and Rx FIFO Bypassing DMA / Link Logic ................................................................ 38
10.2.2
Implementation .................................................................................................................................................. 42
10.2.3
Direct Read of Internal Signals .......................................................................................................................... 42
FireLink 1394 OHCI
82C881
912-2000-031
Page 1
Revision: 1.0
1.0 Features
The OPTi 82C881 1394 OHCI Link Controller is a PCI-
based host controller with the following features.
Compliant with PCI Local Bus Specification 2.1
Compliant with P1394a Draft 2.0 Standard for a High-
performance Serial Bus
Interfaces to 33MHz, 32-bit PCI bus
PnP (Plug and Play) compatible per PCI Local Bus
Specification rev. 2.1
Implements IEEE1212-based control and status
registers that can be mapped to both I/O and memory
space
Incorporates independent DMA controllers for
isochronous and asynchronous operations
Supports four isochronous transmit and isochronous
receive contexts
Supports burst transactions on the PCI bus interface
Offers direct access to the physical address space of
the host
Assigns priority for DMA per 1394 OHCI specification
1.00
Supports four transmit and three receive configurable
FIFOs
Offers both packet per-buffer and buffer-fill modes of
operation for the isochronous receive context
Incorporates two wire industry-standard Serial
EEPROM interface
Functions as a 1394 cycle master
Supports asynchronous and isochronous transfers at
100, 200 and 400 Mbps
Implements a fully Bus Manager Capable node
including an Isochronous Resource Manager
Interfaces to PHYs that conform to the Link-PHY
interface described in Chapter 5 of the P1394a Draft
2.0 specification
Interfaces to 1394-1995 compliant PHYs
Offers selective disabling of 1394a features
(controllable by software) for interfacing to a partially
P1394a compliant PHY
Supports posting of physical write request packets
Complies with the PCI Power Management
specification rev. 1.1, supporting ACPI states D0 and
D3
hot
and PME# generation
Incorporates CLKRUN# support
Implements comprehensive Debug Registers
Implements physical upper bound register.
2.0 Overview
This document describes the OPTi FireLink 1394 OHCI
Link Controller (82C881). It details:
Signal Definitions
Strap Selectable Options
Functionality
Register Descriptions.
FireLink 1394 System Block Diagram
FireLink
TriFire
82C881
1394
82C842
PHY
1394
Port
1394
Port
1394
Port
P
C
I
B
u
s
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