TABLE OF CONTENTS

1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 DOCUMENT SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.0 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 MANCHESTER ENCODER/DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 MANCHESTER DECODER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 COLLISION TRANSLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.5 TP DIFFERENTIAL DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.6 TP DIFFERENTIAL RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.7 LOOPBACK FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.8 LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.9 AUI/TP AUTOSELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.10 JABBER AND SQE TEST FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.11 STATUS INDICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.12 TEST MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.0 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.0 DC ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.0 AC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.0 PACKAGE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

83C694D

LIST OF ILLUSTRATIONS

Figure

Title

Page

1-1

SYSTEM BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1-2

83C694C BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2-1

CRYSTAL CONNECTION DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2-2

AUI TRANSMIT PATH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2-3

AUI RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2-4

ZENER DIODE VOLTAGE REGULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2-5

TWISTED PAIR TRANSMIT PATH AND TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2-6

TWISTED PAIR RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3-1

83C694C PLCC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5-1

TRANSMIT TIMING - START OF TRANSMISSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5-2

TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 0) . . . . . . . . . . . . . . . . . 21

5-3

TRANSMIT TIMING - END OF TRANSMISSION (LAST BIT = 1) . . . . . . . . . . . . . . . . . 22

5-4

TRANSMIT TIMING - LINK TEST PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5-5

RECEIVE TIMING - START OF PACKET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5-6

RECEIVE TIMING - END OF PACKET (LAST BIT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 23

5-7

RECEIVE TIMING - END OF PACKET (LAST BIT = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 24

5-8

COLLISION TIMING (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5-9

COLLISION TIMING (TP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5-10

SQE TEST TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5-11

LOOPBACK TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5-11

TEST LOADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6-1

44-PIN PLCC PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

LIST OF TABLES

Table

Title

Page

3-1

PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4-1

DC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5-1

AC OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5-2

83C694C TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

83C694D

1.0

INTRODUCTION

1.1

DOCUMENT SCOPE

This document describes the function and opera-
tion of the 83C694D Twisted-Pair Interface and
Manchester Encoder/Decoder. It includes a de-
scription of external logic necessary for the efficient
use of this device and its proper role in the chip set
which includes the 83C690 and 83B692 as shown
in Figure 1-1. Figure 1-2 provides a functional block
diagram of the 83C694D chip itself.

1.2

FEATURES

Features of the 83C694D include:

Twisted-Pair interface solution for IEEE 802.3
10BaseT Standard

Compatible with Ethernet II (10BASE5) and
Cheapernet (10BASE2) IEEE 802.3 Stand-
ards

Smart Squelch

digital noise filter at receive

and collision inputs to reject noise and digital
noise on twisted-pair receive inputs.

Direct connection to the transceiver (AUI) ca-
ble

16V fault protection at the AUI transmitter in-
terface

10 Mbps Manchester encoding/ decoding with
receive clock recovery

Low power, 1.25

CMOS technology

TTL/MOS-compatible controller interface

Externally-selectable half- or full-step modes
of operation at AUI TX

outputs

Loopback capability for diagnostics

Single station interface operation

Link test generation and digital equalization for
twisted-pair transmitter

Automatic phase detection

AUI/TP autoselect

Built-in LED drivers for transmit, receive, link
test and polarity status indicators

1.3

GENERAL DESCRIPTION

The 83C694D is used for applications where
Twisted-Pair Interface (TPI) and/or Attachment Unit
Interface (AUI) functions are required. Its two main
functions are to:

Receive a digital data stream from a low-level
input signal and

Convert a digital output data stream into an
analog high-current signal for transmission
across a network cable.

This means that the 83C694D serves as the logical
link between a network cable on one end and a
digital controller chip (such as the 83C690) on the
other end.

To accomplish these two functions, the 83C694D
consists of these components: Manchester en-
coder/decoder, balanced drivers and receivers, on-
board crystal oscillator, signal translator, diagnostic
circuit, and protocol timers and state machines.

The remainder of this data sheet contains the fol-
lowing information:

Section 2 discusses the system architecture in-
cluding an explanation of all chip circuits.

Section 3 provides pin descriptions.

Section 4 provides DC Operating Characteristics.

Section 5 provides AC Operating Characteristics
including Interface Timing diagrams.

Section 6 provides the PLCC package diagram of
this chip.

INTRODUCTION

83C694D

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 83C694

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 83C694