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Data Sheet: ACD80800

1. SUMMARY

The ACD80800 serves as an Address Resolution Logic
for ACD's switch controller chips (ACD82124,
ACD82012 etc.) through a glueless ARL interface. It
automatically builds up an address table and can map
up to 8K MAC addresses into their associated ports.

The ACD80800 can work without a CPU in a unmanaged
switch system, or with a CPU and an ACD MIB
(ACD80900 Management Information Base). A direct
input/output interface is integrated to support a man-
agement CPU. The CPU can configure the operation
mode of the ACD80800, learn all the addresses in the
address table, add new addresses into the table, con-
trol security or filtering features of each address entry,
etc.

The ACD80800 is designed with such a high perfor-
mance that, it will never slow down the frame switching
operation conducted by the ACD's switch controllers.
Together with the non-blocking architecture of the ACD's
switch controllers, the chip set (a ACD switch controller
plus the ACD80800, plus ACD80900 in a managed
switch system) can provide wire speed forwarding rate
under any type of traffic load.

2. FEATURES

Supports up to 8K MAC address lookup

Provides Glueless ARL Interface with ACD's
switch controller chip

Provides Direct Input/Output type of interface for
the management CPU

Provides UART type of interface for the manage-
ment CPU

Wire speed address lookup time.

Wire speed address learning time.

Address can be automatically learned from switch
without THE CPU intervention

Address can be manually added by the CPU
through the CPU interface

Each MAC address can be secured by the CPU
from being changed or aged out

Each MAC address can be marked by the CPU
from receiving any frame

Each newly learned MAC address is notified to
the CPU

Each aged out MAC address is notified to the
CPU

Automatic address aging control, with
configurable aging period

0.35 micron, 3.3V CMOS technology

128-Pin PQFP package

ACD82xxx

n-Port Fast Ethernet

Switch Controller

A S R A M

ACD80800

A d d r e s s R e s o l u t i o n

L o g i c

ACD80900

M I B

C P U

P(n-1)

P 1

P 0

Figure-1: ACD80800 Used in A Managed n-Port Fast Ethernet Switch System

P(n-3)

P(n-2)

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Data Sheet: ACD80800

C P U I n t e r f a c e

Address

Registers

Data

Registers

Command

Registers

Control

Registers

Switch Interface

A d d r e s s

Learning

E n g i n e

C P U I n t e r f a c e E n g i n e

A d d r e s s T a b l e

(8K Entries)

Figure-2. ACD80800 Block Diagram

A d d r e s s

A g i n g

E n g i n e

A d d r e s s

L o o k u p

E n g i n e

3. FUNCTIONAL DESCRIPTION

ACD80800 provides Address Resolution service for
ACD's switch controller chip. ACD80800 provides a
glueless interface with ACD's switch controller, and is
used to build an address table and provide address lookup
service to ACD's switch controller.

Figure 2 is a block

diagram of ACD80800.

Traffic Snooping

All Ethernet frames received by ACD's switch controller
have to be stored into memory buffer. As the frame
data are written into memory, the status of the data
shown on the data bus are displayed by ACD's switch
controller through a state bus. ACD80800's Switch Con-
troller Interface contains the signals of the data bus and
the state bus. By snooping the data bus and the state
bus of ACD's switch controller, ACD80800 can detect
the occurrence of any destination MAC address and
source MAC address embedded inside each frame.

Address Learning

Each source address caught from the data bus, to-
gether with the ID of the ingress port, is passed to the
Address Learning Engine of ACD80800. The Address

Learning Engine will first determine whether the frame
is a valid frame. For a valid frame, it will first try to find
the source address from the current address table. If
that address doesn't exist, or if it does exist but the port
ID associated with the MAC address is not the ingress
port, the address will be learned into the address table.
After an address is learned by the address learning
engine, the CPU will be notified to read this newly learned
address so that it can add it into the CPU's address
table.

Address Aging

After each source address is learned into the address
table, it has to be refreshed at least once within each
address aging period. Refresh means it is caught again
from the switch interface. If it has not occurred for a
pre-set aging period, the address aging engine will re-
move the address from the address table. After an ad-
dress is removed by the address aging engine, the CPU
will be notified through interrupt request that it needs to
read this aged out address so that it can remove this
address from the CPU's address table.

Address Lookup

Each destination address is passed to the Address

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Data Sheet: ACD80800

Lookup Engine of ACD80800. The Address Lookup
Engine checks if the destination address matches with
any existing address in the address table. If it does,
ACD80800 returns the associated Port ID to ACD's
switch controller through the output data bus. Other-
wise, a no match result is passed to ACD's switch con-
troller through the output data bus.

CPU Interface

ACD80800 provides a direct input/output type of inter-
face for a management CPU to access various kind of
registers inside ACD80800. The interface has 8-bit data
bus, and 5-bit address bus. The timing of read and
write operation is controlled by output enable signal and
write enable signal. For details of CPU interface timing
information, refer to the section of "Timing Descrip-
tion."

The CPU can also choose to access the registers of
ACD80800 by sending commands to the UART data
input line. Each command is consisted by action (read
or write), register type, register index, and data. Each
result of command execution is returned to the CPU
through the UART data output line.

CPU Interface Registers

ACD80800 provides a bunch of registers for the control

CPU. Through the registers, the CPU can read all ad-
dress entries of the address table, delete particular ad-
dresses from the table, add particular addresses into
the table, secure an address from being changed, set
filtering on some addresses, change the hashing algo-
rithm etc. Through a proper interrupt request signal, the
CPU can be notified whenever it needs to retrieve data
for a newly-learned address or an aged-out address so
that the CPU can build an exact same address table
learned by ACD80800.

CPU Interface Engine

The command sent by the control CPU is executed by
the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned ad-
dress. The CPU Interface Engine is responsible to find
the newly-learned address from the address table, and
passes it to CPU. The CPU may request to learn next
newly-learned address. Then, it is again the responsi-
bility of the CPU Interface Engine to search for next
newly-learned address from the address table.

Address Table

The address table can hold up to 8K MAC addresses,
together with the associated port ID, security flag, filter-
ing flag, new flag, aging information etc. The address
table resides in the embedded SRAM inside ACD80800.

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Data Sheet: ACD80800

4. PIN DESCRIPTIONS

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

9 6

9 5

9 4

9 3

9 2

9 1

9 0

8 9

8 8

8 7

8 6

8 5

8 4

8 3

8 2

8 1

8 0

7 9

7 8

7 7

7 6

7 5

7 4

7 3

7 2

7 1

7 0

6 9

6 8

6 7

6 6

6 5

128

125

126

127

124

121

122

123

120

117

118

119

116

113

114

115

112

109

110

111

108

105

106

107

104

103

G N D

S W D I 6 3

S W D I 6 2

S W D I 6 1

S W D I 6 0

S W D I 5 9

S W D I 5 8

S W D I 5 7

S W D I 5 6

S W D I 5 5

S W D I 5 4

S W D I 5 3

S W D I 5 2

S W D I 5 1

S W D I 5 0

S W D I 4 9

S W D I 4 8

V D D

G N D

S W D I 4 7

S W D I 4 6

S W D I 4 5

S W D I 4 4

S W D I 4 3

S W D I 4 2

S W D I 4 1

S W D I 4 0

V D D

GND

S W D I 3 9

G N D

V D D

S W D I 0

S W D I 1

S W D I 2

S W D I 3

S W D I 4

S W D I 5

VDD

GND

n R E S E T

VDD

SWDI24

SWDI26

SWDI25

SWDI28

S W D I 3 8

SWDI29

SWDI27

SWDI19

SWDI20

SWDI7

SWDI8

SWDI22

SWDI23

SWDI21

SWDI13

SWDI14

SWDI16

SWDI15

SWDI18

VDD

SWDI17

SWDI10

SWDI12

SWDI11

SWDI9

G N D

Figure-3: Pin Diagram Of ACD80800 (The ARL Chip)

S W D O 0

S W D O 1

S W D O V

S W D O 3

S W D O 2

3 3

3 4

3 5

3 6

3 7

3 8

S W D I 3 7

S W D I 3 6

S W D I 3 5

S W D I 3 4

S W D I 3 3

S W D I 3 2

1 0 1

1 0 2

1 0 0

9 7

9 8

9 9

S W D I 3 1

S W D I 3 0

SWDI6

G N D

V D D

GND

S W S T A T 0

S W E O F

S W S T A T 3

S W P I D 1

S W P I D 2

S W P I D 4

S W P I D 3

S W S Y N C

G N D

V D D

S W S T A T 2

S W S T A T 1

S W D I R 0

S W C L K

S W P I D 0

UARTDO

UARTDI

S W D I R 1

CPUD7

CPUD6

CPUD5

CPUD4

CPUD3

CPUD2

CPUD1

CPUD0

GND

VDD

nCPUOE

nCPUCS

CPUA0

nCPUWE

CPUA1

CPUA2

CPUA3

CPUA4

GND

G N D

W C H D O G

CPUIRQ

G N D

N C

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Data Sheet: ACD80800

Pin Table

Pin Name

Description

I/O

Pin Name

Description

I/O

GND

Ground.

GND

Ground.

S WDI63 Data from s witch controller chip. 3.3V

S WDI5

Data from s witch controller chip.

3.3V

S WDI62 Data from s witch controller chip. 3.3V

S WDI4

Data from s witch controller chip.

3.3V

S WDI61 Data from s witch controller chip. 3.3V

S WDI3

Data from s witch controller chip.

3.3V

S WDI60 Data from s witch controller chip. 3.3V

S WDI2

Data from s witch controller chip.

3.3V

S WDI59 Data from s witch controller chip. 3.3V

S WDI1

Data from s witch controller chip.

3.3V

S WDI58 Data from s witch controller chip. 3.3V

S WDI0

Data from s witch controller chip.

3.3V

S WDI57 Data from s witch controller chip. 3.3V

VDD

3.3V power s upply.

S WDI56 Data from s witch controller chip. 3.3V

GND

Ground.

S WDI55 Data from s witch controller chip. 3.3V

S WDOV

Output data valid s ignal to s witch controller chip.

3.3V

S WDI54 Data from s witch controller chip. 3.3V

S WDO3

Output data to s witch controller chip.

3.3V

S WDI53 Data from s witch controller chip. 3.3V

S WDO2

Output data to s witch controller chip.

3.3V

S WDI52 Data from s witch controller chip. 3.3V

S WDO1

Output data to s witch controller chip.

3.3V

S WDI51 Data from s witch controller chip. 3.3V

S WDO0

Output data to s witch controller chip.

3.3V

S WDI50 Data from s witch controller chip. 3.3V

VDD

3.3V power s upply.

3.3V

S WDI49 Data from s witch controller chip. 3.3V

GND

Ground.

S WDI48 Data from s witch controller chip. 3.3V

GND

Ground.

VDD

3.3V power s upply.

S WCL K

50MHz reference clock s ignal from s witch controller chip.

3.3V

GND

Ground.

S WPID0

Port ID indication s ignal from s witch controller chip.

3.3V

S WDI47 Data from s witch controller chip. 3.3V

S WPID1

Port ID indication s ignal from s witch controller chip.

3.3V

S WDI46 Data from s witch controller chip. 3.3V

S WPID2

Port ID indication s ignal from s witch controller chip.

3.3V

S WDI45 Data from s witch controller chip. 3.3V

S WPID3

Port ID indication s ignal from s witch controller chip.

3.3V

S WDI44 Data from s witch controller chip. 3.3V

S WPID4

Port ID indication s ignal from s witch controller chip.

3.3V

S WDI43 Data from s witch controller chip. 3.3V

S WS YNC

Port 0 indication s ignal from s witch controller chip.

3.3V

S WDI42 Data from s witch controller chip. 3.3V

S WE OF

E nd Of F rame indication s ignal from s witch controller chip. 3.3V

S WDI41 Data from s witch controller chip. 3.3V

VDD

3.3V power s upply.

S WDI40 Data from s witch controller chip. 3.3V

GND

Ground.

S WDI39 Data from s witch controller chip. 3.3V

S WS T AT 0 Data S tatus s ignal from s witch controller chip.

3.3V

S WDI38 Data from s witch controller chip. 3.3V

S WS T AT 1 Data S tatus s ignal from s witch controller chip.

3.3V

S WDI37 Data from s witch controller chip. 3.3V

S WS T AT 2 Data S tatus s ignal from s witch controller chip.

3.3V

S WDI36 Data from s witch controller chip. 3.3V

S WS T AT 3 Data S tatus s ignal from s witch controller chip.

3.3V

S WDI35 Data from s witch controller chip. 3.3V

S WDIR0

Data direction indication s ignal from s witch controller chip. 3.3V

S WDI34 Data from s witch controller chip. 3.3V

S WDIR1

Data direction indication s ignal from s witch controller chip. 3.3V

S WDI33 Data from s witch controller chip. 3.3V

Not connected.

S WDI32 Data from s witch controller chip. 3.3V

nRE S E T

Hardware res et pin.

3.3V

S WDI31 Data from s witch controller chip. 3.3V

100 WCHDOG Watch dog s ignal.

3.3V

S WDI30 Data from s witch controller chip. 3.3V

101 GND

Ground.

VDD

3.3V power s upply.

102 VDD

3.3V power s upply.

GND

Ground.

103 GND

Ground.

S WDI29 Data from s witch controller chip. 3.3V

104 UART DI

UART data input line.

3.3V

S WDI28 Data from s witch controller chip. 3.3V

105 UART DO

UART data output line.

3.3V

S WDI27 Data from s witch controller chip. 3.3V

106 VDD

3.3V power s upply.

S WDI26 Data from s witch controller chip. 3.3V

107 GND

Ground.

S WDI25 Data from s witch controller chip. 3.3V

108 CPUIRQ

Interrupt reques t.

3.3V

S WDI24 Data from s witch controller chip. 3.3V

109 CPUD0

CPU data bus .

3.3V I/O

S WDI23 Data from s witch controller chip. 3.3V

110 CPUD1

CPU data bus .

3.3V I/O

S WDI22 Data from s witch controller chip. 3.3V

111 CPUD2

CPU data bus .

3.3V I/O

S WDI21 Data from s witch controller chip. 3.3V

112 CPUD3

CPU data bus .

3.3V I/O

S WDI20 Data from s witch controller chip. 3.3V

113 CPUD4

CPU data bus .

3.3V I/O

S WDI19 Data from s witch controller chip. 3.3V

114 CPUD5

CPU data bus .

3.3V I/O

S WDI18 Data from s witch controller chip. 3.3V

115 CPUD6

CPU data bus .

3.3V I/O

S WDI17 Data from s witch controller chip. 3.3V

116 CPUD7

CPU data bus .

3.3V I/O

S WDI16 Data from s witch controller chip. 3.3V

117 VDD

3.3V power s upply.

S WDI15 Data from s witch controller chip. 3.3V

118 GND

Ground.

S WDI14 Data from s witch controller chip. 3.3V

119 CPUA0

CPU addres s bus .

3.3V

S WDI13 Data from s witch controller chip. 3.3V

120 CPUA1

CPU addres s bus .

3.3V

S WDI12 Data from s witch controller chip. 3.3V

121 CPUA2

CPU addres s bus .

3.3V

S WDI11 Data from s witch controller chip. 3.3V

122 CPUA3

CPU addres s bus .

3.3V

S WDI10 Data from s witch controller chip. 3.3V

123 CPUA4

CPU addres s bus .

3.3V

S WDI9

Data from s witch controller chip. 3.3V

124 nCPUOE

Output E nable s ignal from CPU.

3.3V

S WDI8

Data from s witch controller chip. 3.3V

125 nCPUWE

Write E nable s ignal from CPU.

3.3V

S WDI7

Data from s witch controller chip. 3.3V

126 nCPUCS

Chip S elect s ignal from CPU.

3.3V

S WDI6

Data from s witch controller chip. 3.3V

127 GND

Ground.

VDD

3.3V power s upply.

128 VDD

3.3V power s upply.

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Data Sheet: ACD80800

Table-1: Switch Interface

Name

Type

Description

SWDI0 ~

SWDI63

Input data, which can be 48-

bit or 64-bit wide

SWSTAT0 ~

SWSTAT3

Input data state

SWEOF

End of frame indication signal

SWDIR0 ~

SWDIR1

Data direction indication

signal

SWSYNC

Port synchronization signal

SWPID0 ~

SWPID4

Port-ID indication signal

SWCLK

Reference clock

SWDOV

Output data valid signal

SWDO0 ~

SWDO3

Output data which can be 2-

bit or 4-bit wide

5. INTERFACE DESCRIPTION

Switch Interface

Switch interface provides a communication channel
between ACD's switch controller chip and ACD80800.
As a frame is being received by ACD's switch control-
ler chip , the destination address and source address
of the frame are snooped from the SWDIx lines of
ACD80800, with respect to the SWCLK signal.
ACD80800 carries a lookup process for each destina-
tion address, and a learning process for each source
address. The result of the lookup is returned to the switch
controller chip through the SWDOx lines.

Table 1 shows

the associated signals in the Switch Interface.

The SWDIx signal comes from the SRAM Data bus of
ACD's switch controller chip . Since all data of the re-
ceived frames have to be written into the shared memory
through the Data bus, the bus can be monitored for
occurrence of DA and SA values, indicated by the as-
sociated state bits. The signals in SWDIx bus can be a
48-bit or 64-bit wide data bus. For a 48-bit wide bus,
the first word will be the DA and the second word will be
the SA. For a 64-bit wide bus, DA is the first 48-bit of
first word, SA is the last 16-bit of first word plus first 32-
bit of second word.

SWDIR is a 2-bit signal to indicate the direction of the
data displayed on the SWDI bus, 01 for receiving, 10
for transmitting, 00 or 11 for other states. ACD80800
only deals with the received data.

SWSTAT bus is a 4-bit signal, used to indicate the mean-
ing (status) of the data. The 4-bit status is defined as:

0000 - Third to Last word

0001 - First word

0010 - Second word

0011 - Reserved

0100 - Reserved

0101 - Drop event

0110 - Jabber

0111 - False carrier

1000 - Alignment error

1001 - Flow control/collision

1010 - Short event/excessive collision

1011 - Runt/Late collision

1100 - Symbol error

1101 - FCS error

1110 - Long event

1111 - Reserved

Note: error type depends on SWDIR is 01 or

10.

SWSYNC is used to indicate port 0 is driving the Data
bus. It is used when the bus is evenly allocated in a time
division multiplexing manner, such that a monitoring de-
vice can implement a counter to indicate the ID of the
port which is driving the SWDI bus, and use SWSYNC
signal to reset the counter. When SWSYNC is in use,
SWPID is ignored.

SWPID is used to indicate the ID of the port which is
driving the Data bus. When SWPID is in use, SWSYNC
is ignored.

SWEOF is used to indicate the start and end of a frame.
It is always asserted when the corresponding port is
idling. The start of a frame is indicated by a high-to-low
transition of SWEOF signal. The end of a frame is indi-
cated by a low to high transition of SWEOF signal.

SWCLK is used to provide timing reference of input
data snooping and output data latching. The signal is
also used as the system clock of the chip.

SWDOV is used to indicate the start of a lookup result
package.

SWDOx is used to return the result of lookup to ACD's
switch controller chip. Data is latched onto SWDOx bus
with respect to the rising edge of SWCLK signal. Each
result package is consisted by 5-bit source port ID, 2-
bit result, and 5-bit destination port ID. The 2-bit result
field is defined as 01 for match, with the port ID shown
by the 5-bit destination port ID field; 10 for no match;
11 for forced disregard (filtering).

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Data Sheet: ACD80800

Table-2: CPU Interface

Name

I/O

Description

CPUA0 ~

CPUA4

5 address lines for register

selection.

CPUD0 ~

CPUD7

I/O

8 data lines.

nCPUOE

Read enable signal, low active.

nCPUWE

Write enable signal, low active.

nCPUCS

Chip Select signal, low active.

CPUIRQ

Interrupt request signal.

UARTDI

UART input data line.

UARTDO

UART output data line.

Header

Address

Data

Checksum

Header

Address

Data

Checksum

Table-3: Other Interface

Name

I/O

Description

WCHDOG

Alive signal from ACD80800 to indicate

it is working properly.

nRESET

Hardware reset signal, low active.

VDD

3.3V power supply.

GND

Ground.

CPU Interface

The CPU interface provides a communication channel
between the CPU and the ACD80800. Basically, the
CPU sends command to the ACD80800 by writing into
associated registers, and retrieve result from ACD80800
by reading corresponding registers. The registers are
described in the section of "Register Description." The
CPU interface signals are described by

table 2:

CPUAx is the address bus used to select the registers
of the ACD80800.

CPUDx is the data bus used to pass data between the
CPU and the registers of the ACD80800.

nCPUOE is used to control the timing of the read op-
eration.

nCPUWE is used to control the timing of the write op-
eration.

nCPUCS is used to make the ACD80800 active to the
nCPUOE or nCPUWE signals.

CPUIRQ is used to generate an interrupt request to the
CPU. For each source of the interrupt, refer to the de-
scription of the interrupt source register.

UARTDI is used by the control CPU to send command
into the ACD80800. The baud rate will be automatically
detected by the ACD80800. The result will be returned
through the UARTDO line with the detected baud rate.
The format of the command packet is shown as follows:

where:

Header is further defined as:

b1:b0 - read or write, 01 for read,
11 for write

b4:b2 - device number, 000 to 111
(0 to 7)

b7:b5 - device type, 010 for ARL

Address - 8-bit value used to select the reg-
ister to access

Data - 32-bit value, only the LSB is used
for write operation, all 0 for read operation

Checksum - 8-bit value of XOR of all bytes

UARTDO is used to return the result of command ex-
ecution to the CPU. The format of the result packet is
shown as follows:

where:

Header is further defined as:

b1:b0 - read or write, 01 for read,
11 for write

b4:b2 - device number, 000 to 111
(0 to 7)

b7:b5 - device type, 010 for ARL

Address - 8-bit value for address of the
selected register

Data - 32-bit value, only the LSB is used
for read operation, all 0 for write operation

Checksum - 8-bit value of XOR of all bytes

The ACD80800 will always check the CMD header to
see if both the device type and the device number
matches with its setting. If not, it ignores the command
and will not generate any response to this command.

Other Interface

(table 3)

WCHDOG signal is used to prevent the system from
hitting dead-lock by any abnormal event. Under normal
condition, the output signal from the WCHDOG pin will
not stay at low for longer than 10ms. If the state of

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Data Sheet: ACD80800

Table-4: Register Description

Reg.

Name

Description

DataReg0

Byte 0 of data

DataReg1

Byte 1 of data

DataReg2

Byte 2 of data

DataReg3

Byte 3 of data

DataReg4

Byte 4 of data

DataReg5

Byte 5 of data

DataReg6

Byte 6 of data

DataReg7

Byte 7 of data

AddrReg0

LSB of address value

AddrReg1

MSB of address value

CmdReg

Command register

RsltReg

Result register

CfgReg

Configuration register

IntSrcReg

Interrupt source register

IntMskReg

Interrupt mask register

nLearnReg0

Address learning disable

nLearnReg1

Address learning disable

nLearnReg2

Address learning disable

AgeTimeReg0

LSB of aging period register

AgeTimeReg

MSB of aging period

PosCfg0

Power On Strobe

configuration register 0

PosCfg1

Power On Strobe

configuration register 1

WCHDOG remains at low state, the chip is not working
properly and needs to be reset.

nRESET pin is used to do a hardware reset to the
ACD80800. Please note that after a hardware reset, all
learned address is cleared, and the address table has
to be built again.

Configuration Interface

The following table shows the Power-On-Strobed con-
figuration setting:

into the command register. When a new command is
written into the command register, ACD80800 will
change the status of the Result register to 0. The
Result register will indicate the completion of the
command at the end of the execution. Before the
completion of the execution, any command written into
the command register is ignored by ACD80800.

The registers accessible to the CPU are described by
table 4:

The

DataRegX are registers used to pass the param-

eter of the command to the ACD80800, and the result
of the command to the CPU.

The

AddrRegX are registers used to specify the

address associated with the command.

The

CmdReg is used to pass the type of command to

the ACD80800. The command types are listed in

table

5. The details of each command is described in the
chapter of "Command Description."

Power-On-Strobed Setting

Name

Description

Shared

Pin#

BIST
Enable

Boot-Internal-Self-Test for
optional internal RAM test

IC Test
Enable

IC Manufacturer test use only:
always pull low

DIO
Enable

1 = Data I/O

0 = UART Mode

Port ID
Select

1 = for 82124 or 82012

0 = reserved

NO CPU

11 = No CPU, 80800 will self
initiate

74/111

00 = With CPU, 80800 will wait
for CPU to initiate

Bus Width
Selection

00 = 32 bit ( reserved )

110/109

01 = 48 bit ( 82124 or 82012)
10 = reserved
11 = 64 bit ( reserved )

UART ID

000 = ID for the only or the first
80800 on the system

114/113/112

001 = ID for the second 80800
on the system with two 80800s

Note: High=1=Enable

6. REGISTER DESCRIPTION

ACD80800 provides a bunch of registers for the CPU
to access the address table inside it. Command is
sent to ACD80800 by writing into the associated
registers. Before the CPU can pass a command to
ACD80800, it must check the result register

(register

11) to see if the command has been done. When the
Result register indicates the command has been done,
the CPU may need to retrieve the result of previous
command first. After that, the CPU has to write the
associated parameter of the command into the Data
registers. Then, the CPU can write the command type

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Data Sheet: ACD80800

Table-5: Command List

Command

Description

0x09

Add the specified MAC address into the

address table

0x0A

Set a lock for the specified MAC address

0x0B

Set a filtering flag for the specified MAC

address

0x0C

Delete the specified MAC address from

the address table

0x0D

Assign a port ID to the specified MAC

address

0x10

Read the first entry of the address table

0x11

Read next page with specified PID

0xFF

System reset

The

RstReg is used to indicate the status of command

execution. The result code is listed as follows:

01 - command is being executed and is
not done yet

10 - command is done with no error

1x - command is done, with error indi-
cated by x, where x is a 4-bit error code:
0001 for cannot find the entry as speci-
fied

The

CfgReg is used to configure the way the

ACD80800 works. The bit definition of CfgReg is
described as:

bit 0 - disable address aging

bit 1 - disable address lookup

bit 2 - disable DA cache

bit 3 - disable SA cache

bit 7:4 - hashing algorithm selection,
default is 0000

The

IntSrcReg is used to indicate what can cause

interrupt request to CPU. The source of interrupt is
listed as:

bit 0 - aged address exists

bit 1 - new address exists

bit 2 - reserved

bit 3 - reserved

bit 4 - bucket overflowed

bit 5 - command is done

bit 6 - system initialization is completed

bit 7 - self test failure

The

IntMskReg is used to enable an interrupt source

to generate an interrupt request. The bit definition is
the same as IntSrcReg. A 1 in a bit enables the
corresponding interrupt source to generate an
interrupt request once it is set.

The

nLearnReg[2:0] are used to disable address

learning activity from a particular port. If the bit
corresponding to a port is set, ACD80800 will not try
to learn new addresses from that port.

The

AgeTimeReg[1:0] are used to specify the period

of address aging control. The aging period can be
from 0 to 65535 units, with each unit counted as 2.684
second.

The

PosCfgReg0 is a configuration register whose

default value is determined by the pull-up or pull-down
status of the associated hardware pin. The bits of
PosCfgReg0 is listed as follows:

bit 0 - BISTEN, shared with ARLDO0, 0
for no self test, 1 for enable self test

bit 1 - TESTEN, shared with ARLDO1, 0
for normal operation, 1 for production
test.

bit 2 - DIOEN, shared with ARLDO2, 0 for
using UART, 1 for using DIO.

bit 3 - SYNCEN, shared with ARLDO3, 0
for using SWPID, 1 for using SWSYNC.

bit 4 - NOCPU

, 0 for have a control CPU,

1 for do not have a control CPU.

Note: When

NOCPU is set as 0, ACD80800 will not

start the initialization process until a System Start
command is sent to the command register.

The

PosCfgReg1 is a configuration register whose

default value is determined by the pull-up or pull-down
status of the associated hardware pin. The bits of
PosCfgReg1 is listed as follows:

bit 1:0 - BUSMODE, shared with
CPUD1:CPUD0, bus width selection, 01
for 48-bit, 10 for 64 bit.

bit 2 - CPUGO, shared with CPUD2, only
effective when NOCPU bit of PosCfgReg0
is set to 1. Setting CPUGO to 0 means

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Data Sheet: ACD80800

Rsvd Rsvd Filter Lock New

Old

Age Valid

wait for the CPU to send the System Start
command before the initialization process
can be started.

bit 5:3 - UARTID, shared with
CPUD5:CPUD3, 3-bit ID for UART
communication.

7. COMMAND DESCRIPTION

Command 09H

Description: Add the specified MAC address into the
address table.

Parameter: Store the MAC address into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. Store
the associated port number into DataReg6.

Result: the MAC address will be stored into the
address table if there is space available. The result is
indicated by the Result register.

Command 0AH

Description: Set the Lock bit for the specified MAC
address.

Parameter: Store the MAC address into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.

Result: the state machine will seek for an entry with
matched MAC address, and set the Lock bit of the
entry. The result is indicated by the Result register.

Command 0BH

Description: Set the Filter flag for the specified MAC
address.

Parameter: Store the MAC address into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.

Result: the state machine will seek for an entry with
matched MAC address, and set the Filter bit of the
entry. The result is indicated by the Result register.

Command 0CH

Description: Delete the specified MAC address from
the address table.

Parameter: Store the MAC address into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB.

Result: the MAC address will be removed from the
address table. The result is indicated by the Result
register.

Command 0DH

Description: Assign the associated port number to the
specified MAC address.

Parameter: Store the MAC address into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. Store
the port number into DataReg6.

Result: the port ID field of the entry containing the
specified MAC address will be changed accordingly.
The result is indicated by the Result register.

Command 10H

Description: Read the first entry of the address table.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of the first entry of the address book will be stored into
the Data registers. The MAC address will be stored
into DataReg5 - DataReg0, with DataReg5 contains
the MSB of the MAC address and DataReg0 contains
the LSB. The port number is stored in DataReg6, and
the Flag

bits are stored in DataReg7.The Read

Pointer will be set to point to second entry of the
address book.

Note - the Flag bits are defined as:

where:

Filter - 1 indicates the frame heading to
this address should be dropped.

Lock - 1 indicates the entry should never
be changed or aged out.

New - 1 indicates the entry is a newly
learned address.

Old - 1 indicates the address has been
aged out.

Age - 1 indicates the address has not

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Data Sheet: ACD80800

been visited for current age cycle.

Valid - 1 indicates the entry is a valid one.

Rsvd - Reserved bits.

Command 11H

Description: Read next entry of address book.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of the address book entry pointed by Read Pointer will
be stored into the Data registers. The MAC address
will be stored into DataReg5 - DataReg0, with
DataReg5 contains the MSB of the MAC address and
DataReg0 contains the LSB. The port number is
stored in DataReg6, and the Flag bits are stored in
DataReg7. The Read Pointer will be increased by one.

Command 20H

Description: Read first valid entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first valid entry of the address book will be stored
into the Data registers. The MAC address will be
stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry.

Command 21H

Description: Read next valid entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next valid entry from the Read Pointer of the
address book will be stored into the Data registers.
The MAC address will be stored into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. The
port number is stored in DataReg6, and the Flag bits
are stored in DataReg7. The Read Pointer is set to
point to this entry.

Command 30H

Description: Read first new page.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first new entry of the address book will be stored
into the Data registers. The MAC address will be
stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry.

Command 31H

Description: Read next new entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next new entry from the Read Pointer of the
address book will be stored into the Data registers.
The MAC address will be stored into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. The
port number is stored in DataReg6, and the Flag bits
are stored in DataReg7. The Read Pointer is set to
point to this entry.

Command 40H

Description: Read first aged entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first aged entry of the address book will be stored
into the Data registers. The MAC address will be
stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry.

Command 41H

Description: Read next aged entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next aged entry from the Read Pointer of the
address book will be stored into the Data registers.
The MAC address will be stored into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the

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Data Sheet: ACD80800

MAC address and DataReg0 contains the LSB. The
port number is stored in DataReg6, and the Flag bits
are stored in DataReg7. The Read Pointer is set to
point to this entry.

Command 50H

Description: Read first locked entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first locked entry of the address book will be stored
into the Data registers. The MAC address will be
stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry.

Command 51H

Description: Read next locked entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next locked entry from the Read Pointer of the
address book will be stored into the Data registers.
The MAC address will be stored into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. The
port number is stored in DataReg6, and the Flag bits
are stored in DataReg7. The Read Pointer is set to
point to this entry.

Command 60H

Description: Read first filtered page.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first filtered entry of the address book will be stored
into the Data registers. The MAC address will be
stored into DataReg5 - DataReg0, with DataReg5
contains the MSB of the MAC address and DataReg0
contains the LSB. The port number is stored in
DataReg6, and the Flag bits are stored in DataReg7.
The Read Pointer is set to point to this entry.

Command 61H

Description: Read next valid entry.

Parameter: None

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next filtered entry from the Read Pointer of the
address book will be stored into the Data registers.
The MAC address will be stored into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. The
port number is stored in DataReg6, and the Flag bits
are stored in DataReg7. The Read Pointer is set to
point to this entry.

Command 80H

Description: Read first entry with specified port
number.

Parameter: Store port number into DataReg6.

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of first entry of the address book with the said port
number will be stored into the Data registers. The
MAC address will be stored into DataReg5 -
DataReg0, with DataReg5 contains the MSB of the
MAC address and DataReg0 contains the LSB. The
port number is stored in DataReg6, and the Flag bits
are stored in DataReg7. The Read Pointer is set to
point to this entry.

Command 81H

Description: Read next valid entry.

Parameter: Store port number into DataReg6.

Result: The result is indicated by the Result register. If
the command is completed with no error, the content
of next entry from the Read Pointer of the address
book with the said port number will be stored into the
Data registers. The MAC address will be stored into
DataReg5 - DataReg0, with DataReg5 contains the
MSB of the MAC address and DataReg0 contains the
LSB. The port number is stored in DataReg6, and the
Flag bits are stored in DataReg7. The Read Pointer is
set to point to this entry.

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