ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

Buffer

Q u e u e M a n a g e r

Lookup Engine

(2K MAC Addr.)

LED Controller

BIST Handler

A R L

ACD80800

(11K MAC Addr.)

(optional)

M I B

ACD80900

(optional)

ARL Interface

S R A M

M A C - 0

M A C - 1

M A C - 1 0

M A C - 1 1

SRAM Interface

MIB Interface

P M D /

P H Y - 0

P M D /

P H Y - 1

P M D /

P H Y - 1 0

P M D /

P H Y - 1 1

M X

D M X

Buffer

FIFO

ACD82112

3. SYSTEM BLOCK DIAGRAM

1. GENERAL DESCRIPTION

The ACD82112 is a single chip implementation of a 12
port 10/100 Ethernet switch system intended for IEEE
802.3 and 802.3u compatible networks. The device in-
cludes 12 independent 10/100 MACs. Each MAC inter-
faces with an external PMD/PHY device through a stan-
dard MII interface. Speed can be automatically config-
ured through the MDIO or the optional CPU UART. Each
port can operate at either 10Mbps or 100Mbps, in half-
duplex or full-duplex mode. The core logic of the
ACD82112, implemented with patent pending BASIQ
(Bandwidth Assured Switching with Intelligent Queu-
ing) technology, can simultaneously process 12 asyn-
chronous 10/100Mbps traffics. The Queue Manager in-
side the ACD82112 provides the capability of routing
traffic with the same order of sequence, without any
packet loss.

A complete 12 port 10/100 switch can be built with the
use of the ACD82112, 10/100 PHY and SRAM. The
MAC addresses space can be expanded from the built-
in 2K to 11K by using ACD's external ARL (

Address

Resolution Logic), the ACD80800. Advanced network
management features can be supported with the use of
ACD's

MIB (Management Information Base,

ACD80900) chip.

2. MAIN FEATURES

�

12 - 10/100 Mbps, auto-sensing ports with MII in-
terface

�

Full / half duplex operation

�

2.4 Gbps aggregated throughput

�

True non-blocking switch architecture

�

Shared buffer with starvation control algorithm

�

Built-in storage of 2,048 MAC addresses

�

Automatic source address learning

�

Optional back-pressure (half duplex) flow control

�

802.3x pause frame (full duplex) flow control

�

Store-and-forward switch mode

�

Port based VLAN support

�

UART type CPU management interface

�

Supports up to 11K addresses with External ARL
controller, the ACD80800

�

RMON and SNMP support with External MIB con-
troller, the ACD80900

�

Status LEDs: Link, Speed, Full/Half Duplex, Trans-
mit, Receive, Collision and Frame Error

�

Reversible MII option for CPU and expansion port
interface, with hardware based flow control

�

Wire speed forwarding rate

�

388-pin PBGA package (including 36 Thermal
Ground pins at the center)

�

3.3V power, 3.3V I/O with 5V tolerance

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

Preamble SFD DA SA Ty pe/Len Data FCS

4. SYSTEM DESCRIPTION

The ACD82112 is a single chip implementation of a 12-
port Fast Ethernet switch. Together with external SRAM
devices and transceiver devices, it can be used to build
a complete 10/100 Mbps Fast Ethernet switch. Each
individual port can be either auto-sensing or manually
selected to run at 10 Mbps or 100 Mbps speed rates
and under Full or Half-duplex mode.

The ACD82112 Ethernet switch contains three major
functional blocks: the Media Access Controller (MAC),
the Queue Manager, and the Lookup Engine.

There are 12 independent MACs within the ACD82112.
The MAC controls the receiving, transmitting, and de-
ferring process of each individual port, in accordance
to the IEEE 802.3 and 802.3u standards. The MAC logic
also provides framing, FCS checking, error handling,
status indication and flow control functions. Each MAC
interfaces with an external transceiver through a stan-
dard MII interface.

The device utilizes ACD's proprietary BASIQ (Band-
width Assured Switching with Intelligent Queuing) tech-
nology. It is a technology to efficiently enforce the first-
in-first-out rule of Ethernet Bridge-type devices. The
technology enables a true non-blocking frame switch-
ing operation at wire speeds for a high throughput and
high port density Ethernet switch.

The on-chip Lookup Engine implements a 2,048 entries
MAC address lookup table. It maps each destination
address into a corresponding port. Each MAC address
is automatically learned by the LOOKUP ENGINE after
an error-free frame is received. Therefore, the
ACD82112 alone can be used to build a complete Fast
Ethernet switch with up to 2,048 host connections

. (For

detailed information about the built-in ARL, please re-
fer to the ACD80800 data sheet.)

For workgroup or backbone switches, the ACD82112
can support more MAC addresses per port through the
use of an external ARL chip, the ACD80800. The
ACD82112 has a glueless ARL interface that allows a
supporting chip (ACD80800) to provide up to 11K MAC
addresses per switch. System designers can also use
this ARL interface to implement a vendor-specific ad-
dress resolution algorithm.

The ACD82112 provides management support through
its MIB (Management Information Base) interface. The
MIB interface can be used to monitor all traffic activities
of the switch system. The supporting chip (the
ACD80900) provides a full set of statistical counters to
support both SNMP and RMON network management
functions. System designers can also use the MIB in-

terface to implement vendor-specific network manage-
ment functionality.

Among the 12 MII interfaces, 5 of them can be config-
ured as reversed MII, to connect directly with stand-
alone MAC controller devices. A MAC in the ACD82112
can be viewed logically as a PHY device if it is config-
ured as the reversed MII interface. Reversed MII is in-
tended for a CPU network interface, or an expansion
port interface.

The System CPU can access various registers inside
the ACD82112 through a serial CPU management in-
terface. The CPU can configure the switch by writing
into the appropriate registers, or retrieve the status of
the switch by reading the corresponding registers. The
CPU can also access the registers of external trans-
ceiver (PHY) devices through the CPU management
interface.

5. FUNCTIONAL DESCRIPTION

The MAC controller performs transmit, receive, and de-
fer functions, in accordance to the 802.3 and 802.3u
specification. The MAC logic also handles frame detec-
tion, frame generation, error detection, error handling,
status indication and flow control functions. Under full-
duplex mode, the flow control is implemented in compli-
ance with IEEE 802.3x standard.

Frame Format

The ACD82112 assumes that the received data packet
will have the following format:

Where,

Preamble is a repetitive pattern of `1010....' of any length

with nibble alignment.

The

SFD (Start Frame Delimiter) is defined as an octet

pattern of 10101011.

The

DA (Destination Address) is a 48-bit field that speci-

fies the MAC address of the destined DTE. If the first
bit of DA is 1, the ACD82112 will treat the frame as a
broadcast/multicast frame and will forward the frame to
all ports within the source port's VLAN except the source
port itself or BPDU address.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

The

SA (Source Address) is a 48-bit field that contains

the MAC address of the source DTE that is transmitting
the frame to the ACD82112. After a frame is received
with no error, the SA is learned as the port's MAC ad-
dress.

The

Type/Len field is a 2-byte field that specifies the

type (DIX Ethernet frame) or length (IEEE 802.3 frame)
of the frame. The ACD82112 does not process this in-
formation.

The

Data is the encapsulated information within the

Ethernet Packet. The ACD82112 does not process any
of the data information in this field.

The

FCS (Frame Check Sequence) is a 32-bit field of

CRC (Cyclic Redundancy Check) value based on the
destination address, the source address, the type/length
and the data field. The ACD82112 will verify the FCS
field for each frame. The procedure for computing FCS
is described in the section "FCS Calculation."

Start of Frame Detection

When a port's MAC is idle, assertion of the RXDV in
the MII interface will cause the port to go into the re-
ceive state. The MII presents the received data in 4-bit
nibbles that are synchronous to the receive clock (25Mhz
or 2.5MHz). The ACD82112 will convert this data into a
serial bit stream, and attempt to detect the occurrence
of the SFD (10101011) pattern. All data prior to the
detection of SFD are discarded. Once SFD is detected,
the following frame data are forwarded and stored in
the buffer of the switch.

Frame Reception

Under normal operating conditions, the ACD82112 ex-
pects a received frame to have a minimum inter frame
gap (IFG). The minimum IFG required by the device is
64 BT.

In the event the ACD82112 receives a packet with IFG
less than 64 BT, the ACD82112 does not guarantee to
be able to receive the frame. The packet will be dropped
if the ACD82112 cannot receive the frame.

The device will check all received frames for errors such
as symbol error, FCS error, short event, runt, long event,
jabber, etc. Frames with any kind of error will not be
forwarded to any port.

Preamble Bit Processing

The preamble bit in the header of each frame will be
used to synchronize the MAC logic with the incoming
bit stream. The minimum length of the preamble is 0 bits
and there is no limitation on the maximum length of pre-
amble. After the receive data valid signal RXDV is as-
serted by the external PHY device, the port will wait for
the occurrence of the SFD pattern (10101011) and then
start a frame receiving process.

Source Address and Destination Address

After a frame is received by the ACD82112, the em-
bedded destination address and source address are
retrieved. The destination address is passed to the lookup
table to find the destination port. The source address is
automatically stored into the address lookup table. For
applications that uses an external ARL, the ACD82112
will disable the internal lookup table and pass the DA
and SA to the external ARL for address lookup and
learning.

During the receive process, the Lookup Engine will at-
tempt to match the destination address with the addresses
stored in the address table. If there is a match found, a
link between the source port and the destination port is
then established. If an external ARL is used, the
ACD82112 indicates the presence of 48-bit DA through
the status line of the ARL interface. The external ARL
will use the value of DA for address comparison and
return a result of the lookup to the ACD82112.

Frame Data

Frame data are transparent to the ACD82112. The
ACD82112 will forward the data to destination port(s)
without interpreting the content of the frame data field.

FCS Calculation

Each port of the ACD82112 has a CRC checking logic
to verify if the received frame has a correct FCS value.
A wrong FCS value is an indication of a fragmented
frame or a frame with frame bit error. The method of
calculating the CRC value is using the following polyno-
mial,

G(x) =

x32 + x26 + x23 + x22 + x16 + x12 + x11

+ x10 + x8 + x7 + x5 + x4 + x2 + x + 1

as a divider to divide the bit sequence of the incoming
frame, beginning with the first bit of the destination ad-
dress field, to the end of the data field. The result of the

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Data Sheet: ACD821

INTRODUCT

calculation, which is the residue after the polynomial
division, is the value of the frame check sequence. This
value should be equal to the FCS field appended at the
end of the frame. If the value does not match the FCS
field of the frame, the Frame Bit Error LED of the port
will be turned on once and the packet will be dropped.

Illegal Frame Length

During the receiving process, the MAC will monitor the
length of the received frame. Legal Ethernet frames
should have a length of not less than 64 bytes and no
more than 1518 bytes. If the carrier-sense signal of a
frame is asserted for less than 76 BT, the frame is flagged
with short event error. If the length of a frame is less
then 512 BT, the frame is flagged with runt error.

In order to support an application where extra byte length
is required, an Extra long frame option

is provided. When

the Extra long frame option is enabled

(Table-7.24, bit-

7), only frames longer than 1530 bytes are marked with
a long event error. Frame length is measured from the
first byte of DA to the last byte of FCS.

Frame Filtering

Frames with any kind of error will be filtered. Types of
error include code error (indicated by assertion of RXER
signal), FCS error, alignment error, short event, runt,
and long event.

Any frame heading to its own source port will be fil-
tered.

When external ARL is used, the filtering decision will be
made by the ARL. The ACD82112 will act in accor-
dance with the ARL's direction.

If the

Spanning Tree Support option is enabled, frames

containing DA equal to any reserved Bridge Manage-
ment Group Address specified in Table 3.5 of the IEEE
802.1D will not be forwarded to any ports, except Port-
11, which may receive BPDU frames

If spanning tree

support is not enabled, frames with DA equal to the
reserved Group Address for PBDU will be broadcasted
to all ports in the same VLAN of the source port.

Jabber Lockup Protection

If a receiving port is active continuously for more than
50,000 bit times, the port is considered to be jabbering.
A jabbering port will automatically be partitioned from
the switch system in order to prevent it from impairing
the performance of the network. The partitioned port

will be re-activated as soon as the offending signal dis-
continues.

Excessive Collision

In the event that there are more than 16 consecutive
collisions, the ACD82112 will reset the counter to zero
and retransmit the packet. This implementation insures
there is no packet loss even under channel capture
situation. However, the ACD82112 has an option to drop
the packet on excessive collisions. When this option is
enabled

(Table-7.24, bit-11), the frame will be dropped

after 16 consecutive collisions.

If a port has encountered 256 consecutive collisions, it
is assumed to be non-functional and will be partitioned.
The partitioned port will not receive any frame. It will still
transmit new frames, but without retry after encounter-
ing a collision. The partition port will be released once a
new frame is transmitted without incurring a collision,
which indicates that, the port has regained normal func-
tions.

False Carrier Events

If the signal in the MII interface is asserted but the re-
ceive data valid (RXDV) signal is not, and the RXD shows
1110 at the same time, the port is considered to have a
false carrier event. If a port has more than two con-
secutive false carrier events, the port will automatically
be partitioned from the switch system. The partitioned
port will be re-activated if it has been idling for 33,000
BT or it has received 500 bits of valid data after a mini-
mum 64 BT idle period.

Frame Forwarding

If the first bit of the destination address is 0, the frame
is handled as a unicast frame. The destination address
is passed to the Address Resolution Logic; which re-
turns a destination port number to identify which port
the frame should be forwarded to. If the Address Reso-
lution Logic cannot find any match for the destination
address, the frame will be treated as a frame with un-
known DA. The frame will be processed in one of two
ways. If the option flood-to-all-port is enabled, the switch
will forward the frame to all ports within the same VLAN
of the source port, except the source port itself. If the
option is not enabled, the frame will be forwarded to the
`dumping port' of the source port VLAN only. The dump-
ing port is determined by the VLAN ID of the source
port. If the source port belongs to multiple VLANs, a
frame with unknown DA will then be forwarded to mul-
tiple dumping ports of the VLANs.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

If the first bit of the destination address is a 1, the frame
is handled as a multicast or broadcast frame. The
ACD82112 does not differentiate a multicast packet from
a broadcast packet except for the reserved bridge man-
agement group address, as specified in Table 3.5 of
IEEE 802.1D standard. The destination ports of a broad-
cast frame are all ports within the same VLAN except
the source port itself.

The order of all broadcast frames with respect to the
unicast frames is strictly enforced by the ACD82112.

Frame Transmission

The ACD82112 transmits all frames in accordance to
IEEE 802.3 standard. The ACD82112 will send the
frames with a guaranteed minimum interframe gap of
96 BT, even if the received frames have an IFG less
than the minimum requirement. Before the transmit pro-
cess is started, the MAC logic will check if the channel
has been silent for more than 64 BT. Within the 64 BT
silent window, the transmission process will defer on
any receiving process. If the channel has been silent
for more than 64 BT, the MAC will wait an additional 32
BT before starting the transmit process. In the event
that the carrier sense signal is asserted by the MII dur-
ing the wait period, the MAC logic will generate a JAM
signal to cause a forced collision.

The MAC logic will abort the transmit process if a colli-
sion is detected through the assertion of the Col signal
of the MII. Re-transmission of the frame is scheduled in
accordance to the IEEE 802.3's truncated binary expo-
nential backoff algorithm. If the transmit process has
encountered 16 consecutive collisions, an excessive
collision error is reported, and the ACD82112 will try to
re-transmit the frame, unless the drop-on-excessive-
collision option of the port is enabled. It will first reset
the number of collisions to zero and then start the trans-
mission after a 96 bit time of inter frame gap. If drop-
on-excessive-collision is enabled, the ACD82112 will not
try to re-transmit the frame after 16 consecutive colli-
sions. If collision is detected after 512 BT of the trans-
mission, a late collision error will be reported, but the
frame will still be retransmitted after proper backoff time.

Frame Generation

During a transmit process, frame data is read out from
the memory buffer and is forwarded to the destination
port's PHY device in nibbles. 7 bytes of a preamble
signal (10101010) will be generated first followed by the
SFD (10101011), and then the frame data and 4 bytes
of FCS are sent out at last.

Shared Buffer

All ports of the ACD82112 work in Store-And-Forward
mode so that all ports can support both 10Mbps and
100Mbps data speeds. The ACD82112 utilizes a global
memory buffer pool, which is shared by all ports. The
device has a unique architecture that inherits the ad-
vantage of both output buffer-based and input buffer-
based switches. The output buffer-based switches store
the received data only once into the memory, and hence
has a short latency. Whereas input buffer based
switches typically have more efficient flow control.

Starvation Control Scheme

All frames received by the ACD82112 will be stored
into a common physical frame buffer pool. In order to
make sure all ports have fair access to the network, a
buffer allocation scheme (starvation control) is used to
prevent active ports from occupying all the buffers and
starve off the less active ports.

The frame buffer pool is divided into 3 portions: the
reserved pool, the common pool and the extra pool,
as shown in

Figure-5.1:

Extra Pool

(shared by all full duplex ports

with flow control capability)

Reserved Pool

(dedicated to each port)

Common Pool

(shared by all the ports)

~ 5 0 %

~ 8 0 %

Figure-5.1: Buffer Partition

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Data Sheet: ACD821

INTRODUCT

The

reserved pool guarantees each port will have a

fair network access possibility, even under the worst
traffic congestion situation. It takes about 50% of the
total buffer and is evenly allocated to each port as its
dedicated buffer slot. The dedicated slot is not shared
with other ports.

The

common pool provides a deep buffer for the busy

ports (e.g. server port) to serve multiple low speed
ports (e.g. client port) simultaneously. It helps to avoid
head-of-line blocking. It takes about 30% of the total
buffer and is shared by all ports. It stores the con-
gested traffics before the flow control mechanism is
triggered.

The

extra pool is reserved only for ports with pause

frame based flow control capacity. It takes the remain-
ing 20% of the total buffer. It is used to minimize the
chance of frame dropping by buffering for the latency
of the pause frame based flow control scheme. It is
used only after a flow control mechanism is triggered.

Flow Control Scheme

Flow control activity is triggered when the buffer
utilization exceeds certain thresholds specified by the
dedicated registers.

Upper and the Lower Thresholds of the reserved
buffer slot for each port.

specify the Upper and the Lower thresholds of the
broadcast queue.

Under full duplex operation, if the buffer utilization of a
port has exceeded the upper threshold of the reserved
buffer slot, and the common pool has been used up,

max-pause-frame ( a pause frame with a maximum
time interval of FFFFh) will be sent to the sending
party to stop it from sending new frames. If pause-
frame based flow control is not enabled at that port,
the frame will be dropped. Once a

max-pause-frame

is sent, if the utilization of the reserved buffer slot of
the port drops below the lower threshold, a

mini-

pause-frame (a pause frame with minimum time
interval of 0) will be sent to the linking party to enable
new frame transmission.

Under half duplex operation, if the buffer utilization of
a port has exceeded the upper threshold of the
reserved buffer slot, and the common pool has been
used up, the port will execute back-pressure based
flow control by sending a jam pattern on each incom-
ing frame. If backpressure flow control of the port is
not enabled, the frame will be dropped.

If the broadcast flow control is enabled (when bit-13 of
register-25 is set), flow control will be triggered when

the broadcast queue is longer than the upper thresh-
old specified by

pause-frame capability will send a

max-pause-frame

to its linking party. All half-duplex ports with
backpressure capability will jam incoming frames.
After a max-pause-frame is sent, and if the broadcast
queue is shorten below the lower threshold specified
by

release the hold on transmission.

VLAN Support

(Registers 23 & 24)

The ACD82112 can support up to 4 port-based security
VLANs. Each port of the ACD82112 can be assigned to
up to four VLAN. On power up, every port is assigned
to VLAN-I as the default VLAN. Frames from the source
port will only be forwarded to destination ports within
the same VLAN domain. A broadcast/multicast frame
will be forwarded to all ports within the VLAN(s) of the
source port. A unicast frame will be forwarded to the
destination port only if the destination port is in the same
VLAN as the source port. Otherwise, the frame will be
treated as a frame with unknown DA. Each VLAN can
be assigned with a dedicated dumping port. Multiple
VLANs can also share a dumping port. Unicast frames
with unknown destination addresses will be forwarded
to the dumping port of the source port VLAN.

Security VLAN can be disabled by setting the corre-
sponding bit in the system configuration register (bit 8
of

is disabled, each VLAN becomes a Leaky VLAN and is
equivalent to a broadcast domain. Four dumping ports
of four different Leaky VLANs can be grouped together
to form a fat pipe uplink (for example, port 0, port 1,
port 2, and port 3 can be grouped to form an 800 Mbps
uplink port). When multiple dumping ports are grouped
as a single pipe, each port has to be assigned to one
and only one VLAN. A unicast frame with a matched
DA will be forwarded to any destination port, even if the
VLAN ID is different. All unmatched DA packets will be
forwarded to the designated dumping port of the source
port VLAN. The broadcast and multicast packets will
only be forwarded to the ports in the same VLAN of the
source port. Therefore, a 200 to 800 Mbit/s pipe can be
established by carefully grouping the dumping ports,
and directly connecting with any segmentation switches.

Dumping Port

Each VLAN can be assigned with a dedicated dumping
port. Multiple VLANs can share a dumping port. Each
dumping port can be used for an up-link connection or
for a DTE connection. That is, the dumping port can be
used to connect the switch with a computer repeater

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Data Sheet: ACD821

INTRODUCT

hub, a workgroup switch, a router, or any type of inter-
connection device compliant with IEEE 802.3 standard.
ACD82112 will direct the following frames to the dump-
ing port:

�

A frame with a unicast destination address that does
not match with any port's source address within the
VLAN of the source port.

�

A frame with a broadcast/multicast destination ad-
dress*.

*See

Spanning Tree Support

If the device is configured to work under Flood-to-All-
Port mode

(Register 25, bit 8), the frames with un-

known DA will be forwarded to all the ports in the VLAN(s)
of the source port except the source port itself.

Mode of Operation

(Register 18)

All ports of the ACD82112 can work in half duplex mode
or full duplex mode. If auto-negotiation is enabled, the
mode is determined by the PHY device. Otherwise, the
mode is assigned by the Full Duplex mode indication/
assignment register.

Spanning Tree Support

The ACD82112 supports the Spanning Tree protocol.
When Spanning Tree Support is enabled

(Register-16

bit 1, see Table 7.15), frames from the CPU port (port
11) having a DA value equal to the reserved Bridge
Management Group Address for BPDU will be forwarded
to the port specified by the CPU. Frames from all other
ports with a DA value equal to the Reserved Group Ad-
dress for BPDU will be forwarded to the CPU port if the
port is in the same VLAN of the CPU port. Port 11 is
designed as the default CPU port. When Spanning Tree
Support is disabled, all reserved group addresses for
Bridge Management is treated as broadcast address,
with the exception of the reserved multicast addresses
for pause frame specified by IEEE802.3x.

Every port of the ACD82112 can be set to block-and-
listen mode through the CPU interface. In this mode,
incoming frames with a DA value equal to the reserved
Group Address for BPDU will be forwarded to the CPU
port. Incoming frames with all other DA values will be
dropped. Outgoing frames with a DA value equal to the
Group Address for BPDU will be forwarded to the at-
tached PHY device; all other outgoing frames will be
filtered.

Queue Management

Each port of the ACD82112 has its own individual trans-
mission queue. All frames coming into the ACD82112
are stored into the shared memory buffer, and are lined
up in the transmission queues of the corresponding
destination port. The order of all frames, unicast or
broadcast, is strictly enforced by the ACD82112. The
ACD82112 is designed with a non-blocking switching
architecture. It is capable of achieving wire speed for-
warding rates and can handle maximum traffic loads.

MII Interface

The MAC of each port of the ACD82112 interfaces with
the port's PHY device through the standard MII inter-
face. For reception, the received data (RXD) is sampled
by the rising edge of the receive clock (RXCLK). As-
sertion of the receive data valid (RXDV) signal will cause
the MAC to look for the start of SFD. For transmission,
the transmit data enable (TXEN) signal is asserted when
the first preamble nibble is sent on the transmit data
(TXD) lines. The transmit data are clocked out by the
falling edge of the transmit clock (TXCLK).

PHY Management

The ACD82112 supports PHY device management
through the serial MDIO and MDC signal lines. The
ACD82112 can continuously poll the status of the PHY
devices through the serial management interface, with-
out CPU intervention. The ACD82112 will also config-
ure the PHY capability field to ensure proper operation
of the link. The ACD82112 also enables the CPU to
access any registers in the PHY devices through the
CPU interface. The ID of the PHY device can start from
either "1" or "4", depending on the setting of bit-10 of
register-25.

Reversed MII Interface

Five of the ACD82112's 12 ports can be configured
with reversed MII interface. Reversed MII behaves as a
PHY MII: the TXCLK, COL, RXD<3:0>, RXCLK, RXDV,
CRS signals (names specified by IEEE 802.3u) be-
come output signals of the ACD82112, and the TXER,
TXD<3:0>, TXEN, RXER signals (names specified by
IEEE 802.3u) become input signals of the ACD82112.
The Reversed MII interface enables an external MAC
device to be connected directly with the ACD82112.

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Data Sheet: ACD821

INTRODUCT

SRAM Interface

The ACD82112 requires the use of ASRAM, or Flow-
through SSRAM as a memory buffer. Each read or write
cycle takes up to 20 ns. For ASRAM, the access time
should be at or less than 12 ns. For SSRAM, the speed
should be at or higher than 100MHz. The SRAM inter-
face contains a 52-bit data bus, a 17-bit address bus
and 4 chip-select signals.

CPU Interface

The ACD82112 does not require any microprocessor
for operation. Initialization and most configurations can
be done with the pull-up or pull-down of designated hard-
ware pins. A CPU interface is provided for a micropro-
cessor to access the control registers and status regis-
ters. The microprocessor can send a read command to
retrieve the status of the switch, or send a write com-
mand to configure the switch through the interface. The
interface is a commonly used UART type interface. The
CPU interface can also be used to access the registers
inside each PHY device connected with the ACD82112.

ARL Interface

The ACD82112 has a built-in MAC address storage for
up to 2,048 source addresses. If more than 2,048 ad-
dresses are needed, an external ARL (e.g. ACD80800)
can be used to expand the address space to 11K en-
tries.

The external ARL is connected through the ARL inter-
face

(Table-7.24, bit-9). It can tap the value of DA out

of the memory interface bus, and execute a lookup pro-
cess to map the value of the DA into a port number. It
can also learn the SA values embedded in the received
frames. The value of SA is used to build the address
lookup table inside the ACD80800.

MIB Interface

Traffic activities on all ports of the ACD82112 can be
monitored through the MIB interface. Through the MIB
interface, a MIB device can view the frames transmitted
from or received by any port. Therefore, the MIB de-
vice can maintain a record of traffic statistics for each
port to support network management. Since all received
data are stored into the memory buffer, and all transmit-
ted data are retrieved from the memory buffer, the data
of the activities can also be captured from the memory
interface data bus. The status of each data transaction
between the ACD82112 and the SRAM is displayed by
dedicated status signal pins of the ACD82112.

LED Interface

The ACD82112 provides a wide variety of LED indica-
tors for simple system management. The update of the
LED is completely autonomous and merely requires low
speed TTL or CMOS devices as LED drivers. The sta-
tus display is designed to be flexible to allow the system
designer to choose those indicators appropriate for the
specification of the equipment.

There are two LED control signals, LEDVLD0 and
LEDVLD1. They are used to indicate the start and end
of the LED data signal presented on nLED0-nLED3.
The LEDCLK signal is a 2.5MHz clock signal. The ris-
ing edge of LEDCLK should be used to latch the LED
data signal into the LED driver circuitry.

The LED data signals contain Lnk, Xmt, Rcv, Col, Err,
Fdx and Spd, which represent Link status, Transmit sta-
tus, Receive status, Collision indication, Frame error
indication, Full duplex operation and Operational Speed
status respectively. These status signals are sent out
sequentially from port 11 to port 0, once every 50ms.
For details about the timing diagrams of the LED sig-
nals, refer to the chapter of "Timing Description "

Life Pulse

The ACD82112 continuously sends out life pulses to
the WCHDOG pin when it is operating properly. In a
catastrophic event, the ACD82112 will not send the life
pulse to cause the external watchdog circuitry to time-
out and reset the switch system.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

6. INTERFACE DESCRIPTION

MII Interface (MII)

The ACD82112 communicates with the external 10/100
Ethernet transceivers through standard MII interface.
The signals of MII interface are described in

Table-6.1:

For MII interface, signal PxRXDV, PxRXER and PxRXD0
through PxRXD3 are sampled by the rising edge of
PxRXCLK. Signal PxTXEN, and PxTXD0 through
PxTXD3 are clocked out by the falling edge of PxTXCLK.
The detailed timing requirement is described in the chap-
ter of "Timing Description"

Ports 0, 1, 2, 3 and 11 can be configured as reversed
MII ports (

ter). These ports, when configured as "normal" MII, have
the same characteristics as all other MII ports. How-
ever, when configured as reversed MII interface, they
will behave logically like a PHY device, and can inter-
face directly with a MAC device. The signal of reversed
MII interface are described by

Table-6.2:

*Collision Indication for half-duplex, Receive-Not-Ready for full
duplex only.

For reversed MII interface, signal PxRXDVR, and
PxRXD0R through PxRXD3R are clocked out by the
falling edge of PxRXCLKR. Signal PxTXENR, and
PxTXD0R through PxTXD3R can be sampled by the
falling edge or rising edge of PxTXCLKR, depends on
the setting of bit 9 of

is described in the chapter of "Timing Description."

PHY Management Interface

All control and status registers of the PHY devices are
accessible through the PHY management interface. The
interface consists of two signals: MDC and MDIO, which
are described in

table-6.3.

Frames transmitted on MDIO has the following format
(

Table-6.4):

Table-6.1: MII Interface Signals

Name

Type

Description

PxCRS

Carrier sense

PxRXDV

Receive data valid

PxRXCLK

Receive clock (25/2.5 MHz)

PxRXERR

Receive error

PxRXD0

Receive data bit 0

PxRXD1

Receive data bit 1

PxRXD2

Receive data bit 2

PxRXD3

Receive data bit 3

PxCOL

Collision indication

PxTXEN

Transmit data valid

PxTXCLK

Transmit clock (25/2.5 MHz)

PxTXD0

Transmit data bit 0

PxTXD1

Transmit data bit 1

PxTXD2

Transmit data bit 2

PxTXD3

Transmit data bit 3

Table-6.2: Reversed MII Interface Signals

Name

Type

Description

PxCRSR

Carrier sense

PxRXDVR

Transmit data valid

PxRXCLKR

Transmit clock (25/2.5 MHz)

PxRXERR

Transmit-Not-Ready

PxRXD0R

Transmit data bit 0

PxRXD1R

Transmit data bit 1

PxRXD2R

Transmit data bit 2

PxRXD3R

Transmit data bit 3

PxCOLR*

Collision Indication/

Receive-Not-Ready*

PxTXENR

Receive data valid

PxTXCLKR

Receive clock (25/2.5 MHz)

PxTXD0R

Receive data bit 0

PxTXD1R

Receive data bit 1

PxTXD2R

Receive data bit 2

PxTXD3R

Receive data bit 3

Table-6.3: PHY Management Interface Signals

Name

Type

Description

MDC

PHY management clock (1.25MHz)

MDIO

I/O

PHY management data

Table-6.4: MDIO Format

Operation

PRE

PHY-ID

REG-AD

DATA

IDLE

Write

1...1

aaaaa

rrrrr

d...d

Read

1...1

aaaaa

rrrrr

d...d

Prior to any transaction, the ACD82112 will output thirty-
two bits of `1' as preamble signal. After the preamble, a
01 signal is used to indicate the start of the frame.

For a write operation, the device will send a `01' to sig-
nal a write operation. Following the `01' write signal will
be the 5 bit ID address of the PHY device and the 5 bit
register address. A `10' turn around signal is then fol-
lowed. After the turn around, the 16 bit of data will be
written into the register. After the completion of the write
transaction, the line will be left in a high impedance
state.

For a read operation, the ACD82112 will output a `10' to
indicate read operation after the start of frame indica-
tor. Following the `10' read signal will be the 5-bit ID
address of the PHY device and the 5-bit register ad-
dress. Then, the ACD82112 will cease driving the MDIO
line, and wait for one bit time. During this time, the
MDIO should be in a high impedance state. The
ACD82112 will then synchronize with the next bit of `0"
driven by the PHY device, and continue on to read 16
bits of data from the PHY device.

The system designer can set the ID of the PHY devices
as 1 for port 0, 2 for port 1, ... and 12 for port 11, when
the PHYID option (Bit-10 of Register-25) is set to "0". If
the PHYID option is set to "1", the corresponding PHY
ID should set to 4 through 15. The detailed timing re-
quirements on PHY management signals are described
in the chapter of "Timing Description."

CPU Interface

The ACD82112 includes a CPU interface to enable an
external CPU to access the internal registers of the
ACD82112. The signal used in the CPU is UART. The
baud rate can be from 1200 bps to 76800 bps. The
ACD82112 automatically detects the baud rate for each
command, and returns the result at the same baud rate.
The signals in CPU interface are described in

Table-

6.5.

A command sent by CPU comes through the CPUDI
line. The command consists of 8 octets. Command
frames transmitted on CPUDI have the following format
(

Table-6.6):

The byte order of data in all fields follows the big-endian
convention, i.e. most significant octet first. The bit or-
der is the least significant order first. The Command
octet specifies the type of the operation. Bit 2 and bit 3
of the command octet is used to specify the device ID
of the chip. They are set by bit 16 and bit 17 of the
Register 25 at power on strobing. The address octet
specifies the type of the register. The index octet speci-
fies the index of the register in a register array. For
write operation, the Data field is a 3-octet value to specify
what to write into the register. For read operation, the
Data field is a 3-octet 0 as padded data. The checksum
value is an 8-bit value of exclusive-OR of all octets in the
frame, starting from the Command octet.

For each valid command heading to it, the ACD82112
will always send a response. Response from the
ACD82112 is sent through the CPUDO line. Response
frames sent by the ACD82112 has the following format
(

Table-6.7):

The command octet specifies the type of the response.
The result octet specifies the result of the execution.

The Result field in a response frame is defined as:

�

00 for no error

�

01 for Checksum

�

10 for address incorrect

�

11 for MDIO waiting timeout

For response to a read operation, the Data field is a 4-
octet value to indicate the content of the register. For
response to a write operation, the Data field is 32 bits of
0. The checksum value is an 8-bit value of exclusive-OR
of all octets in the response frame, starting from the
Command octet.

Table-6.5: CPU Interface Signals

Name

Type

Description

CPUDI

CPU data input

CPUDO

CPU data output

CPUIRQ

CPU interrupt request

Table-6.6: CPUDI Format

Operation

Command

Address

Index

Data

Checksum

Write

0010XX11

8-bit

24-bit

8-bit

Read

0010XX01

8-bit

24-bit

8-bit

Table-6.7: Switch Response Format

Response

Command

Result

Data

Checksum

Write

00100011

8-bit

24-bit

8-bit

Read

00100001

8-bit

24-bit

8-bit

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Data Sheet: ACD821

INTRODUCT

CPUIRQ is used to notify the CPU that some special
status has been encountered by the ACD82112, like
port partition, fatal system error, etc. By clearing the
appropriate bit in the interrupt mask register, one can
stop the specific source from generating an interrupt
request. Reading the interrupt source register retrieves
the source of the interrupt request and clears the inter-
rupt source register.

SRAM Interface

All received frames are stored into the shared memory
buffer through the SRAM interface. When the destina-
tion port is ready to transmit the frame, data is read
from the shared memory buffer through the SRAM in-
terface. The signals in SRAM interface are described
in

Table-6.8.

Data is written into the SRAM or read from the SRAM in
52-bit wide words. The data is a 48 bit wide value and
the control is a 4 bit wide value. ADDR specifies the
address of the word, and DATA contains the content of
the word. Bit 0 ~ 47 of DATA bus are used to pass 48-
bit frame data. Bit 48 are used to indicate the start and
end of a frame. Bit 49~51 are used to indicate the length
of the data shown on first 48 bit of DATA bus.

nOE and nWE are used to control the timing of read or
write operation respectively. nCSx selects the SRAM
chip corresponding to the word address. The timing
requirement on SRAM access is described in "Timing
Description" (Chapter-9).

ARL Interface

The ARL interface provides a communication path be-
tween the ACD82112 and an ARL device, which can
provide up to 11K of address lookup. As the ACD82112
receives a frame, the destination address and source
address of the frame are displayed on the ARLDO data
lines for the external ARL device. After the external ARL
finds the corresponding destination port, it returns the
result through the ARLDIx lines to the ACD82112. The
timing requirement on ARL signals is described in Chap-
ter 9, "Timing Description."

Table-6.9 shows the asso-

ciated signals in ARL interface.

The data signal is tapped from the DATA bus of the
SRAM interface. Since all data of the received frames
will be written into the shared memory through the DATA
bus, the bus can be used to monitor occurrences of DA
and SA values, indicated by the status signal of ARLSTAT.
Therefore, ARLD0 through ARLD51 are the same sig-
nals of DATA0 through DATA51.

The ARLDIR1 and ARLDIR0 are used to indicate the
direction of data on the ARLDO bus:

�

00: Idle

�

01: For receiving data

�

10: For transmitting data

�

11: Header

The ARLSYNC is used to indicate port 0 is driving the
DATA bus. Since the bus is pre-allocated in time divi-
sion multiplexing manner, the ARL device can deter-
mine which port is driving the DATA bus.

The ARLSTAT are used to indicate the status of the
data shown on the first 48 bit of DATA bus. The 4-bit
status is defined as:

�

0000 - Idle

�

0001 - First word (DA)

�

0010 - Second word (SA)

�

0011 - Third through last word

�

0100 - Filter Event

�

0101 - Drop Event

�

0110 - Jabber

�

0111 - False Carrier/Deferred Transmission*

�

1000 - Alignment error/Single Collision*

�

1001 - Flow Control/Multiple Collision*

�

1010 - Short Event/Excessive Collision*

�

1011 - Runt/Late Collision*

�

1100 - Symbol Error

�

1101 - FCS Error

Table-6.8: SRAM Interface

Name

Type

Description

DATA0 - DATA51

I/O

memory data bus

ADDR0 - ADDR16

memory address bus

nOE

output enable, low active

nWE

write enable, low active

nCS0 - nCS3

chip select signals, low active.

Table-6.9: ARL Interface Signals

Name

Type

Description

ARLDO0-RLDO51

ARL data output, shared with

DATA 0 - DATA 51

ARLDIR1-ARLDIR0

ARL data direction indicator

00 for idle

01 for receive

10 for transmit

11 for control

ARLSYNC

ARL port synchronization

ARLSTAT0-

ARLSTAT3

ARL data state indicator

ARLCLK

ARL clock

ARLDI0 - ARLDI3

ARL data input

ARLDIV

ARL input data valid

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Data Sheet: ACD821

INTRODUCT

�

1110 - Long Event

�

1111 - Reserved

*Note: error type depends on the port is receiving or
transmitting.

ARLDIx is used to receive the lookup result from the
external ARL. The result is returned by external ARL
device through the ARLDIx lines. Returned data can be
sampled by the rising or the falling edges of ARLCLK,
depending on the setting of Bit-18 of Register-25. The
ARL results have the following format:

Where

�

SID is a 5-bit ID of the source port (0 - 11)

�

RSLT is a 2-bit result, defined as:

00 - reserved
01 - matched
10 - not matched
11 - forced discard

�

DID is a 5-bit ID of the destination port (0 - 11)

The start of each ARL result is indicated by assertion of
ARLDIV signal.

LED Interface

The signals in the LED interface is described in

Table-

6.10:

The status of each port is displayed on the LED inter-
face for every 50ms. LEDVLD0 and LEDVLD1 are used
to indicate the start and end of the LED data. LED data
is clocked out by the falling edge of LEDCLK, and should
be sampled by the rising edge of LEDCLK. LED data of
port-11 are clocked out first, followed by port-10 down
to port-0. All LED signals are low active.

SID

RSLT

DID

Table-6.10: LED Interface Signals

Name

Type

Description

Signal Group 1

Signal Group 2

LEDVLD0

LED signal valid #0

LEDVLD1

LED signal valid #1

nLEDCLK

2.5 MHz LED clock

nLED0

Dual purpose indicator

address learning status

frame error indicator

nLED1

Dual purpose indicator

full duplex indication

collision indication

nLED2

Dual purpose indicator

port speed (1=10Mbps,0=100Mbps)

receiving activity

nLED3

Dual purpose indicator

Link status

transmit activity

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Data Sheet: ACD821

INTRODUCT

Table-6.12: Other Interface

Name

Type

Description

CLK50

50 MHz clock input

nRESET

hardware reset

WCHDOG

watch dog life pulse signal

VDD

3.3 V power

VSS

ground

Configuration Interface

The default values of certain register bits are set by
internal pull-high/pull-low with 75K Ohm resistors. These
default values can be overwritten by external pull-high/
pull-low of certain designated pins with 4.7K Ohm exter-
nal resistors.

Table-6.11 lists all the available pins. The

meanings of the register bits are described in the chap-
ter of "Register Description."

Other Interface (

Table-6.12)

The CLK50 should come from a clock oscillator, with
0.01% (100 ppm) accuracy.

The nRESET is a low-active hardware reset pin. Asser-
tion of this pin will cause the ACD82112 to go through
the power-up initialization process. All registers are set
to their default value after reset.

The WCHDOG pin is used to handle exceptional cases.
A normal working ACD82112 sends out continuous life
pulses from the WCHDOG pin, which can be monitored
by an external watchdog circuit. If no life pulse is de-
tected , the external watchdog circuit may force reset
of the switch system. It is a safeguard against unfore-
seeable situations.

The VDD is 3.3V power supply.

The VSS is power ground.

Table-6.11: Configuration Interface

Pin Name

Register #

Bit #

Default

P7TXD0

P7TXD1

P7TXD2

P7TXD3

P6TXD0

P6TXD1

P6TXD2

P6TXD3

LEDCLK

LEDVLD0

LEDVLD1

nLED3

nLED2

nLED1

nLED0

P5TXD0

P5TXD1

P5TXD2

P5TXD3

P0TXD0

P0TXD1

P0TXD2

P0TXD3

P1TXD0

P1TXD1

P1TXD2

P1TXD3

P2TXD3

P2TXD2

20, inside the

Internal ARL

See Table-7.25

See Table-7.30

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Data Sheet: ACD821

INTRODUCT

7. REGISTER DESCRIPTION

Registers in the ACD82112 are used to define the op-
eration mode of various function modules of the switch
controller and the peripheral devices. Default values at
power-on are defined by the factory. The management
CPU (optional) can read the content of all registers and
modify some of the registers to change the operation
mode. Table-7.0 lists all the registers inside the switch
controller.

INTSRC register (register 1)

The INTSRC register indicates the source of the inter-
rupt request. Before the CPU starts to respond to an
interrupt request, it should read this register to find out
the interrupt source. This register is automatically cleared
after each read. Table-7.1 lists all the bits of this regis-
ter.

SYSERR register (register 2)

The SYSERR register indicates the presence of sys-
tem errors. It is automatically cleared after each read.
Table-7.2 lists all kind of system error.

Table-7.0: Register List

Address

Name

Type

Size

Depth

Description

Reserved

INTSRC

8 Bit

Interrupt Source

SYSERR

12 Bit

System Error

PAR

12 Bit

Port Partition Indication

PMERR

12 Bit

PHY Management Error

ACT

12 Bit

Port Avtivity

Reserved

SAL

R/W

24 Bit

Source Address, bit 23:0

SAH

R/W

24 Bit

Source Address, bit 47:24

UTH

R/W

16 Bit

Unicast Threshold

BTH

R/W

16 Bit

Broadcast Threshold

MAXL

R/W

16 Bit

FCS of Max-Pause-Frame, bit 15:0

MAXH

R/W

16 Bit

FCS of Max-Pause-Frame, bit 31:16

MINL

R/W

16 Bit

FCS of Min-Pause-Frame, bit 15:0

MINH

R/W

16 Bit

FCS of Min-Pause-Frame, bit 31:16

SYSCFG

R/W

16 Bit

System Configuration

INTMSK

R/W

8 Bit

Interrupt Mask

SPEED

R/W

12 Bit

Port Speed

LINK

R/W

12 Bit

Port Link

nFWD

R/W

12 Bit

Port Forward Disable

nBP

R/W

12 Bit

Port Back Pressure Disable

nPORT

R/W

12 Bit

Port Disable

PVID

R/W

4 Bit

Port VLAN ID

VPID

R/W

5 Bit

VLAN Dumping Port

POSCFG

R/W

20 Bit

Power-On-Strobe Configuration

PAUSE

R/W

12 Bit

Port Pause Frame Disable

DPLX

R/W

12 Bit

Port Duplex Mode

RVSMII

R/W

5 Bit

Reversed MII Selection

nPM

R/W

12 Bit

Port PHY Management Disable

ERRMSK

R/W

8 Bit

Error Mask

CLKADJ

R/W

4 Bit

ARL Clock Delay Adjustment

32-43

PHYREG

R/W

16 Bit

Pointer to Registers in PHY devices

44-63

Reserved

R/W

Table-7.1: INTSRC Register

Bit

Description

Default

System initialization completed

System error occurred

Port partition occurred

ARL Interrupt

4
5
6
7

Reserved

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Data Sheet: ACD821

INTRODUCT

PAR register (register 3)

The PAR register indicates the presence of the parti-
tioned ports and the port ID. A port can be automati-
cally partitioned if there is a consecutive false carrier
event, an excessive collision or a jabber. This register is
automatically cleared after each read. Table-7.3 lists all
the bits of this register.

Table-7.2: SYSERR Register

Bit

Description

Default

BIST failure indication

1
2
3
4
5
6
7
8

Reserved

Table-7.3: PAR Register

Bit

Description

Default

0 - Port 0 is not partitioned.
1 - Port 0 is partitioned.

0 - Port 1 is not partitioned.
1 - Port 1 is partitioned.

0 - Port 2 is not partitioned.
1 - Port 2 is partitioned.

0 - Port 3 is not partitioned.
1 - Port 3 is partitioned.

0 - Port 4 is not partitioned.
1 - Port 4 is partitioned.

0 - Port 5 is not partitioned.
1 - Port 5 is partitioned.

0 - Port 6 is not partitioned.
1 - Port 6 is partitioned.

0 - Port 7 is not partitioned.
1 - Port 7 is partitioned.

0 - Port 8 is not partitioned.
1 - Port 8 is partitioned.

0 - Port 9 is not partitioned.
1 - Port 9 is partitioned.

0 - Port 10 is not partitioned.
1 - Port 10 is partitioned.

0 - Port 11 is not partitioned.
1 - Port 11 is partitioned.

PMERR register (register 4)

The PMERR register indicates the presence of PHYs
that have failed to respond to the PHY Management
command issued through the MDIO line. This register
is automatically cleared after each read. Table-7.4 de-
scribes all the bit of this register.

ACT register (register 5)

The ACT register indicates the presence of transmit or
receive activities of each port since the register was
last read. This register is automatically cleared after
each read. Table-7.5 describes all the bits of this regis-
ter.

Table-7.4: PMERR Register

Bit

Description

Default

0 - Port 0's PHY responded
1 - Port 0's PHY failed to respond

0 - Port 1's PHY responded
1 - Port 1's PHY failed to respond

0 - Port 2's PHY responded
1 - Port 2's PHY failed to respond

0 - Port 3's PHY responded
1 - Port 3's PHY failed to respond

0 - Port 4's PHY responded
1 - Port 4's PHY failed to respond

0 - Port 5's PHY responded
1 - Port 5's PHY failed to respond

0 - Port 6's PHY responded
1 - Port 6's PHY failed to respond

0 - Port 7's PHY responded
1 - Port 7's PHY failed to respond

0 - Port 8's PHY responded
1 - Port 8's PHY failed to respond

0 - Port 9's PHY responded
1 - Port 9's PHY failed to respond

0 - Port 10's PHY responded
1 - Port 10's PHY failed to respond

0 - Port 11's PHY responded
1 - Port 11's PHY failed to respond

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Data Sheet: ACD821

INTRODUCT

SAL & SAH register (register 8,9)

The SAL and SAH registers together contain the com-
plete Source Address for pause frame generation. SAL
contains the least significant 24 bit of the MAC address.
SAH contains the most significant 24 bit of the MAC
address. The default locally managed source address
for pause frame generation is FEh-FFh-FFh-FFh-FFh-
FFh a. Table-7.8 and table-7.9 describes all the bits of
these two registers.

UTH register (register 10)

The UTH register contains the unicast buffer thresholds
for each port. When the upper threshold is exceeded,
the MAC may generate a max-pause-frame. When the

lower threshold is crossed, the MAC may generate a
mini-pause-frame. Table-7.10 describes each bit in this
register.

Note: The default value is related to the memory size

specified by bit[6:5] of register 25.

BTH register (register 11)

The BTH register contains the broadcast queue buffer
threshold for each port. When the upper threshold is
exceeded, the MAC may generate a max-pause-frame.
When the lower threshold is crossed, the MAC may
generate a mini-pause-frame. Table-7.11 describes each
bit in this register.

MINL & MINH register (register 12,13)

The MINL and MINH registers together contain the 32-
bit Frame Check Sequence (FCS) of the mini-pause-
frame. MINL contains the least significant 16 bit of the
FCS. MINH contains the most significant 16 bit of the
FCS. The default FCS value assumes the default source
address for the mini-pause-frame. Table-7.12 and table-
7.13 describe all the bits of these two registers.

Table-7.8: SAL Register

Bit

Description

Default

7:0

Bit 47:40 of the switch's MAC address.

FEh

15:8

Bit 39:32 of the switch's MAC address.

23:16

Bit 31:24 of the switch's MAC address.

FFh

Table-7.9: SAH Register

Bit

Description

Default

7:0

Bit 23:16 of the switch's MAC address.

15:8

Bit 15:8 of the switch's MAC address.

23:16

Bit 7:0 of the switch's MAC address.

FFh

Table-7.10: UTH Register

Bit

Description

Default*

7:0

Lower threshold of unicast utilization.

4,8,16,32

15:8 Higher threshold of unicast utilization. 8,24,64,144

Table-7.5: ACT register

Bit

Description

Default

0 - Port 0 no activity
1 - Port 0 has activity

0 - Port 1 no activity
1 - Port 1 has activity

0 - Port 2 no activity
1 - Port 2 has activity

0 - Port 3 no activity
1 - Port 3 has activity

0 - Port 4 no activity
1 - Port 4 has activity

0 - Port 5 no activity
1 - Port 5 has activity

0 - Port 6 no activity
1 - Port 6 has activity

0 - Port 7 no activity
1 - Port 7 has activity

0 - Port 8 no activity
1 - Port 8 has activity

0 - Port 9 no activity
1 - Port 9 has activity

0 - Port 10 no activity
1 - Port 10 has activity

0 - Port 11 no activity
1 - Port 11 has activity

Table-7.11: BTH Register

Bit

Description

Default

7:0

Lower threshold of broadcast queue

15:8

Higher threshold of broadcast queue

Table-7.12: MINL Register

Bit

Description

Default

7:0

Bit 31:24 of the mini-pause-frame's FCS

15:8

Bit 23:16 of the mini-pause-frame's FCS

Table-7.13: MINH Register

Bit

Description

Default

7:0

Bit 15:18 of the mini-pause-frame's FCS

15:8

Bit 7:0 of the mini-pause-frame's FCS

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

MAXL & MAXH register (register 14,15)

The MAXL and MAXH registers together contain the
32-bit Frame Check Sequence (FCS) of the max-pause-
frame. MAXL contains the least significant 16 bit of the
FCS. MAXH contains the most significant 16 bit of the
FCS. The default FCS value assumes the default source
address for the max-pause-frame. Table-7.14 and table-
7.15 describe all the bits of these two registers.

SYSCFG register (register 16)

The SYSCFG register specifies certain system con-
figurations. The system options are described in the
chapter of "Function Description." Table-7.16 describes
all the bit of this register.

INTMSK register (register 17)

The INTMSK register defines the valid interrupt sources
allowed to assert interrupt request pin. Table-7.17 lists
all the bits of this register.

Table-7.17: INTMSK Register

Bit

Description

Default

Enable "system initialization
completion" to interrupt

Enable "internal system error"
to interrupt

Enable "port partition event"
to interrupt

Enable "Internal ARL" to interrupt

ARL Interupt Enable

5
6
7

Reserved

Table-7.16: SYSCFG Register

Bit

Description

Default

0 - BIST enabled;
1 - BIST disabled.

0 - Spanning Tree support disabled;
1 - Spanning Tree support enabled

0 - rising edge of RXCLK to latch RXD for MII
1 - falling edge of RXCLK to latch RXD for MII

Reserved.

0 - wait for CPU.
1 - system ready to start
*This bit is used by the CPU when bit-15 of
register-25 is set as "0" (for system with
control CPU). The system will wait for CPU
to set this bit.

0 - PHY Management not completed
1 - PHY Management completed.
*This bit is used by the CPU when bit-15 of
register-25 is set as "0" (for system with a
control CPU). The MAC will not start until this
bit is set sy the CPU.

0 - Watchdog function enabled.
1 - Watchdog function disabled.

0 - Secure VLAN checking rule enforced.
1 - Leaky VLAN checking rule enforced.

0 - Rising edge of RXCLK to latch data.
1 - Falling edge of RXCLK to latch data.
*For Reversed MII port only.

0 - Late Back-Pressure scheme disabled
1 - Late Back-Pressure scheme enabled
*When enabled, the MAC will generate back-
pressure only after reading the first bit of DA

0 - special handling of broadcast frames
disabled
1 - special handling of broadcast frames
enabled
*When enabled, all broadcast frames from
non-CPU port are forwarded to the CPU port
only, and all broadcast frames from the CPU
port are forwarded to all other ports.

Software Reset: "1" to start a system reset to
innitialize all state machines.

Hardware Reset: "1" to stop the life pulse on
the watchdog pin, which in turn will trigger the
external watchdog circuitry to reset the whole
system.

Reserved

Table-7.14: MAXL Register

Bit

Description

Default

7:0

Bit 31:24 of the max-pause-frame's FCS

15:8

Bit 23:16 of the max-pause-frame's FCS

Table-7.15: MAXH Register

Bit

Description

Default

7:0

Bit 15:8 of the max-pause-frame's FCS

15:8

Bit 7:0 of the max-pause-frame's FCS

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

SPEED register (register 18)

The SPEED register specifies or indicates the speed
rate of each port. It is read-only, unless the bit-12 of
register-25 is set (through POS to disable automatic
PHY management). At read-only mode, it indicates the
speed achieved through PHY management. At the write-
able mode, the control CPU will be able to assign speed
rate for each port. Table-7.18 describes all the bit of
this register.

LINK register (register 19)

The LINK register specifies or indicates the link status
of each port. It is read-only, unless bit-12 of register-25
is set (through POS, to disable automatic PHY man-
agement). At read-only mode, it indicates the result
achieved by PHY management. At write-able mode, the
control CPU can assign link status for each port. Table-
7.19 describes all the bit of this register.

nFWD register (register 20)

The nFWD register defines the forwarding mode of each
port. Under

forwarding mode, a port can forward all

frames. Under

block-and-listen mode, a port will not

forward regular frames, except BPDU frames. If the

spanning tree algorithm discovers redundant links, the
control CPU will allow only one link remaining in

for-

warding mode and force all other links into block-and-
listen mode. Setting the associated bit in this register
will put the port into

block-and-listen mode. Table-7.20

Table-7.18: SPEED Register

Bit

Description

Default

0 - Port 0 at 10Mbps
1 - Port 0 at 100Mbps

0 - Port 1 at 10Mbps
1 - Port 1 at 100Mbps

0 - Port 2 at 10Mbps
1 - Port 2 at 100Mbps

0 - Port 3 at 10Mbps
1 - Port 3 at 100Mbps

0 - Port 4 at 10Mbps
1 - Port 4 at 100Mbps

0 - Port 5 at 10Mbps
1 - Port 5 at 100Mbps

0 - Port 6 at 10Mbps
1 - Port 6 at 100Mbps

0 - Port 7 at 10Mbps
1 - Port 7 at 100Mbps

0 - Port 8 at 10Mbps
1 - Port 8 at 100Mbps

0 - Port 9 at 10Mbps
1 - Port 9 at 100Mbps

0 - Port 10 at 10Mbps
1 - Port 10 at 100Mbps

0 - Port 11 at 10Mbps
1 - Port 11 at 100Mbps

Table-7.19: LINK Register

Bit

Description

Default

0 - Port 0 link not established
1 - Port 0 link established

0 - Port 1 link not established
1 - Port 1 link established

0 - Port 2 link not established
1 - Port 2 link established

0 - Port 3 link not established
1 - Port 3 link established

0 - Port 4 link not established
1 - Port 4 link established

0 - Port 5 link not established
1 - Port 5 link established

0 - Port 6 link not established
1 - Port 6 link established

0 - Port 7 link not established
1 - Port 7 link established

0 - Port 8 link not established
1 - Port 8 link established

0 - Port 9 link not established
1 - Port 9 link established

0 - Port 10 link not established
1 - Port 10 link established

0 - Port 11 link not established
1 - Port 11 link established

Table-7.20: nFWD Register

Bit

Description

Default

0 - Port 0 in forwarding state.
1 - Port 0 in block-and-listen state.

0 - Port 1 in forwarding state.
1 - Port 1 in block-and-listen state.

0 - Port 2 in forwarding state.
1 - Port 2 in block-and-listen state.

0 - Port 3 in forwarding state.
1 - Port 3 in block-and-listen state.

0 - Port 4 in forwarding state.
1 - Port 4 in block-and-listen state.

0 - Port 5 in forwarding state.
1 - Port 5 in block-and-listen state.

0 - Port 6 in forwarding state.
1 - Port 6 in block-and-listen state.

0 - Port 7 in forwarding state.
1 - Port 7 in block-and-listen state.

0 - Port 8 in forwarding state.
1 - Port 8 in block-and-listen state.

0 - Port 9 in forwarding state.
1 - Port 9 in block-and-listen state.

0 - Port 10 in forwarding state.
1 - Port 10 in block-and-listen state.

0 - Port 11 in forwarding state.
1 - Port 11 in block-and-listen state.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

describes all the bit of this register.

nBP register (register 21)

The nBP register defines back-pressure flow control
capability for each port. Table-7.21 describes all the bit
of this register.

nPORT register (register 22)

The nPORT register is used to isolate ports from the
network. Setting the associated bit in this register will
stop a port from receiving or transmitting any frame.
Table-7.22 describes all the bits of this register.

PVID register (register 23)

The PVID registers assign VLAN IDs for each port.
There are 12 PVID registers, one for each port. A PVID
consists of 4 bits, each corresponding to one of the 4
VLANs. A port can belong to more than one VLAN at
the same time. Table-7.23 describes all the bits of this
register.

VPID register (register 24)

The VPID registers specify the dumping port for each
VLAN. There are 4 VPID 5-bit registers, one for each
VLAN. A valid VPID are "0" through "11" (other values
are reserved and should not used). Table-7.24 describes
all the bits of this register.

Table-7.21: nBP Register

Bit

Description

Default

0 - Port 0 back-pressure scheme enabled
1 - Port 0 back pressure scheme disabled

0 - Port 1 back-pressure scheme enabled
1 - Port 1 back pressure scheme disabled

0 - Port 2 back-pressure scheme enabled
1 - Port 2 back pressure scheme disabled

0 - Port 3 back-pressure scheme enabled
1 - Port 3 back pressure scheme disabled

0 - Port 4 back-pressure scheme enabled
1 - Port 4 back pressure scheme disabled

0 - Port 5 back-pressure scheme enabled
1 - Port 5 back pressure scheme disabled

0 - Port 6 back-pressure scheme enabled
1 - Port 6 back pressure scheme disabled

0 - Port 7 back-pressure scheme enabled
1 - Port 7 back pressure scheme disabled

0 - Port 8 back-pressure scheme enabled
1 - Port 8 back pressure scheme disabled

0 - Port 9 back-pressure scheme enabled
1 - Port 9 back pressure scheme disabled

0 - Port 10 back-pressure scheme enabled
1 - Port 10 back pressure scheme disabled

0 - Port 11 back-pressure scheme enabled
1 - Port 11 back pressure scheme disabled

Table-7.22: nPORT Register

Bit

Description

Default

0 - Port 0 enabled
1 - Port 0 disabled

0 - Port 1 enabled
1 - Port 1 disabled

0 - Port 2 enabled
1 - Port 2 disabled

0 - Port 3 enabled
1 - Port 3 disabled

0 - Port 4 enabled
1 - Port 4 disabled

0 - Port 5 enabled
1 - Port 5 disabled

0 - Port 6 enabled
1 - Port 6 disabled

0 - Port 7 enabled
1 - Port 7 disabled

0 - Port 8 enabled
1 - Port 8 disabled

0 - Port 9 enabled
1 - Port 9 disabled

0 - Port 10 enabled
1 - Port 10 disabled

0 - Port 11 enabled
1 - Port 11 disabled

Table-7.23: PVID Register

Bit

Description

Default

0 - port not in VLAN-I.

1 - port in VLAN-I.

0 - port not in VLAN-II.
1 - port in VLAN-II.

0 - port not in VLAN-III.
1 - port in VLAN-III.

0 - port not in VLAN-IV.
1 - port in VLAN-IV.

Table-7.24: VPID Registers (4 registers)

Bit

Description

Default

4:0

Dumping port ID for VLAN-1

"00000"

4:0

Dumping port ID for VLAN-2

"11111"

4:0

Dumping port ID for VLAN-3

dumping port

4:0

Dumping port ID for VLAN-4

not defined

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

POSCFG register (register 25)

The POSCFG register specifies a certain configuration
setting for the switch system. The default values of this
register can be changed through pull-up/pull-down of
specific pins, as described in the "Configuration Inter-
face" section of the "Interface Description" chapter.
Table-7.25 describes all the bit of this register.

Table-7.25: POSCFG Register

Bit

Description

Default

3:0

8 timing adjustment levels for SRAM Read data latching:

0000

0000 - no delay
0001 - level 1 delay
0011 - level 2 delay
0101 - level 3 delay
0111 - level 4 delay
1001 - level 5 delay
1011 - level 6 delay
1101 - level 7 delay
1111 - level 8 delay

0 - Absolute address mode: 1 row of 512K words, nCS2=ADDR17, nCS3=ADDR18

1 - Chip-Select address mode: 4 rows of 128K words, nCS[3:0] to select 4 rows of memory

6:5

SRAM size selection:

00 - 64K words
01 - 128K words
10 - 256k words
11 - 512K words

0 - Long Event defined as frame longer than 1518 byte.

1 - Long Event defined as frame longer than 1530 byte.

0 - Frames with unknown DA forwarded to the dumping port.

1 - Frames with unknown DA forwarded to all ports.

0 - Internal ARL selected (2K MAC address entry).

1 - External ARL selected (11K MAC address entry).

0 - PHY IDs start from 1, range from 1 to 12.

1 - PHY IDs start from 4, range from 4 to 15.

0 - Re-transmit after excessive collision.

1 - Drop after excessive collision.

0 - Automatic PHY Management enabled

1 - Automatic PHY Management disabled: the control CPU need to update the SPEED, LINK, DPLX and
nPAUSE registers

Reserved

0 - Sysem errors will trigger software reset

1 - Sysem errors will trigger hardware reset

0 - System start itself without a control CPU

1 - System start after system-ready bit in register-16 is set by the control CPU

17:16

2-bit device ID for UART communication. The device responses only to UART commands with
matching ID

0 - Rising edge of ARLCLK to latch ARLDI.

1 - Falling edge of ARLCLK to latch ARLDI.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

PAUSE register (register 26)

The PAUSE register defines the pause-frame based
flow control capability of each port. Table-7.26 describes
all the bits of this register.

DPLX register (register 27)

The DPLX register specifies or indicates the half/full-
duplex mode of each port. It is read-only, unless bit-12
of register-25 is set (through POS, to disable automatic
PHY management). At read-only mode, it indicates the
result achieved by the PHY management. At write-able
mode, the control CPU can assign a half-duplex or full-
duplex mode for each port. Table-7.27 describes all the
bits of this register.

RVSMII register (register 28)

The RVSMII register defines the

reversed MII mode for

each port. Table-7.28 describes all the bits of this regis-
ter.

Table-7.26: PAUSE Register

Bit

Description

Default

0 - Port 0 Pause-Frame disabled
1 - Port 0 Pause-Frame enabled

0 - Port 1 Pause-Frame disabled
1 - Port 1 Pause-Frame enabled

0 - Port 2 Pause-Frame disabled
1 - Port 2 Pause-Frame enabled

0 - Port 3 Pause-Frame disabled
1 - Port 3 Pause-Frame enabled

0 - Port 4 Pause-Frame disabled
1 - Port 4 Pause-Frame enabled

0 - Port 5 Pause-Frame disabled
1 - Port 5 Pause-Frame enabled

0 - Port 6 Pause-Frame disabled
1 - Port 6 Pause-Frame enabled

0 - Port 7 Pause-Frame disabled
1 - Port 7 Pause-Frame enabled

0 - Port 8 Pause-Frame disabled
1 - Port 8 Pause-Frame enabled

0 - Port 9 Pause-Frame disabled
1 - Port 9 Pause-Frame enabled

0 - Port 10 Pause-Frame disabled
1 - Port 10 Pause-Frame enabled

0 - Port 11 Pause-Frame disabled
1 - Port 11 Pause-Frame enabled

Table-7.27: DPLX Register

Bit

Description

Default

0 - Port 0 under half duplex mode
1 - Port 0 under full duplex mode

0 - Port 1 under half duplex mode
1 - Port 1 under full duplex mode

0 - Port 2 under half duplex mode
1 - Port 2 under full duplex mode

0 - Port 3 under half duplex mode
1 - Port 3 under full duplex mode

0 - Port 4 under half duplex mode
1 - Port 4 under full duplex mode

0 - Port 5 under half duplex mode
1 - Port 5 under full duplex mode

0 - Port 6 under half duplex mode
1 - Port 6 under full duplex mode

0 - Port 7 under half duplex mode
1 - Port 7 under full duplex mode

0 - Port 8 under half duplex mode
1 - Port 8 under full duplex mode

0 - Port 9 under half duplex mode
1 - Port 9 under full duplex mode

0 - Port 10 under half duplex mode
1 - Port 10 under full duplex mode

0 - Port 11 under half duplex mode
1 - Port 11 under full duplex mode

Table-7.28: RVSMII register

Bit

Description

Default

0 - Port 0 under normal MII mode
1 - Port 0 under reversed MII mode

0 - Port 1 under normal MII mode
1 - Port 1 under reversed MII mode

0 - Port 2 under normal MII mode
1 - Port 2 under reversed MII mode

0 - Port 3 under normal MII mode
1 - Port 3 under reversed MII mode

0 - Port 11 under normal MII mode
1 - Port 11 under reversed MII mode

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

nPM register (register 29)

The nPM register indicates the automatic PHY man-
agement capability of each port. If a bit is set in this
register, the corresponding SPEED, LINK, DPLX, and
PAUSE status registers of a port will remain unchanged.
Table-7.29 describes all the bits of this register.

ERRMSK register (register 30)

The ERRMSK register defines certain errors as

sys-

tem errors. It is reserved for factory use only. Table-
7.30 lists all the error masks specified by this register.

Table-7.29: nPM Register

Bit

Description

Default

0 - Port 0's status update enabled
1 - Port 0's status update disabled

0 - Port 1's status update enabled
1 - Port 1's status update disabled

0 - Port 2's status update enabled
1 - Port 2's status update disabled

0 - Port 3's status update enabled
1 - Port 3's status update disabled

0 - Port 4's status update enabled
1 - Port 4's status update disabled

0 - Port 5's status update enabled
1 - Port 5's status update disabled

0 - Port 6's status update enabled
1 - Port 6's status update disabled

0 - Port 7's status update enabled
1 - Port 7's status update disabled

0 - Port 8's status update enabled
1 - Port 8's status update disabled

0 - Port 9's status update enabled
1 - Port 9's status update disabled

0 - Port 10's status update enabled
1 - Port 10's status update disabled

0 - Port 11's status update enabled
1 - Port 11's status update disabled

Table-7.30: ERRMSK register

Bit

Description

Default

0
1
2
3
4
5
6
7

Reserved

CLKADJ register (register 31)

The CLKADJ register defines the delay time of the
ARLCLK relative to the transition edge of the data sig-
nals. The ARLCLK provides reference timing for sup-
porting chips, such as the ACD80800 and the
ACD80900, which need to snoop the data bus for cer-
tain activities. Table-7.31 describes all the bits of this
register.

PHYREG register (register 32-44)

The PHYREG refers to the registers residing on the
PHY devices. The ACD82112 merely provides an ac-
cess path for the control CPU to access the registers
on the PHYs. For detailed information about these reg-
isters, please refer to the PHY data sheet.

Register-32 through Register-44 are assigned to PHY-
0 through PHY-11 respectively. The contents of these
registers are the register IDs inside the corresponding
PHYs. For example, a "4" in Register-44 will point to the
Control Register-4 inside PHY-11.

Table-7.31: CLKADJ Register

Bit

Description

Default

0 - ARLCLK not inverted
1 - ARLCLK inverted
ARLCLK delay levels:

000 - level 0 delay
001 - level 1 delay
010 - level 2 delay
011 - level 3 delay
100 - level 4 delay
101 - level 5 delay
110 - level 6 delay
111 - level 7 delay

000

3:1

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Data Sheet: ACD821

INTRODUCT

Table-8.2: Pin List By Location

Pin Signal Name I/O Type Pin Signal Name I/O Type Pin Signal Name I/O Type Pin Signal Name I/O Type

A01 DAT A51

3.3V

I/O

D11

AR L S Y NC

3.3V

P 01 DAT A25

3.3V

I/O

AC17

VS S

A02 DAT A50

3.3V

I/O

D12 VS S

P 02 DAT A24

3.3V

I/O

AC18

P 3T X ENR

3.3V

A03 S T AT 1

3.3V

D13 VS S

P 03 VDD

AC19

P 3R X D0R

3.3V

A04 S T AT 3

3.3V

D14

P 11R X D3R

3.3V

P 04

VS S

AC20

VS S

A05 ADDR 9

3.3V

D15 VS S

P 23 P 7T X D0

3.3V

I/O

AC21

P 4T X D1

3.3V

A06 ADDR 8

3.3V

D16

P 11R X D1R

3.3V

P 24 P 7T X D1

3.3V

I/O

AC22

P 4R X CL K

3.3V

A07 ADDR 7

3.3V

D17

VS S

P 25 P 7T X D2

3.3V

I/O

AC23

VS S

A08 ADDR 6

3.3V

D18

P 11T X ENR

3.3V

P 26 P 7T X D3

3.3V

I/O

AC24

P 5COL

3.3V

A09 ADDR 5

3.3V

D19

P 11COL R

3.3V

I/O

R 01 DAT A23

3.3V

I/O

AC25

P 5T X D2

3.3V

I/O

A10

nWE

3.3V

D20

VS S

R 02 DAT A22

3.3V

I/O

AC26

P 5T X D1

3.3V

I/O

A11 nCS 0

3.3V

D21

P 10R X ER

3.3V

R 03 VDD

AD01

DAT A5

3.3V

I/O

A12 ADDR 4

3.3V

D22

P 10T X D2

3.3V

R 04

VS S

AD02

DAT A4

3.3V

I/O

A13 ADDR 3

3.3V

D23

VS S

R 23 P 7COL

3.3V

AD03

VDD

A14 ADDR 2

3.3V

D24 P 9R X D0

3.3V

R 24 P 7CR S

3.3V

AD04

P 0CR S R

3.3V

I/O

A15 ADDR 1

3.3V

D25

P 9T X D1

3.3V

R 25 P 6R X D3 3.3V

AD05

P 0T X D1R

3.3V

I/O

A16 ADDR 0

3.3V

D26

P 9T X D2

3.3V

R 26 P 6R X D2

3.3V

AD06

P 0T X CL K R

3.3V

I/O

A17 P 11R X ER R

3.3V

E01 DAT A43

3.3V

I/O

T 01

DAT A21

3.3V

I/O

AD07

VDD

A18 P 11T X D1R

3.3V

E02 DAT A42

3.3V

I/O

T 02

DAT A20

3.3V

I/O

AD08

P 1CR S R

3.3V

I/O

A19 P 11CR S R

3.3V

I/O

E03 AR L DIR 0

3.3V

T 03 L EDCL K

3.3V

I/O

AD09

P 1T X D0R

3.3V

I/O

A20 P 10R X D3

3.3V

E04 AR L DIR 1

3.3V

T 04 CP UIR Q

3.3V

AD10

VDD

A21 P 10R X D1

3.3V

E23 P 9R X DV

3.3V

T 23 P 6R X D1

3.3V

AD11

P 1R X DVR

3.3V

A22 P 10R X DV

3.3V

E24 P 9T X EN

3.3V

T 24 P 6R X D0

3.3V

AD12

P 1R X D3R

3.3V

A23 P 10T X D0

3.3V

E25

P 9COL

3.3V

T 25 P 6R X DV

3.3V

AD13

P 2T X D2R

3.3V

A24 P 10COL

3.3V

E26

P 9CR S

3.3V

T 26 P 6R X CL K

3.3V

AD14

VDD

A25 P 9R X D3

3.3V

F 01 DAT A41

3.3V

I/O

U01 DAT A19

3.3V

I/O

AD15

P 2R X CL K R

3.3V

I/O

A26 P 9R X D1

3.3V

F 02 DAT A40

3.3V

I/O

U02 DAT A18

3.3V

I/O

AD16

P 2R X D2R

3.3V

B 01 DAT A49

3.3V

I/O

F 03

VDD

U03

VDD

AD17

VDD

B 02 DAT A48

3.3V

I/O

F 04

VS S

U04

VS S

AD18

P 3T X D0R

3.3V

B 03 S T AT 0

3.3V

F 23 P 9T X D0

3.3V

U23

VS S

AD19

P 3R X DVR

3.3V

B 04 S T AT 2

3.3V

F 24

P 9T X D3

3.3V

U24 VDD

AD20

VDD

B 05 ADDR 10

3.3V

F 25

P 8R X D3

3.3V

U25 P 6R X ER

3.3V

AD21

P 4COL

3.3V

B 06 ADDR 11

3.3V

F 26

P 8R X D2

3.3V

U26 P 6T X CL K

3.3V

AD22

P 4T X D0

3.3V

B 07 ADDR 12

3.3V

G01 DAT A39

3.3V

I/O

V01 DAT A17

3.3V

I/O

AD23

P 4R X DV

3.3V

B 08 ADDR 13

3.3V

G02 DAT A38

3.3V

I/O

V02 DAT A16

3.3V

I/O

AD24

VDD

B 09 ADDR 14

3.3V

G03

VDD

V03

VDD

AD25

P 4R X D3

3.3V

B 10

nOE

3.3V

I/O

G04

VS S

V04 VS S

AD26

P 5CR S

3.3V

B 11

ADDR 15

3.3V

G23

VS S

V23 P 6T X D0

3.3V

I/O

AE01

DAT A3

3.3V

I/O

B 12 ADDR 16

3.3V

G24

VDD

V24 P 6T X EN

3.3V

AE02

DAT A2

3.3V

I/O

B 13 nCS 2

3.3V

G25

P 8R X DV

3.3V

V25 P 6T X D1

3.3V

I/O

AE03

VS S

B 14 nCS 3

3.3V

G26

P 8R X CL K

3.3V

V26 P 6T X D2

3.3V

I/O

AE04

P 0T X D3R

3.3V

I/O

B 15 nCS 1

3.3V

H01

DAT A37

3.3V

I/O

W01 DAT A15

3.3V

I/O

AE05

P 0T X D0R

3.3V

I/O

B 16 P 11R X DVR

3.3V

H02 DAT A36

3.3V

I/O

W02

DAT A14

3.3V

I/O

AE06

P 0R X CL K R 3.3V

I/O

B 17 P 11R X CL K R

3.3V

I/O

H03

L ED2

3.3V

I/O

W03

CP UDO

3.3V

I/O

AE07

P 0R X D0R

3.3V

B 18 P 11T X D0R

3.3V

H04

L ED3

3.3V

I/O

W04

CP UDI

3.3V

AE08

P 1COL R

3.3V

I/O

B 19 P 11T X D2R

3.3V

H23

P 8R X D1

3.3V

W23

P 6CR S

3.3V

AE09

P 1T X D2R

3.3V

I/O

B 20 P 10R X D2

3.3V

H24 P 8R X D0

3.3V

W24 P 6COL

3.3V

AE10

P 1T X CL K R

3.3V

I/O

B 21 P 10R X D0

3.3V

H25 P 8R X ER

3.3V

W25 P 6T X D3

3.3V

I/O

AE11

P 1R X CL K R

3.3V

I/O

B 22 P 10T X CL K

3.3V

H26 P 8T X D0

3.3V

W26 P 5R X D3

3.3V

AE12

P 1R X D2R

3.3V

B 23 P 10T X D1

3.3V

J01 DAT A35

3.3V

I/O

Y 01 DAT A13

3.3V

I/O

AE13

P 2T X D3R

3.3V

B 24 P 10CR S

3.3V

J02 DAT A34

3.3V

I/O

Y 02 DAT A12

3.3V

I/O

AE14

P 2T X ENR

3.3V

B 25 P 9R X D2

3.3V

J03

VDD

Y 03

VDD

AE15

P 2R X ER R

3.3V

B 26 P 9R X ER

3.3V

J04

VS S

Y 04

VS S

AE16

P 2R X D1R

3.3V

C01

DAT A47

3.3V

I/O

J23 P 8T X CL K

3.3V

Y 23

VS S

AE17

P 3COL R

3.3V

I/O

C02 DAT A46

3.3V

I/O

J24 P 8T X EN

3.3V

Y 24

VDD

AE18

P 3T X D2R

3.3V

C03 VDD

J25

P 8T X D1

3.3V

Y 25

P 5R X D1

3.3V

AE19

P 3T X CL K R

3.3V

I/O

C04 AR L DIV

3.3V

J26 P 8T X D2

3.3V

Y 26 P 5R X D2

3.3V

AE20

P 3R X CL K R

3.3V

I/O

C05 VDD

K 01

DAT A33

3.3V

I/O

AA01

DAT A11

3.3V

I/O

AE21

P 3R X D2R

3.3V

C06 AR L DI2

3.3V

K 02 DAT A32

3.3V

I/O

AA02

DAT A10

3.3V

I/O

AE22

P 4CR S

3.3V

C07

VDD

K 03

VDD AA03

MDIO

3.3V

I/O

AE23

P 4T X D2

3.3V

C08 AR L DI0

3.3V

K 04

VS S

AA04

WCHDOG

3.3V

AE24

P 4R X ER

3.3V

C09 VDD

K 23

VS S

AA23

P 5T X CL K

3.3V

AE25

P 4R X D1

3.3V

C10

VDD K 24

VDD AA24

P 5R X ER

3.3V

AE26

P 4R X D2

3.3V

C11

AR L CL K

3.3V

K 25 P 8T X D3

3.3V

AA25

P 5R X DV

3.3V

AF 01

DAT A1

3.3V

I/O

C12 VDD

K 26

P 8COL

3.3V

AA26

P 5R X D0

3.3V

AF 02

DAT A0

3.3V

I/O

C13 VDD

L 01

DAT A31

3.3V

I/O

AB 01

DAT A9

3.3V

I/O

AF 03

CL K 50

3.3V

C14 P 11R X D2R

3.3V

L 02 DAT A30

3.3V

I/O

AB 02

MDC

3.3V

AF 04

P 0T X D2R

3.3V

I/O

C15 VDD

L 03 L ED1

3.3V

I/O

AB 03

DAT A8

3.3V

I/O

AF 05

P 0R X ER R

3.3V

C16

P 11R X D0R

3.3V

L 04

L ED0

3.3V

I/O

AB 04

VS S

3.3V

AF 06

P 0R X DVR

3.3V

C17 VDD

L 23

P 8CR S

3.3V

AB 23

P 5T X D3

3.3V

I/O

AF 07

P 0R X D1R

3.3V

C18 P 11T X CL K R

3.3V

I/O

L 24

P 7R X D3

3.3V

AB 24

P 5T X D0

3.3V

I/O

AF 08

P 0R X D2R

3.3V

C19 P 11T X D3R

3.3V

L 25 P 7R X D2

3.3V

AB 25

P 5T X EN

3.3V

AF 09

P 1T X D3R

3.3V

I/O

C20 VDD

L 26

P 7R X D1

3.3V

AB 26

P 5R X CL K

3.3V

AF 10

P 1T X ENR

3.3V

C21 P 10R X CL K

3.3V

M01 DAT A29

3.3V

I/O

AC01

DAT A7

3.3V

I/O

AF 11

P 1R X ER R

3.3V

C22 P 10T X EN

3.3V

M02 DAT A28

3.3V

I/O

AC02

DAT A6

3.3V

I/O

AF 12

P 1R X D1R

3.3V

C23 P 10T X D3

3.3V

M03

VDD

AC03

nR ES ET

3.3V

AF 13

P 2COL R

3.3V

I/O

C24

VDD

M04

VS S

AC04

VS S

AF 14

P 2T X D0R

3.3V

C25 P 9R X CL K

3.3V

M23 P 7R X D0

3.3V

AC05

P 0COL R

3.3V

I/O

AF 15

P 2T X CL K R

3.3V

I/O

C26 P 9T X CL K

3.3V

M24 P 7R X DV

3.3V

AC06

P 0T X ENR

3.3V

AF 16

P 2R X D0R

3.3V

D01 DAT A45

3.3V

I/O

M25 P 7R X CL K

3.3V

AC07

VS S

AF 17

P 3CR S R

3.3V

I/O

D02 DAT A44

3.3V

I/O

M26 P 7R X ER

3.3V

AC08

P 0R X D3R

3.3V

AF 18

P 3T X D3R

3.3V

D03 VS S

3.3V

N01

DAT A27

3.3V

I/O

AC09

P 1T X D1R

3.3V

I/O

AF 19

P 3T X D1R

3.3V

D04 VS S

N02

DAT A26

3.3V

I/O

AC10

VS S

AF 20

P 3R X ER R

3.3V

D05 AR L DI3

3.3V

N03

L EDVL D1

3.3V

I/O

AC11

P 1R X D0R

3.3V

AF 21

P 3R X D1R

3.3V

D06 VS S

N04

L EDVL D0

3.3V

I/O

AC12

P 2CR S R

3.3V

I/O

AF 22

P 3R X D3R

3.3V

D07 VS S

N23

VS S

AC13

P 2T X D1R

3.3V

AF 23

P 4T X D3

3.3V

D08 AR L DI1

3.3V

N24 VDD

AC14

VS S

AF 24

P 4T X EN

3.3V

D09 VS S

N25

P 7T X CL K

3.3V

AC15

P 2R X DVR

3.3V

AF 25

P 4T X CL K

3.3V

D10 VS S

N26

P 7T X EN

3.3V

AC16

P 2R X D3R

3.3V

AF 26

P 4R X D0

3.3V

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

Table-8.3: Pin List By Name

Signal

Name

I/O Type

Pin

Signal

Name

I/O Type

Pin

Signal

Name

I/O Type

Pin

Signal

Name

I/O

Type

Pin

ADDR 0

3.3V

A16 L EDVL D1

3.3V

I/O

N03 P 5R X D0

3.3V

AA26

P 11CR S R

3.3V

I/O

A19

ADDR 1

3.3V

A15 MDC

3.3V

AB 02

P 5R X D1

3.3V

Y 25

P 11R X CL K R

3.3V

I/O

B 17

ADDR 2

3.3V

A14 MDIO

3.3V

I/O

AA03

P 5R X D2

3.3V

Y 26

P 11R X D0R

3.3V

C16

ADDR 3

3.3V

A13 nCS 0

3.3V

A11 P 5R X D3

3.3V

W26

P 11R X D1R

3.3V

D16

ADDR 4

3.3V

A12 nCS 1

3.3V

B 15 P 5R X DV

3.3V

AA25

P 11R X D2R

3.3V

C14

ADDR 5

3.3V

A09 nCS 2

3.3V

B 13 P 5R X ER

3.3V

AA24

P 11R X D3R

3.3V

D14

ADDR 6

3.3V

A08 nCS 3

3.3V

B 14

P 5T X CL K

3.3V

AA23

P 11R X DVR

3.3V

B 16

ADDR 7

3.3V

A07 nOE

3.3V

I/O

B 10

P 5T X D0

3.3V

I/O

AB 24

P 11R X ER R

3.3V

A17

ADDR 8

3.3V

A06 nR ES ET

3.3V

AC03

P 5T X D1

3.3V

I/O

AC26

P 11T X CL K R

3.3V

I/O

C18

ADDR 9

3.3V

A05 nWE

3.3V

A10

P 5T X D2

3.3V

I/O

AC25

P 11T X D0R

3.3V

B 18

ADDR 10

3.3V

B 05 P 0COL R

3.3V

I/O

AC05

P 5T X D3

3.3V

I/O

AB 23

P 11T X D1R

3.3V

A18

ADDR 11

3.3V

B 06 P 0CR S R

3.3V

I/O

AD04

P 5T X EN

3.3V

AB 25

P 11T X D2R

3.3V

B 19

ADDR 12

3.3V

B 07

P 0R X CL K R 3.3V

I/O

AE06

P 6COL

3.3V

W24

P 11T X D3R

3.3V

C19

ADDR 13

3.3V

B 08 P 0R X D0R

3.3V

AE07

P 6CR S

3.3V

W23 P 11T X ENR

3.3V

D18

ADDR 14

3.3V

B 09 P 0R X D1R

3.3V

AF 07

P 6R X CL K

3.3V

T 26

S T AT 0

3.3V

B 03

ADDR 15

3.3V

B 11

P 0R X D2R

3.3V

AF 08

P 6R X D0

3.3V

T 24 S T AT 1

3.3V

A03

ADDR 16

3.3V

B 12 P 0R X D3R

3.3V

AC08

P 6R X D1

3.3V

T 23

S T AT 2

3.3V

B 04

AR L CL K

3.3V

C11

P 0R X DVR

3.3V

AF 06

P 6R X D2

3.3V

R 26

S T AT 3

3.3V

A04

AR L DI0

3.3V

C08

P 0R X ER R

3.3V

AF 05

P 6R X D3 3.3V

R 25

VDD

P ower

3.3V

AD03

AR L DI1

3.3V

D08 P 0T X CL K R

3.3V

I/O

AD06

P 6R X DV

3.3V

T 25

VDD

P ower

3.3V

AD07

AR L DI2

3.3V

C06 P 0T X D0R

3.3V

I/O

AE05

P 6R X ER

3.3V

U25

VDD

P ower

3.3V

AD14

AR L DI3

3.3V

D05 P 0T X D1R

3.3V

I/O

AD05

P 6T X CL K

3.3V

U26

VDD

P ower

3.3V

AD20

AR L DIR 0

3.3V

E03 P 0T X D2R

3.3V

I/O

AF 04

P 6T X D0

3.3V

I/O

V23

VDD

P ower

3.3V

AD24

AR L DIR 1

3.3V

E04 P 0T X D3R

3.3V

I/O

AE04

P 6T X D1

3.3V

I/O

V25

VDD

P ower

3.3V

C03

AR L DIV

3.3V

C04 P 0T X ENR

3.3V

AC06

P 6T X D2

3.3V

I/O

V26

VDD

P ower

3.3V

C05

AR L S Y NC

3.3V

D11

P 1COL R

3.3V

I/O

AE08

P 6T X D3

3.3V

I/O

W25 VDD

P ower

3.3V

C09

CL K 50 3.3V

AF 03

P 1CR S R

3.3V

I/O

AD08

P 6T X EN

3.3V

V24

VDD

P ower

3.3V

C12

CP UDI

3.3V

W04 P 1R X CL K R

3.3V

I/O

AE11

P 7COL

3.3V

R 23

VDD

P ower

3.3V

C13

CP UDO

3.3V

I/O

W03 P 1R X D0R

3.3V

AC11

P 7CR S

3.3V

R 24

VDD

P ower

3.3V

C15

CP UIR Q

3.3V

T 04 P 1R X D1R

3.3V

AF 12

P 7R X CL K

3.3V

M25

VDD

P ower

3.3V

C20

DAT A0

3.3V

I/O

AF 02

P 1R X D2R

3.3V

AE12

P 7R X D0

3.3V

M23 VDD

P ower

3.3V

C24

DAT A1

3.3V

I/O

AF 01

P 1R X D3R

3.3V

AD12

P 7R X D1

3.3V

L 26 VDD

P ower

3.3V

G03

DAT A2

3.3V

I/O

AE02

P 1R X DVR

3.3V

AD11

P 7R X D2

3.3V

L 25 VDD

P ower

3.3V

J03

DAT A3

3.3V

I/O

AE01

P 1R X ER R

3.3V

AF 11

P 7R X D3

3.3V

L 24 VDD

P ower

3.3V

N24

DAT A4

3.3V

I/O

AD02

P 1T X CL K R

3.3V

I/O

AE10

P 7R X DV

3.3V

M24 VDD

P ower

3.3V

P 03

DAT A5

3.3V

I/O

AD01

P 1T X D0R

3.3V

I/O

AD09

P 7R X ER

3.3V

M26 VDD

P ower

3.3V

R 03

DAT A6

3.3V

I/O

AC02

P 1T X D1R

3.3V

I/O

AC09

P 7T X CL K

3.3V

N25 VDD

P ower

3.3V

Y 24

DAT A7

3.3V

I/O

AC01

P 1T X D2R

3.3V

I/O

AE09

P 7T X D0

3.3V

I/O

P 23 VDD

P ower

3.3V

AD17

DAT A8

3.3V

I/O

AB 03

P 1T X D3R

3.3V

I/O

AF 09

P 7T X D1

3.3V

I/O

P 24 VDD

P ower

3.3V

C10

DAT A9

3.3V

I/O

AB 01

P 1T X ENR

3.3V

AF 10

P 7T X D2

3.3V

I/O

P 25 VDD

P ower

3.3V

K 03

DAT A10

3.3V

I/O

AA02

P 2COL R

3.3V

I/O

AF 13

P 7T X D3

3.3V

I/O

P 26 VDD

P ower

3.3V

K 24

DAT A11

3.3V

I/O

AA01

P 2CR S R

3.3V

I/O

AC12

P 7T X EN

3.3V

N26 VDD

P ower

3.3V

U03

DAT A12

3.3V

I/O

Y 02 P 2R X CL K R

3.3V

I/O

AD15

P 8COL

3.3V

K 26

VDD P ower

3.3V

U24

DAT A13

3.3V

I/O

Y 01 P 2R X D0R

3.3V

AF 16

P 8CR S

3.3V

L 23

VDD P ower

3.3V

Y 03

DAT A14

3.3V

I/O

W02 P 2R X D1R

3.3V

AE16

P 8R X CL K

3.3V

G26

VDD

P ower

3.3V

AD10

DAT A15

3.3V

I/O

W01 P 2R X D2R

3.3V

AD16

P 8R X D0

3.3V

H24

VDD

P ower

3.3V

C07

DAT A16

3.3V

I/O

V02 P 2R X D3R

3.3V

AC16

P 8R X D1

3.3V

H23

VDD

P ower

3.3V

C17

DAT A17

3.3V

I/O

V01 P 2R X DVR

3.3V

AC15

P 8R X D2

3.3V

F 26

VDD

P ower

3.3V

F 03

DAT A18

3.3V

I/O

U02 P 2R X ER R

3.3V

AE15

P 8R X D3

3.3V

F 25

VDD

P ower

3.3V

G24

DAT A19

3.3V

I/O

U01 P 2T X CL K R

3.3V

I/O

AF 15

P 8R X DV

3.3V

G25

VDD

P ower

3.3V

M03

DAT A20

3.3V

I/O

T 02 P 2T X D0R

3.3V

AF 14

P 8R X ER

3.3V

H25

VDD

P ower

3.3V

V03

DAT A21

3.3V

I/O

T 01 P 2T X D1R

3.3V

AC13

P 8T X CL K

3.3V

J23

VS S

3.3V

AB 04

DAT A22

3.3V

I/O

R 02 P 2T X D2R

3.3V

AD13

P 8T X D0

3.3V

H26

VS S

3.3V

D03

DAT A23

3.3V

I/O

R 01 P 2T X D3R

3.3V

AE13

P 8T X D1

3.3V

J25

VS S

Ground

D09

DAT A24

3.3V

I/O

P 02 P 2T X ENR

3.3V

AE14

P 8T X D2

3.3V

J26

VS S

Ground

D12

DAT A25

3.3V

I/O

P 01 P 3COL R

3.3V

I/O

AE17

P 8T X D3

3.3V

K 25

VS S

Ground

D15

DAT A26

3.3V

I/O

N02 P 3CR S R

3.3V

I/O

AF 17

P 8T X EN

3.3V

J24

VS S

Ground

D20

DAT A27

3.3V

I/O

N01 P 3R X CL K R

3.3V

I/O

AE20

P 9COL

3.3V

E25

VS S

Ground

G04

DAT A28

3.3V

I/O

M02 P 3R X D0R

3.3V

AC19

P 9CR S

3.3V

E26

VS S Ground

AC04

DAT A29

3.3V

I/O

M01 P 3R X D1R

3.3V

AF 21

P 9R X CL K

3.3V

C25

VS S Ground

AC14

DAT A30

3.3V

I/O

L 02 P 3R X D2R

3.3V

AE21

P 9R X D0

3.3V

D24

VS S Ground

AC23

DAT A31

3.3V

I/O

L 01 P 3R X D3R

3.3V

AF 22

P 9R X D1

3.3V

A26

VS S Ground

D04

DAT A32

3.3V

I/O

K 02 P 3R X DVR

3.3V

AD19

P 9R X D2

3.3V

B 25

VS S Ground

D10

DAT A33

3.3V

I/O

K 01 P 3R X ER R

3.3V

AF 20

P 9R X D3

3.3V

A25

VS S Ground

D13

DAT A34

3.3V

I/O

J02 P 3T X CL K R

3.3V

I/O

AE19

P 9R X DV

3.3V

E23

VS S Ground

K 04

DAT A35

3.3V

I/O

J01 P 3T X D0R

3.3V

AD18

P 9R X ER

3.3V

B 26

VS S Ground

K 23

DAT A36

3.3V

I/O

H02 P 3T X D1R

3.3V

AF 19

P 9T X CL K

3.3V

C26

VS S Ground

P 04

DAT A37

3.3V

I/O

H01 P 3T X D2R

3.3V

AE18

P 9T X D0

3.3V

F 23

VS S Ground

R 04

DAT A38

3.3V

I/O

G02 P 3T X D3R

3.3V

AF 18

P 9T X D1

3.3V

D25

VS S Ground

Y 04

DAT A39

3.3V

I/O

G01 P 3T X ENR

3.3V

AC18

P 9T X D2

3.3V

D26

VS S

Ground

AC07

DAT A40

3.3V

I/O

F 02 P 4COL

3.3V

AD21

P 9T X D3

3.3V

F 24

VS S

Ground

AC10

DAT A41

3.3V

I/O

F 01 P 4CR S

3.3V

AE22

P 9T X EN

3.3V

E24

VS S

Ground

AC17

DAT A42

3.3V

I/O

E02 P 4R X CL K

3.3V

AC22

P 10COL

3.3V

A24

VS S

Ground

AC20

DAT A43

3.3V

I/O

E01 P 4R X D0

3.3V

AF 26

P 10CR S

3.3V

B 24

VS S

Ground

AE03

DAT A44

3.3V

I/O

D02 P 4R X D1

3.3V

AE25

P 10R X CL K

3.3V

C21

VS S

Ground

D06

DAT A45

3.3V

I/O

D01 P 4R X D2

3.3V

AE26

P 10R X D0

3.3V

B 21

VS S

Ground

D07

DAT A46

3.3V

I/O

C02 P 4R X D3

3.3V

AD25

P 10R X D1

3.3V

A21

VS S

Ground

D17

DAT A47

3.3V

I/O

C01

P 4R X DV

3.3V

AD23

P 10R X D2

3.3V

B 20

VS S

Ground

D23

DAT A48

3.3V

I/O

B 02 P 4R X ER

3.3V

AE24

P 10R X D3

3.3V

A20

VS S

Ground

F 04

DAT A49

3.3V

I/O

B 01 P 4T X CL K

3.3V

AF 25

P 10R X DV

3.3V

A22

VS S

Ground

G23

DAT A50

3.3V

I/O

A02 P 4T X D0

3.3V

AD22

P 10R X ER

3.3V

D21

VS S

Ground

J04

DAT A51

3.3V

I/O

A01 P 4T X D1

3.3V

AC21

P 10T X CL K

3.3V

B 22

VS S

Ground

M04

L ED0

3.3V

I/O

L 04 P 4T X D2

3.3V

AE23

P 10T X D0

3.3V

A23

VS S

Ground

N23

L ED1

3.3V

I/O

L 03 P 4T X D3

3.3V

AF 23

P 10T X D1

3.3V

B 23

VS S

Ground

U04

L ED2

3.3V

I/O

H03 P 4T X EN

3.3V

AF 24

P 10T X D2

3.3V

D22

VS S

Ground

U23

L ED3

3.3V

I/O

H04 P 5COL

3.3V

AC24

P 10T X D3

3.3V

C23

VS S

Ground

V04

L EDCL K

3.3V

I/O

T 03 P 5CR S

3.3V

AD26

P 10T X EN

3.3V

C22

VS S

Ground

Y 23

L EDVL D0

3.3V

I/O

N04 P 5R X CL K

3.3V

AB 26

P 11COL R

3.3V

I/O

D19 WCHDOG

3.3

AA04

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

1. SUMMARY

The internal Address Resolution Logic (ARL) of ACD's
switch controllers automatically builds up an address
table and maps up to 2,048 MAC addresses into their
associated port. It can work by itself without any CPU
intervention in an UN-managed system.

For a managed system, the management CPU can con-
figure the operation mode of the ARL, learn all the ad-
dress in the address table, add new address into the
table, control security or filtering feature of each ad-
dress entry etc.

The ARL is designed with such a high performance that
it will never slow down the frame switching operation. It
helps the switch controllers to reach wire speed for-
warding rate under any type of traffic load.

The address space can be expanded to 11K entries by
using the external ARL, the ACD80800.

2. FEATURES

�

Supports up to 2,048 MAC address lookup

�

Provides UART type of interface for the manage-
ment CPU

�

Wire speed address lookup time.

�

Wire speed address learning time.

�

Address can be automatically learned from switch
without the CPU intervention

�

Address can be manually added by the CPU through
the CPU interface

�

Each MAC address can be secured by the CPU
from being changed or aged out

�

Each MAC address can be marked by the CPU
from receiving any frame

�

Each newly learned MAC address is notified to the
CPU

�

Each aged out MAC address is notified to the CPU

�

Automatic address aging control, with configurable
aging period

CPU Interface

Address

Registers

Data

Registers

Command

Registers

Control

Registers

Switch Interface

Address

Learning

Engine

CPU Interface Engine

Address Table

(2048 Entries)

Figure-1. ARL Block Diagram

Address

Aging

Engine

Address

L o o k u p

Engine

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

3. FUNCTIONAL DESCRIPTION

The ARL provides Address Resolution service for ACD's
switch controllers.

Figure 2 is a block diagram of the

ARL.

Traffic Snooping

All Ethernet frames received by ACD's switch controller
have to be stored into memory buffer. As the frame
data are written into memory, the status of the data
shown on the data bus are displayed by ACD's switch
controller through a state bus. The ARL's Switch Con-
troller Interface contains the signals of the data bus and
the state bus. By snooping the data bus and the state
bus of ACD's switch controller, the ARL can detect the
occurrence of any destination MAC address and source
MAC address embedded inside each frame.

Address Learning

Each source address caught from the data bus, to-
gether with the ID of the ingress port, is passed to the
Address Learning Engine of the ARL. The Address
Learning Engine will first determine whether the frame
is a valid frame. For a valid frame, it will first try to find
the source address from the current address table. If
that address doesn't exist, or if it does exist but the port
ID associated with the MAC address is not the ingress
port, the address will be learned into the address table.
After an address is learned by the address learning
engine, the CPU will be notified to read this newly learned
address so that it can add it into the CPU's address
table.

Address Aging

After each source address is learned into the address
table, it has to be refreshed at least once within each
address aging period. Refresh means it is caught again
from the switch interface. If it has not occurred for a
pre-set aging period, the address aging engine will re-
move the address from the address table. After an ad-
dress is removed by the address aging engine, the CPU
will be notified through interrupt request that it needs to
read this aged out address so that it can remove this
address from the CPU's address table.

Address Lookup

Each destination address is passed to the Address
Lookup Engine of the ARL. The Address Lookup En-
gine checks if the destination address matches with
any existing address in the address table. If it does, the
ARL returns the associated Port ID to ACD's switch
controller through the output data bus. Otherwise, a no
match result is passed to ACD's switch controller through
the output data bus.

CPU Interface

The CPU can access the registers of the ARL by send-
ing commands to the UART data input line. Each com-
mand is consisted by action (read or write), register
type, register index, and data. Each result of command
execution is returned to the CPU through the UART data
output line.

CPU Interface Registers

The ARL provides a bunch of registers for the control
CPU. Through the registers, the CPU can read all ad-
dress entries of the address table, delete particular ad-
dresses from the table, add particular addresses into
the table, secure an address from being changed, set
filtering on some addresses, change the hashing algo-
rithm etc. Through a proper interrupt request signal, the
CPU can be notified whenever it needs to retrieve data
for a newly-learned address or an aged-out address so
that the CPU can build an exact same address table
learned by the ARL.

CPU Interface Engine

The command sent by the control CPU is executed by
the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned ad-
dress. The CPU Interface Engine is responsible to find
the newly-learned address from the address table, and
passes it to CPU. The CPU may request to learn next
newly-learned address. Then, it is again the responsi-
bility of the CPU Interface Engine to search for next
newly-learned address from the address table.

Address Table

The address table can hold up to 2,048 MAC addresses,
together with the associated port ID, security flag, filter-
ing flag, new flag, aging information etc. The address
table resides in the embedded SRAM inside the ARL.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

Header

Address

Data

Checksum

Header

Address

Data

Checksum

4. INTERFACE DESCRIPTION

CPU Interface

The CPU can communicate with the ARL through the
UART interface of the switch IC. The management CPU
can send command to the ARL by writing into associ-
ated registers, and retrieve result from ARL by reading
corresponding registers. The registers are described
in the section of "Register Description." The CPU inter-
face signals are described by

table-1:

UARTDI is used by the control CPU to send command
into the ARL. The baud rate will be automatically de-
tected by the ARL. The result will be returned through
the UARTDO line with the detected baud rate. The for-
mat of the command packet is shown as follows:

where:

�

Header is further defined as:

b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7, same as the host switch control-
ler)
b7:b5 - device type, 010 for ARL

�

Address - 8-bit value used to select the reg-
ister to access

�

Data - 32-bit value, only the LSB is used
for write operation, all 0 for read operation

�

Checksum - 8-bit value of XOR of all bytes

UARTDO is used to return the result of command ex-
ecution to the CPU. The format of the result packet is
shown as follows:

where:

�

Header is further defined as:

b1:b0 - read or write, 01 for read, 11
for write
b4:b2 - device number, 000 to 111 (0
to 7)
b7:b5 - device type, 010 for ARL

�

Address - 8-bit value for address of the
selected register

�

Data - 32-bit value, only the LSB is used
for read operation, all 0 for write operation

�

Checksum - 8-bit value of XOR of all bytes

The ARL will always check the CMD header to see if
both the device type and the device number matches
with its setting. If not, it ignores the command and will
not generate any response to this command.

Table-1: CPU Interface

Name

I/O

Description

UARTDI

UART input data line.

UARTDO

UART output data line.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

Data Sheet: ACD821

INTRODUCT

The

DataRegX are registers used to pass the param-

eter of the command to the ACD80800, and the result
of the command to the CPU.

The

AddrRegX are registers used to specify the ad-

dress associated with the command.

The

CmdReg is used to pass the type of command to

the ACD80800. The command types are listed in

table-

3. The details of each command is described in the
chapter of "Command Description."

The

RstReg is used to indicate the status of command

execution. The result code is listed as follows:

�

01 - command is being executed and is
not done yet

�

10 - command is done with no error

�

1x - command is done, with error indi-
cated by x, where x is a 4-bit error code:
0001 for cannot find the entry as speci-
fied

5. REGISTER DESCRIPTION

ACD80800 provides a bunch of registers for the CPU
to access the address table inside it. Command is sent
to ACD80800 by writing into the associated registers.
Before the CPU can pass a command to ACD80800, it
must check the result register

(register 11) to see if the

command has been done. When the Result register
indicates the command has been done, the CPU may
need to retrieve the result of previous command first.
After that, the CPU has to write the associated param-
eter of the command into the Data registers. Then, the
CPU can write the command type into the command
register. When a new command is written into the com-
mand register, ACD80800 will change the status of the
Result register to 0. The Result register will indicate the
completion of the command at the end of the execution.
Before the completion of the execution, any command
written into the command register is ignored by
ACD80800.

The registers accessible to the CPU are described by
table-2:

Table-3: Command List

Command

Description

0x09

Add the specified MAC address into the
address table

0x0A

Set a lock for the specified MAC
address

0x0B

Set a filtering flag for the specified MAC
address

0x0C

Delete the specified MAC address from
the address table