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comtech aha corporation
PRODUCT BRIEF *
AHA3580
80 MBYTES/SEC ALDC DATA
COMPRESSION COPROCESSOR IC
The AHA3580 is a single-chip CMOS lossless
compression and decompression integrated circuit.
The device implements the ALDC compression
algorithm defined by various industry standards.
This algorithm is also known as Adaptive Lossless
Data Compression.
The device compresses, decompresses or
passes data through. Flexible interfaces connect
directly with various microprocessors and DMA
devices used in tape drive systems including SCSI
and Fiber Controllers. Content Addressable
Memory within the ALDC engine eliminates
external SRAMs typically required for dictionary
storage in a compression system.
FEATURES
PERFORMANCE:
80 MBytes/sec data compression, decompression
or pass-through rate with a single 80 MHz clock
2:1 average compression ratio
A four byte Record Length register allows record
lengths up to 4 gigabytes
Four byte Record Count register allows multiple
record transfers
Error checking in decompression mode reportable
via an interrupt
FLEXIBILITY:
Polled or interrupt driven I/O
Port A/B DMA interfaces include FAS466,
FAS440 and AIC-43C97C
Programmable polarity for DMA control signals
DMA FIFO access via microprocessor port at Port
A Interface
SYSTEM INTERFACE:
Single-chip data compression solution
Programmable Interrupts
Interfaces directly with industry standard SCSI
chips
OTHERS:
Open standard ALDC adaptive lossless
compression algorithm
Complies to QIC-154, ECMA 222, ANSI
X3.280-1996 and ISO 15200 standard
specifications
Algorithm compatible to IBM ALDC1-20S-HA,
IBM ALDC1-20S-LP and AHA3520
100 pin package in 14 mm 14 mm TQFP body
Low power 3.3 Volt device
APPLICATIONS
Tape drives
Network communications wired and wireless
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62
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60
59
58
57
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51
AP
ARI
T
Y
[
0
]
AD
A
T
A[
8
]
AD
A
T
A[
9
]
AD
A
T
A[
1
0
]
AD
A
T
A[
1
1
]
AD
A
T
A[
1
2
]
GND
VDD
AD
A
T
A[
1
3
]
AD
A
T
A[
1
4
]
AD
A
T
A[
1
5
]
AD
A
T
A[
0
]
AD
A
T
A[
1
]
NC
A
D
BO
EN
AD
A
T
A[
2
]
GND
VDD
AD
A
T
A[
3
]
AD
A
T
A[
4
]
AD
A
T
A[
5
]
+T
IE
AD
A
T
A[
6
]
AD
A
T
A[
7
]
GND
50
49
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46
45
44
43
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32
31
VDD
ACIN
ADDR[0]
ADDR[1]
ADDR[2]
+TIE
TIE
BCIN
NC
ADDR[3]
ADDR[4]
VDD
GND
CLK
TIE
RESETN
BCOUT
TIE
BDBOEN
WAITN
30
29
28
27
26
NC
IREQN
NC
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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20
21
22
23
24
25
GND
BD
A
T
A[
7
]
BD
A
T
A[
6
]
BD
A
T
A[
5
]
BD
A
T
A[
4
]
BD
A
T
A[
3
]
BD
A
T
A[
2
]
VDD
GND
BD
A
T
A[
1
]
BF
F_
F
E
BA
F
_
AE
BD
A
T
A[
0
]
BD
A
T
A[
1
5
]
BD
A
T
A[
1
4
]
BD
A
T
A[
1
3
]
BD
A
T
A[
1
2
]
VDD
GND
BD
A
T
A[
1
1
]
BD
A
T
A[
1
0
]
BD
A
T
A[
9
]
BD
A
T
A[
8
]
BP
AR
I
T
Y
[
0
]
BP
AR
I
T
Y
[
1
]
76
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80
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VDD
GND
APARITY[1]
MDATA[7]
+TIE
MDATA[6]
MDATA[5]
MDATA[4]
MDATA[3]
ACOUT
NC
GND
VDD
MCIN[0]
MCIN[1]
MDATA[2]
MDATA[1]
MDATA[0]
NC
96
97
98
99
100
AFF_FE
AAF_AE
MMODE
NC
VDD
AHA3580A-080 PTC
+TIE
XXXXXXX MMDDQL
1YWWBZZZZZ
CCCCCCC
Note: XXXXXXX = IBM part number
MM = Module Mfg. location; DD = Device Mfg. location
QL = Qualification Level
1YWWBZZZZZ = IBM assembly date code & module lot no.
CCCCCCC = Country of Origin
comtech aha corporation
Figure 1:
AHA3580 Block Diagram
FUNCTIONAL DESCRIPTION
Major blocks in this device are the
Microprocessor Interface, Port A Interface, Port B
Interface, and the Compression/Decompression
Engine. The Microprocessor Interface provides
status and control information by register access.
Port A and Port B Interfaces are DMA ports
configurable for polarity, handshaking modes, and
other options. The operating mode establishes the
direction of both the Port A and Port B Interfaces.
Compression or Compression Pass Through sets the
Port A Interface as an input and the Port B Interface
as an output. Conversely Decompression or
Decompression Pass Through sets the Port A
Interface as an output and the Port B Interface as an
input. Decompression Output Disabled mode
allows the device to decompress a block of data up
to a predetermined point while dumping the
uncompressed data, then automatically begin
outputting the remaining uncompressed data in that
block or record.
A four byte Record Length and four byte
Record Count registers allow the user to partition
the data into multiple records to process.
Compression Pass Through mode and
Decompression Pass Through modes allow data
transfers through the device without changing the
data. Both the Port A Interface and Port B Interface
have 16-byte FIFOs. Port A and Port B have two
selectable DMA modes, FAS466 and AIC-43C97C.
FAS466 mode operates as slave on Port A and
master on Port B. The AIC-43C97C mode is, more
explicitly, SCSI initiator synchronous mode and
operates as master on Port A and slave on Port B.
APARITY[1:0]
ADATA[15:0]
CLOCK
ACOUT
ACIN
AAF_AE
BPARITY[1:0]
BDATA[15:0]
BCOUT
BDBOEN
BCIN
MC
IN[1:0]
WA
I
T
N
ADD
R[4:0]
MMO
DE
RESETN
IR
E
Q
N
ADBOEN
AFF_FE
BFF_FE
MD
A
T
A[7:0]
BAF_AE
PORT A
DMA
STATE
MACHINE
CLOCK
GENERATION
PORT B
DMA
STATE
MACHINE
PROCESSOR INTERFACE STATE MACHINE
PROCESSOR INTERFACE
PORT A
INTERFACE
PORT B
INTERFACE
AHA3580 Compression Chip
ALDC
CORE
IBM,
IBM is a registered trademark of IBM.
comtech aha corporation
THE ALDC COMPRESSION ALGORITHM
The ALDC (Adaptive Lossless Data
Compression) algorithm is one variant of the LZ1
(Lempel-Ziv 1) class of data compression
algorithms, first proposed by Abraham Lempel and
Jacob Ziv in 1977.
LZ1 algorithms achieve compression by
building and maintaining a data structure, called a
HISTORYBUFFER. An LZ1 encode process and
an LZ1 decode process both initialize this structure
to the same known state, and update it in an identical
fashion. The encoder does this using the input data
it receives for compression, while the decoder
generates an identical data stream as its output,
which it also uses for the update process.
The compression process consists of examining
the incoming data stream to identify any sequences
or strings of data bytes which already exist in the
encoder history. If an identical such history is
available to a decoder, this matching string can be
encoded and output as a 2 element
COPYPOINTER, containing a byte count and
history location. It is then possible for a decoder to
reproduce this string exactly, by copying it from the
given location in its own history. If the
COPYPOINTER can be encoded in fewer bits of
information than required for the data string it
specifies, compression is achieved.
If an incoming byte of data does not form part of
a matching string, a LITERAL, containing this
embedded value, is encoded and then output to
explicitly represent this byte.
A decoder performs the inverse operation by
first parsing a compressed data stream into
LITERALS and COPYPOINTERS for processing.
ALDC is a lossless algorithm, insuring that the
decompressed data output is exactly the same as the
uncompressed data input. QIC-154 Development
Standard describes this industry standard algorithm
in detail.
PORT A AND PORT B CONFIGURATION
Port A and Port B are 16-bit bidirectional data
ports with parity checking and generation.The ports
are controlled by the configuration registers
ACNF[15:0] and BCNF[15:0], and polarity
registers APOL[7:0] and BPOL[7:0].
Table 1:
Port A Interface Signals
Table 2:
Port B Interface Signals
SIGNAL
NAME
AIC-43C97C
FAS466
APOL
bit
DIRECTION
ACIN
DACKA
DREQA
7
I
ACOUT
DREQA
DACKA
5
O
ADBOEN
deasserted
ADBOEN
3
O
AFF_FE
not used
AFF_FE
1
I
AAF_AE
not used
AAF_AE
0
I
SIGNAL
NAME
FAS466
AIC-43C97C
BPOL
bit
DIRECTION
BCIN
DACKB
DREQB
7
I
BCOUT
DREQB
DACKB
5
O
BDBOEN
BDBOEN
deasserted
3
I
BFF_FE
BFF_FE
not used
1
O
BAF_AE
BAF_AE
not used
0
O
www.aha.com
e-mail: sales@aha.com
comtech aha corporation
PB3580_0104
2005 Comtech AHA Corp.
comtech aha corporation
1126 Alturas Drive
fax: 208.892.5601
tel: 208.892.5600
Moscow ID 83843-8331
A subsidiary of Comtech Telecommunications Corporation
SYSTEMS APPLICATIONS
A typical application for the AHA3580 is the
implementation of data compression in a tape drive
system. An in-line architecture is employed in this
system.
The in-line application inserts compression
directly between the host and the system data buffer.
There is no direct connection between the buffer
and the host. For compression, data flows from the
host, through the bus controller and into the
AHA3580. The data is then compressed by the
ALDC engine and flows into the system buffer
followed by the tape drive interface. This data flow
is usually controlled by a local microprocessor. For
decompression, the flow is reversed.
In an in-line architecture the AHA compression
chip operates at the data rate of the host interface
controller. The AHA3580 device supports a
sustained data transfer rate of up to 80 MBytes/sec.
In a look-aside application, the system buffer is
in series with the data flow. There is a direct
connection between the host and the buffer memory
through a DMA port. For compression, data flows
from the host, through the bus interface and
peripheral controller and into the system buffer.
Data then flows from the system buffer into the
AHA3580 where it is compressed and sent back to
the system buffer. Finally, data is transferred from
the system buffer interface. During decompression,
this flow is reversed.
EXAMPLE IN-LINE APPLICATION
EXAMPLE LOOK-ASIDE APPLICATION
ORDERING INFORMATION
ABOUT AHA
Comtech AHA Corporation (AHA) develops
and markets superior integrated circuits, boards,
and intellectual property core technology for
communications systems architects worldwide.
AHA has been setting the standard in Forward Error
Correction and Lossless Data Compression
technology for many years and provides flexible,
cost-effective solutions for today's growing
bandwidth and reliability challenges. Comtech
AHA Corporation is a wholly owned subsidiary of
Comtech Telecommuncations Corp. (NASDAQ:
CMTL). For more information, visit www.aha.com.
AHA3580
DATA COMPRESSION
INTERFACE
CHIP
BUS
SCSI or ATAPI
CONTROLLER
BUFFER
DRAM
SYSTEM
PROCESSOR
SYSTEM
MEMORY
CONTROLLER
TAPE
DRIVE
INTERFACE
AHA3580
DATA COMPRESSION
INTERFACE
CHIP
BUS
SCSI or ATAPI
CONTROLLER
BUFFER
DRAM
SYSTEM
PROCESSOR
SYSTEM
MEMORY
CONTROLLER
PERIPHERAL
CONTROLLER
DATA FLOW
CONTROL
PART NUMBER
DESCRIPTION
AHA3580A-080 PTC
80 Mbytes/sec ALDC Data
Compression Coprocessor IC
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