ii
Copyright 2001 ARM Limited. All rights reserved.
ARM DDI 0201A
ARM946E-S (Rev 1)
Technical Reference Manual
Copyright 2001 ARM Limited. All rights reserved.
Release Information
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as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
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may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
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fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final (information on a developed product).
Web Address
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Change history
Date
Issue
Change
16th February 2001
A
First release
ARM DDI 0201A
Copyright 2001 ARM Limited. All rights reserved.
iii
Contents
ARM946E-S (Rev 1)Technical Reference Manual
Preface
About this document ..................................................................................... xii
Further reading ............................................................................................. xv
Feedback ..................................................................................................... xvi
Chapter 1
Introduction
1.1
About the ARM946E-S (Rev 1) ................................................................... 1-2
1.2
Microprocessor block diagram .................................................................... 1-3
Chapter 2
Programmer's Model
2.1
About the ARM946E-S (Rev 1) programmer's model ................................. 2-2
2.2
About the ARM9E-S programmer's model .................................................. 2-3
2.3
CP15 register map summary ...................................................................... 2-4
Chapter 3
Caches
3.1
Cache architecture ...................................................................................... 3-2
3.2
ICache ......................................................................................................... 3-6
3.3
DCache ....................................................................................................... 3-8
3.4
Cache lockdown ........................................................................................ 3-12
Contents
iv
Copyright 2001 ARM Limited. All rights reserved.
ARM DDI 0201A
Chapter 4
Protection Unit
4.1
About the protection unit ............................................................................. 4-2
4.2
Memory regions .......................................................................................... 4-3
4.3
Overlapping regions ................................................................................... 4-6
Chapter 5
Tightly-coupled Memory Interface
5.1
ARM946E-S (Rev 1) TCM interface description ......................................... 5-2
5.2
Using CP15 control register ........................................................................ 5-3
5.3
Enabling the instruction tightly-coupled memory during soft reset ............. 5-7
5.4
DTCM Accesses ......................................................................................... 5-8
5.5
ITCM accesses ........................................................................................... 5-9
Chapter 6
Bus Interface Unit and Write Buffer
6.1
About the BIU and write buffer ................................................................... 6-2
6.2
AHB bus master interface ........................................................................... 6-3
6.3
Noncached Thumb instruction fetches ....................................................... 6-9
6.4
AHB clocking ............................................................................................ 6-10
6.5
The write buffer ......................................................................................... 6-13
Chapter 7
Coprocessor Interface
7.1
About the coprocessor interface ................................................................. 7-2
7.2
LDC/STC .................................................................................................... 7-4
7.3
MCR/MRC .................................................................................................. 7-8
7.4
Interlocked MCR ....................................................................................... 7-10
7.5
CDP .......................................................................................................... 7-12
7.6
Privileged instructions ............................................................................... 7-13
7.7
Busy-waiting and interrupts ...................................................................... 7-14
Chapter 8
Debug Support
8.1
About the debug interface .......................................................................... 8-2
8.2
Debug systems ........................................................................................... 8-4
8.3
The JTAG state machine ............................................................................ 8-7
8.4
Scan chains .............................................................................................. 8-13
8.5
Debug access to the caches .................................................................... 8-19
8.6
Debug interface signals ............................................................................ 8-21
8.7
ARM9E-S core clock domains .................................................................. 8-26
8.8
Determining the core and system state .................................................... 8-27
8.9
Overview of EmbeddedICE-RT ................................................................ 8-28
8.10
Disabling EmbeddedICE-RT .................................................................... 8-30
8.11
The debug communications channel ........................................................ 8-31
8.12
Real-time debug ....................................................................................... 8-34
Contents
ARM DDI 0201A
Copyright 2001 ARM Limited. All rights reserved.
v
Chapter 9
ETM Interface
9.1
About the ETM interface ............................................................................. 9-2
9.2
Enabling the ETM interface ......................................................................... 9-4
Chapter 10
Test Support
10.1
About the ARM946E-S (Rev 1) test methodology ..................................... 10-2
10.2
Scan insertion and ATPG ......................................................................... 10-3
10.3
BIST of memory arrays ............................................................................. 10-5
Appendix A
AC Parameters
A.1
Timing diagrams ......................................................................................... A-2
A.2
AC timing parameter definitions ................................................................ A-12
Appendix B
Signal Descriptions
B.1
Signal properties and requirements ............................................................ B-2
B.2
Clock interface signals ................................................................................ B-3
B.3
TCM interface signals ................................................................................. B-4
B.4
AHB signals ................................................................................................ B-5
B.5
Coprocessor interface signals ..................................................................... B-7
B.6
Debug signals ............................................................................................. B-9
B.7
JTAG signals ............................................................................................. B-11
B.8
Miscellaneous signals ............................................................................... B-12
B.9
ETM interface signals ............................................................................... B-13
B.10
INTEST wrapper signals ........................................................................... B-15
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