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CM6800/1

TART-

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PFC/PWM C

ONTROLLER

OMBO

2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 1

GENERAL DESCRIPTION

FEATURES

Patent Number #5,565,761, #5,747,977, #5,742,151,
#5,804,950, #5,798,635

Pin to pin compatible with ML4800 and FAN6800

Additional folded-back current limit for PWM section.

23V Bi-CMOS process

VIN OK guaranteed turn on PWM at 2.5V instead of 1.5V

Internally synchronized leading edge PFC and trailing edge
PWM in one IC

Slew rate enhanced transconductance error amplifier for
ultra-fast PFC response

Low start-up current (100

A typ.)

Low operating current (3.0mA type.)

Low total harmonic distortion, high PF

Reduces ripple current in the storage capacitor between the
PFC and PWM sections

Average current, continuous or discontinuous boost leading
edge PFC

VCC OVP Comparator, Low Power Detect Comparator

PWM configurable for current mode or voltage mode
operation

Current fed gain modulator for improved noise immunity

Brown-out control, over-voltage protection, UVLO, and soft
start, and Reference OK

The CM6800/1 is a controller for power factor corrected,
switched mode power suppliers. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully compiles with
IEC-1000-3-2 specifications. Intended as a BiCMOS
version of the industry-standard ML4824, CM6800/1
includes circuits for the implementation of leading edge,
average current, "boost" type power factor correction and a
trailing edge, pulse width modulator (PWM). Gate-driver
with 1A capabilities minimizes the need for external driver
circuits. Low power requirements improve efficiency and
reduce component costs.

An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section
also includes peak current limiting and input voltage
brownout protection. The PWM section can be operated in
current or voltage mode, at up to 250kHz, and includes an
accurate 50% duty cycle limit to prevent transformer
saturation.

The only difference between CM6800 and CM6801 is that
CM6800 includes an additional folded-back current limit for
PWM section to provide short circuit protection function.

APPLICATIONS

PIN CONFIGURATION

Desktop PC Power Supply

Internet Server Power Supply

IPC Power Supply

UPS

Battery Charger

DC Motor Power Supply

Monitor Power Supply

Telecom System Power Supply

Distributed Power

SOP-16 (S16) / PDIP-16 (P16)

Top View

IEAO

SENSE

RMS

RAMP1

RAMP2

VEAO

REF

PFC OUT

PW M OUT

GND

DC I

LIMIT

CM6800/1

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PFC/PWM C

ONTROLLER

OMBO

2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 2

PIN DESCRIPTION

Operating Voltage

Pin No.

Symbol

Description

Min. Typ. Max.

Unit

IEAO

PFC transconductance current error amplifier output

4.25

2 I

PFC gain control reference input

3 I

SENSE

Current sense input to the PFC current limit comparator

-5

0.7

4 V

RMS

Input for PFC RMS line voltage compensation

Connection point for the PWM soft start capacitor

PWM voltage feedback input

RAMP 1

(RTCT)

Oscillator timing node; timing set by RT CT

1.2

3.9

8 RAMP

(PWM RAMP)

When in current mode, this pin functions as the current sense
input; when in voltage mode, it is the PWM input from PFC
output (feed forward ramp).

0 6

9 DC

LIMIT

PWM current limit comparator input

GND Ground

PWM OUT

PWM driver output

VCC

PFC OUT

PFC driver output

VCC

13 V

Positive

supply

10 15 18 V

14 V

REF

Buffered output for the internal 7.5V reference

7.5

15 V

PFC transconductance voltage error amplifier input

2.5

16 VEAO

PFC transconductance voltage error amplifier output

0 6

CM6800/1

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PFC/PWM C

ONTROLLER

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2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 4

BLOCK DIAGRAM (CM6801)

VDC

RAMP2

GAIN

MODULATOR

DC ILIMIT

VEAO

IEAO

VCC

VREF

PFC OUT

OSCILLATOR

7.5V

REFERENCE

PWM OUT

DUTY CYCLE

LIMIT

UVLO

VFB

IAC

VRMS

ISENSE

RAMP1

GND

2.75V

2.45V

VCC

GND

-1V

0.5V

1.0V

0.3V

17.9V

2.5V

Vcc

VCC

VREF

VCC

VFB

GND

350

3.5K

GMi

GMv

VCC OVP

3.5K

PFC OVP

PFC ILIMIT

DC ILIMIT

VIN OK

MPPWM

MNPWM

MNPFC

MPPFC

SW SPST

1.5V

SW SPST

20uA

SW SPST

350

PWMOUT

TRI-FAULT

PWM

DUTY

PFCOUT

PULSE
WIDTH
MODULATOR

POWER
FACTOR
CORRECTOR

PWM

CMP

LOW POWER

DETECT

SS CMP

PFC CMP

CLK

ORDERING INFORMATION

Part Number

Temperature Range

Package

CM6800IP

-40 to 125

16-Pin PDIP (P16)

CM6800IS

-40 to 125

16-Pin Wide SOP (S16)

CM6801IP

-40 to 125

16-Pin PDIP (P16)

CM6801IS

-40 to 125

16-Pin Wide SOP (S16)

CM6800GIP*

-40 to 125

16-Pin PDIP (P16)

CM6800GIS*

-40 to 125

16-Pin Wide SOP (S16)

CM6801GIP*

-40 to 125

16-Pin PDIP (P16)

CM6801GIS*

-40 to 125

16-Pin Wide SOP (S16)

*Note:

G : Suffix for Pb Free Product

CM6800/1

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PFC/PWM C

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OMBO

2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 5

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum ratings are those values beyond which the device could be permanently damaged.

Parameter Min.

Max.

Units

20 V

IEAO

0 4.5 V

SENSE

Voltage

-5

0.7

GND 0.3

VCC + 0.3

GND 0.3

VCC + 0.3

PFC OUT
PWMOUT
Voltage on Any Other Pin

GND 0.3

VCC + 0.3

REF

Input Current

Peak PFC OUT Current, Source or Sink

Peak PWM OUT Current, Source or Sink

PFC OUT, PWM OUT Energy Per Cycle

1.5

Junction Temperature

150

Storage Temperature Range

-65

150

Operating Temperature Range

-40

125

Lead Temperature (Soldering, 10 sec)

260

Thermal Resistance (

)

Plastic DIP
Plastic SOIC

105

ELECTRICAL CHARACTERISTICS

Unless otherwise stated, these specifications apply Vcc=+15V, R

= 52.3k, C

= 470pF, T

=Operating Temperature Range (Note 1)

CM6800/1

Symbol Parameter

Test

Conditions

Min. Typ. Max.

Unit

Voltage Error Amplifier (g

)

Input Voltage Range

Transconductance

NONINV

= V

INV

, VEAO = 3.75V

mho

Feedback Reference Voltage

2.45

2.5

2.55

Input Bias Current

Note 2

-1.0

-0.05

Output High Voltage

5.8

6.0

Output Low Voltage

0.1

0.4

Sink

Current

= 3V, VEAO = 6V

-35

-20

Source

Current

= 1.5V, VEAO = 1.5V

Open Loop Gain

Power Supply Rejection Ratio

11V < V

< 16.5V

Current Error Amplifier (g

)

Input Voltage Range

-1.5

0.7

Transconductance

NONINV

= V

INV

, VEAO = 3.75V

100

mho

Input Offset Voltage

-15

Output High Voltage

4.0

4.25

Output Low Voltage

1.0

1.2

CM6800/1

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PFC/PWM C

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2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 6

ELECTRICAL CHARACTERISTICS

(Conti.)

Unless otherwise stated, these specifications apply

Vcc=+15V, R

= 52.3k, C

= 470pF, T

=Operating Temperature Range (Note 1)

CM6800/1

Symbol Parameter

Test

Conditions

Min. Typ. Max.

Unit

Sink

Current

SENSE

= +0.5V, IEAO = 4.0V

-65

-35

Source

Current

SENSE

= -0.5V, IEAO = 1.5V

Open Loop Gain

Power Supply Rejection Ratio

11V < V

< 16.5V

PFC OVP Comparator

Threshold

Voltage

2.70 2.77 2.85 V

Hysteresis

230 290 mV

Low Power Detect Comparator

Threshold

Voltage

0.2 0.3 0.4 V

VCC OVP Comparator

Threshold

Voltage

17.5 17.9 18.5 V

Hysteresis

1.40 1.5 1.65 V

Tri-Fault Detect

Fault Detect HIGH

2.65

2.75

2.85

Time to Fault Detect HIGH

FAULT DETECT LOW

=OPEN.470pF from V

to GND

Fault Detect LOW

0.4

0.5

0.6

PFC I

LIMIT

Comparator

Threshold

Voltage

-1.10

-1.00

-0.90 V

(PFC I

LIMIT

Gain Modulator

Output)

100

Delay to Output (Note 4)

Overdrive Voltage = -100mV

250

DC I

LIMIT

Comparator

Threshold

Voltage

0.95 1.0 1.05 V

Delay to Output (Note 4)

Overdrive Voltage = 100mV

250

OK Comparator

OK Threshold Voltage

2.35

2.45

2.55

Hysteresis

0.95 1.2 1.4 V

GAIN Modulator

= 100

A, V

RMS

=0, V

= 1V

0.70 0.84 0.95

= 100

A, V

RMS

= 1.1V, V

= 1V

1.80 2.00 2.20

= 150

A, V

RMS

= 1.8V, V

= 1V

0.90 1.00 1.10

Gain (Note 3)

= 300

A, V

RMS

= 3.3V, V

= 1V

0.25 0.32 0.40

Bandwidth

= 100

MHz

Output Voltage =
3.5K*(I

SENSE

-I

OFFSET

)

= 250

A, V

RMS

= 1.1V, V

= 1V

0.84 0.90 0.95 V

Oscillator

Initial

Accuracy

= 25

66 76

kHz

Voltage Stability

11V < V

< 16.5V

Temperature

Stability

2 %

Total Variation

Line, Temp

kHz

Ramp Valley to Peak Voltage

2.5

PFC Dead Time (Note 4)

600

860

CT Discharge Current

RAMP2

= 0V, V

RAMP1

= 2.5V

6.5

CM6800/1

TART-

URRENT

PFC/PWM C

ONTROLLER

OMBO

2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 7

ELECTRICAL CHARACTERISTICS

(Conti.)

Unless otherwise stated, these specifications apply

Vcc=+15V, R

= 52.3k, C

= 470pF, T

=Operating Temperature Range (Note 1)

CM6800/1

Symbol Parameter

Test

Conditions

Min. Typ. Max.

Unit

Reference

Output

Voltage

= 25, I(V

REF

) = 1mA

7.4 7.5 7.6 V

Line Regulation

11V < V

< 16.5V

0mA < I(V

REF

) < 7mA; T

= 0~70

Load Regulation

0mA < I(V

REF

) < 5mA; T

= -40~85

Temperature

Stability

0.4 %

Total Variation

Line, Load, Temp

7.35

7.65

Long Term Stability

= 125, 1000HRs

5 25

PFC

Minimum Duty Cycle

IEAO

> 4.0V

Maximum Duty Cycle

IEAO

< 1.2V

OUT

= -20mA at room temp

ohm

OUT

= -100mA at room temp

ohm

Output Low Rdson

OUT

= 10mA, V

= 9V at room temp

0.4

0.8

OUT

= 20mA at room temp

ohm

Output High Rdson

OUT

= 100mA at room temp

ohm

Rise/Fall Time (Note 4)

= 1000pF

PWM

Duty Cycle Range

0-44

0-47

0-49

OUT

= -20mA at room temp

ohm

OUT

= -100mA at room temp

ohm

Output Low Rdson

OUT

= 10mA, V

= 9V

0.4

0.8

OUT

= 20mA at room temp

ohm

Output High Rdson

OUT

= 100mA at room temp

ohm

Rise/Fall Time (Note 4)

= 1000pF

PWM Comparator Level Shift

1.5

1.7

1.9

Supply

Start-Up

Current

= 12V, C

= 0

100

150

Operating Current

14V, C

= 0

3.0

7.0

Undervoltage Lockout Threshold CM6800/1

12.74

13.26

Undervoltage Lockout Hysteresis CM6800/1 2.85 3.0 3.15 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the V

pin.

Note 3: Gain = K x 5.375V; K = (I

SENSE

OFFSET

) x [I

(VEAO 0.625)]

-1

; VEAO

MAX

= 6V

Note 4: Guaranteed by design, not 100% production test.

CM6800/1

TART-

URRENT

PFC/PWM C

ONTROLLER

OMBO

2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 9

Functional Description

The CM6800/1 consists of an average current controlled,
continuous boost Power Factor Correction (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM's line regulation. In
either mode, the PWM stage uses conventional trailing
edge duty cycle modulation, while the PFC uses leading
edge modulation. This patented leading/trailing edge
modulation technique results in a higher usable PFC error
amplifier bandwidth, and can significantly reduce the size of
the PFC DC buss capacitor.

The synchronized of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the CM6800/1 runs at the same frequency as the
PFC.

In addition to power factor correction, a number of
protection features have been built into the CM6800/1.
These include soft-start, PFC overvoltage protection, peak
current limiting, brownout protection, duty cycle limiting, and
under-voltage lockout.

Power Factor Correction

Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to the
line voltage, so the power factor is unity (one). A common
class of nonlinear load is the input of most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect, which occurs on
the input filter capacitor in these supplies, causes brief
high-amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line
voltage. Such supplies present a power factor to the line of
less than one (i.e. they cause significant current harmonics
of the power line frequency to appear at their input). If the
input current drawn by such a supply (or any other
nonlinear load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous
line voltage. The PFC section of the CM6800/1 uses a
boost-mode DC-DC converter to accomplish this. The input
to the converter is the full wave rectified AC line voltage. No
bulk filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges (at twice line
frequency) from zero volts to the peak value of the AC input
and back to zero. By forcing the boost converter to meet
two simultaneous conditions, it is possible to ensure that
the current drawn from the power line is proportional to the
input

line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC

rms

. The other

condition is that the current drawn from the line at any given
instant must be proportional to the line voltage. Establishing
a suitable voltage control loop for the converter, which in turn
drives a current error amplifier and switching output driver
satisfies the first of these requirements. The second
requirement is met by using the rectified AC line voltage to
modulate the output of the voltage control loop. Such
modulation causes the current error amplifier to command a
power stage current that varies directly with the input voltage.
In order to prevent ripple, which will necessarily appear at the
output of boost circuit (typically about 10VAC on a 385V DC
level), from introducing distortion back through the voltage
error amplifier, the bandwidth of the voltage loop is
deliberately kept low. A final refinement is to adjust the
overall gain of the PFC such to be proportional to 1/VIN2,
which linearizes the transfer function of the system as the AC
input to voltage varies.

Since the boost converter topology in the CM6800/1 PFC is
of the current-averaging type, no slope compensation is
required.

PFC Section

Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
CM6800/1. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line
voltage, and PFC output voltages. There are three inputs to
the gain modulator. These are:

1. A current representing the instantaneous input voltage

(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current via a
resistor and is then fed into the gain modulator at I

Sampling current in this way minimizes ground noise, as is
required in high power switching power conversion
environments. The gain modulator responds linearly to this
current.

2. A voltage proportional to the long-term RMS AC line

voltage, derived from the rectified line voltage after scaling
and filtering. This signal is presented to the gain modulator
at VRMS. The gain modulator's output is inversely
proportional to V

RMS

(except at unusually low values of

RMS

where special gain contouring takes over, to limit

power dissipation of the circuit components under heavy
brownout conditions). The relationship between V

RMS

and

gain is called K, and is illustrated in the Typical
Performance Characteristics.

3. The output of the voltage error amplifier, VEAO. The gain

modulator responds linearly to variations in this voltage.

CM6800/1

TART-

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PFC/PWM C

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2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 10

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the
gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC form the power line. The general for of the
output of the gain modulator is:

GAINMOD

RMS

VEAO

x 1V (1)

More exactly, the output current of the gain modulator is
given by:

I

GAINMOD

= K x (VEAO 0.625V) x I

Where K is in units of V

-1

Note that the output current of the gain modulator is limited
around 228.47

A and the maximum output voltage of the

gain modulator is limited to 228.47uA x 3.5K=0.8V. This
0.8V also will determine the maximum input power.

However, I

GAINMOD

cannot be measured directly from I

SENSE

= I

GAINMOD

-I

OFFSET

and I

OFFSET

can only be measured

when VEAO is less than 0.5V and I

GAINMOD

is 0A. Typical

OFFSET

is around 60uA.

Selecting R

for IAC pin

IAC pin is the input of the gain modulator. IAC also is a
current mirror input and it requires current input. By
selecting a proper resistor R

, it will provide a good sine

wave current derived from the line voltage and it also helps
program the maximum input power and minimum input line
voltage.

R

=Vin peak x 7.9K. For example, if the minimum line

voltage is 80VAC, the R

=80 x 1.414 x 7.9K=894Kohm.

Current Error Amplifier, IEAO
The current error amplifier's output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the inverting
input to the current error amplifier, the output current of the
gain modulator is summed with a current which results from
a negative voltage being impressed upon the I

SENSE

pin.

The negative voltage on I

SENSE

represents the sum of all

currents flowing in the PFC circuit, and is typically derived
from a current sense resistor in series with the negative
terminal of the input bridge rectifier.

In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier
is a virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC, an
increase in positive current from the gain modulator will
cause the output stage to increase its duty cycle until the
voltage on I

SENSE

is adequately negative to cancel this

increased current. Similarly, if the gain modulator's output
decreases, the output duty cycle will decrease, to achieve a
less negative voltage on the I

SENSE

pin.

Cycle-By-Cycle Current Limiter and Selecting R

The I

SENSE

pin, as well as being a part of the current feedback

loop, is a direct input to the cycle-by-cycle current limiter for
the PFC section. Should the input voltage at this pin ever be
more negative than 1V, the output of the PFC will be
disabled until the protection flip-flop is reset by the clock
pulse at the start of the next PFC power cycle.

R

is the sensing resistor of the PFC boost converter. During

the steady state, line input current x R

= I

GAINMOD

x 3.5K.

Since the maximum output voltage of the gain modulator is
I

GAINMOD

max x 3.5K= 0.8V during the steady state, R

x line

input current will be limited below 0.8V as well. Therefore, to
choose R

, we use the following equation:

=0.8V x Vinpeak/(2x Line Input power)

For example, if the minimum input voltage is 80VAC, and the
maximum input rms power is 200Watt, R

= (0.8V x 80V x

1.414)/(2 x 200) = 0.226 ohm.

PFC OVP
In the CM6800/1, PFC OVP comparator serves to protect the
power circuit from being subjected to excessive voltages if
the load should suddenly change. A resistor divider from the
high voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.75V, the PFC output driver is shut
down. The PWM section will continue to operate. The OVP
comparator has 250mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below 2.50V. The VFB
power components and the CM6800/1 are within their safe
operating voltages, but not so low as to interfere with the
boost voltage regulation loop. Also, VCC OVP can be served
as a redundant PFCOVP protection. VCC OVP threshold is
17.9V with 1.5V hysteresis.

CM6800/1

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PFC/PWM C

ONTROLLER

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2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 11

OSCILLATOR

ISENSE

RAMP1

GAIN

MODULATOR

VRMS

IAC

VFB

PFC OUT

7.5V

REFERENCE

IEAO

VCC

VEAO

VREF

0.5V

0.3V

-1V

VCC

2.5V

17.9V

VCC

GND

2.75V

MNPFC

GMi

VCC OVP

MPPFC

GMv

3.5K

PFC ILIMIT

3.5K

PFC OVP

CLK

LOW POWER

DETECT

PFC CMP

POWER
FACTOR
CORRECTOR

TRI-FAULT

Figure 1. PFC Section Block Diagram

Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the types
of compensation networks most commonly used for the
voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to V

REF

to produce a soft-start characteristic on the

PFC: as the reference voltage comes up from zero volts, it
creates a differentiated voltage on I

EAO

which prevents the

PFC from immediately demanding a full duty cycle on its
boost converter.

PFC Voltage Loop
There are two major concerns when compensating the
voltage loop error amplifier, V

EAO

; stability and transient

response. Optimizing interaction between transient
response and stability requires that the error amplifier's
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest anticipated
international power frequency). The gain vs. input voltage
of the CM6800/1's voltage error amplifier, V

EAO

has a

specially shaped non-linearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line or
load conditions will cause the input to the voltage error
amplifier (V

) to deviate from its 2.5V (nominal) value. If

this happens, the transconductance of the voltage error
amplifier will increase significantly, as shown in the Typical
Performance Characteristics. This raises the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristics.

The Voltage Loop Gain (S)

EAO

OUTDC

EAO

OUT

EAO

OUT

: Compensation Net Work for the Voltage Loop

: Transconductance of VEAO

: Average PFC Input Power

OUTDC

: PFC Boost Output Voltage; typical designed value is

380V.
C

: PFC Boost Output Capacitor

PFC Current Loop
The current amplifier, I

EAO

compensation is similar to that of

the voltage error amplifier, V

EAO

with exception of the choice

of crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage loop.
It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.

The Current Loop Gain (S)

OUTDC

SENSE

EAO

OFF

ISENSE

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Page 12

: Compensation Net Work for the Current Loop

: Transconductance of IEAO

OUTDC

: PFC Boost Output Voltage; typical designed value

is 380V and we use the worst condition to calculate the Z

: The Sensing Resistor of the Boost Converter

2.5V: The Amplitude of the PFC Leading Modulation Ramp
L: The Boost Inductor

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

SENSE

Filter, the RC filter between R

and I

SENSE

There are 2 purposes to add a filter at I

SENSE

pin:

1.) Protection: During start up or inrush current

conditions, it will have a large voltage cross Rs
which is the sensing resistor of the PFC boost
converter. It requires the I

SENSE

Filter to attenuate

the energy.

2.) To reduce L, the Boost Inductor: The I

SENSE

Filter

also can reduce the Boost Inductor value since the
I

SENSE

Filter behaves like an integrator before going

SENSE

which is the input of the current error

amplifier, IEAO.

The I

SENSE

Filter is a RC filter. The resistor value of the I

SENSE

Filter is between 100 ohm and 50 ohm because I

OFFSET

x the

resistor can generate an offset voltage of IEAO. By selecting
R

FILTER

equal to 50 ohm will keep the offset of the IEAO less

than 5mV. Usually, we design the pole of I

SENSE

Filter at

fpfc/6, one sixth of the PFC switching frequency. Therefore,
the boost inductor can be reduced 6 times without disturbing
the stability. Therefore, the capacitor of the I

SENSE

Filter,

FILTER

, will be around 283nF.

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Page 13

Oscillator (RAMP1)

The oscillator frequency is determined by the values of R

and C

, which determine the ramp and off-time of the

oscillator output clock:

OSC

DEADTIME

RAMP

The dead time of the oscillator is derived from the following
equation:

t

RAMP

= C

x R

x In

3.75

1.25

REF

at V

REF

= 7.5V:

RAMP

= C

x R

x 0.51

The dead time of the oscillator may be determined using:

t

DEADTIME

5.5mA

2.5V

x C

= 450 x C

The dead time is so small (t

RAMP

>> t

DEADTIME

) that the

operating frequency can typically be approximately by:

OSC

RAMP

EXAMPLE:
For the application circuit shown in the datasheet, with the
oscillator running at:

OSC

= 100kHz =

RAMP

Solving for C

x R

yields 1.96 x 10

-5

. Selecting standard

components values, C

= 390pF, and R

= 51.1k

The dead time of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator dead time, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken
that C

not be made so large as to extend the Maximum

Duty Cycle beyond 50%. This can be accomplished by
using a stable 390pF capacitor for C

PWM Section

Pulse Width Modulator
The PWM section of the CM6800/1 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or
voltage-mode operation. In current-mode applications, the
PWM ramp (RAMP2) is usually derived directly from a
current sensing resistor or current transformer in the
primary of the output stage, and is thereby representative

of the current flowing in the converter's output stage.
DCI

LIMIT

, which provides cycle-by-cycle current limiting, is

typically connected to RAMP2 in such applications. For
voltage-mode, operation or certain specialized applications,
RAMP2 can be connected to a separate RC timing network
to generate a voltage ramp against which V

will be

compared. Under these conditions, the use of voltage
feedforward from the PFC buss can assist in line regulation
accuracy and response. As in current mode operation, the
DC I

LIMIT

input is used for output stage overcurrent protection.

No voltage error amplifier is included in the PWM stage of
the CM6800/1, as this function is generally performed on the
output side of the PWM's isolation boundary. To facilitate the
design of optocoupler feedback circuitry, an offset has been
built into the PWM's RAMP2 input which allows V

command a zero percent duty cycle for input voltages below
1.25V.

PWM Current Limit
The DC I

LIMIT

pin is a direct input to the cycle-by-cycle current

limiter for the PWM section. Should the input voltage at this
pin ever exceed 1V, the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle. Beside, the
cycle-by-cycle current, when the DC ILIMIT triggered the
cycle-by-cycle current, it also softly discharge the voltage of
soft start capacitor. It will limit PWM duty cycle mode.
Therefore, the power dissipation will be reduced during the
dead short condition.

V

OK Comparator

The V

OK comparator monitors the DC output of the PFC

and inhibits the PWM if this voltage on V

is less than its

nominal 2.45V. Once this voltage reaches 2.45V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.

PWM Control (RAMP2)
When the PWM section is used in current mode, RAMP2 is
generally used as the sampling point for a voltage
representing the current on the primary of the PWM's output
transformer, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a
ramp voltage generated by a second set of timing
components (R

RAMP2

, C

RAMP2

),that will have a minimum value

of zero volts and should have a peak value of approximately
5V. In voltage mode operation, feedforward from the PFC
output buss is an excellent way to derive the timing ramp for
the PWM stage.

Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 20

A supplies

the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed by
the following equation:

= t

DELAY

1.25V

CM6800/1

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Page 14

where C

is the required soft start capacitance, and the

DEALY

is the desired start-up delay.

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of C

= 5ms x

1.25V

= 80nF

Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the
SS capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the V

OK comparator at

start-up. The magnitude of V

at start-up is related both to

line voltage and nominal PFC output voltage. Typically, a
1.0

F soft start capacitor will allow time for V

and PFC

out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.

Generating V

After turning on CM6800/1 at 13V, the operating voltage
can vary from 10V to 17.9V. The threshold voltage of VCC
OVP comparator is 17.9V. The hysteresis of VCC OVP is
1.5V. When VCC see 17.9V, PFCOUT will be low, and
PWM section will not be disturbed. That's the two ways to
generate VCC. One way is to use auxiliary power supply
around 15V, and the other way is to use bootstrap winding
to self-bias CM6800/1 system. The bootstrap winding can
be either taped from PFC boost choke or from the
transformer of the DC to DC stage.

The ratio of winding transformer for the bootstrap should be
set between 18V and 15V. A filter network is recommended
between VCC (pin 13) and bootstrap winding. The resistor of
the filter can be set as following.
R

FILTER

x I

VCC

~ 2V, I

VCC

= I

+ (Q

PFCFET

+ Q

PWMFET

) x fsw

= 3mA (typ.)

If anything goes wrong, and VCC goes beyond 19.4V, the
PFC gate (pin 12) drive goes low and the PWM gate drive
(pin 11) remains function. The resistor's value must be
chosen to meet the operating current requirement of the
CM6800/1 itself (5mA, max.) plus the current required by the
two gate driver outputs.

EXAMPLE:
With a wanting voltage called, V

BIAS

,of 18V, a VCC of 15V

and the CM6800/1 driving a total gate charge of 90nC at
100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET),
the gate driver current required is:

I

GATEDRIVE

= 100kHz x 90nC = 9mA

BIAS

9mA

5mA

15V

18V

Choose R

BIAS

= 214

The CM6800/1 should be locally bypassed with a 1.0

ceramic capacitor. In most applications, an electrolytic
capacitor of between 47

F and 220

F is also required

across the part, both for filtering and as part of the start-up
bootstrap circuitry.

CM6800/1

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Champion Microelectronic Corporation

Page 15

Leading/Trailing Modulation

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
on right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp
up. The effective duty cycle of the trailing edge modulation
is determined during the ON time of the switch. Figure 4
shows a typical trailing edge control scheme.

In case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When
the modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during OFF time of the switch. Figure 5 shows a leading
edge control scheme.

One of the advantages of this control technique is that it
required only one system clock. Switch 1(SW1) turns off and
switch 2 (SW2) turns on at the same instant to minimize the
momentary "no-load" period, thus lowering ripple voltage
generated by the switching action. With such synchronized
switching, the ripple voltage of the first stage is reduced.
Calculation and evaluation have shown that the 120Hz
component of the PFC's output ripple voltage can be
reduced by as much as 30% using this method.

CM6800/1

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Page 16

APPLICATION CIRCUIT (Voltage Mode)

VREF

VEAO

IEAO

VCC

PFC_DC

VFB

PFC_VIN

PFC_Vout

IVIN

PWM_Vout

PWM_DC

ISENSE

VRMS

C51

R61

470

C47

VCC

ILIMIT

VDC

VREF

R32

C31

R32A

C38

R60

C18

C44

C19

C45

C39

R33

R64

R49

R43

C40

C46

R46

R48

R45

ZD2

CM431

R66

VCC

C52

PWM_OUT

C54

C53

VCC

R44

VREF

R63

C56

C22

IVIN_EMC

C34

C15

C57

R23

IVIN

D13

MUR1100

R25
10k

R24

R22

IBOOT

IAC

C23

R27
100k

PFC_Vout

Q2N904

IL1

C43

C41

R58

C17

PWM_Rload
500m

IC10

R35

4.7

PFC_Vout

C10

C22

ILOAD

IC18

Q2N2222

IL4

IC17

R31

R29

10k

R28

PWM_IN

IBIAS

R26
18k

U2 CM6800/01/24

IAC

IEAO

I-SENSE

VCC

VREF

VFB

VEAO

VRMS

VDC

RAMP1

RAMP2 ILIMIT

GND

PWM-OUT

PFC-OUT

Q2N2222

D12

1N4148

PWM_OUT

VCC

D10

MUR1100

1N4002

C55A

R65A

R59

R17A

R18

R16A

C33

R14

R15

R12

R13

C30

D9A

MUR1100

D16

1N4148

D9B

ILIMIT

ZD1

6.8V

R10

R34

4.7

R11

C14

T 2:3

VIN

PFC_VIN

R62

C50

ISO1

R57

RT1

C49

R56

C48

VDC

100n

470p

EMC FILTER

10n

100n

10n

CM6800/1

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Champion Microelectronic Corporation

Page 17

APPLICATION CIRCUIT (Current Mode)

VREF

PWM_DC

VCC

ILIM

PFC_Vout

IEAO

IVIN

PFC_DC

VEAO

PFC_VIN

VRMS

VFB

PWM_Vout

ISENSE

C51

R61 470

C47

ILIMIT

VDC

VREF

R32

C31

R32A

C38

R60

C18

C44

C19

C45

C39

R33

R64

R49

R43

C40

C46

R46

R48

R45

ZD2

R66

CM431

VCC

C52

PWM_OUT

C54

C53

VCC

R44

VREF

R63

C56

C22

IVIN_EMC

C34

C15

C57

R23

IVIN

D13

MUR1100

R25

10k

R24

R22

IBOOT

IAC

C23

R27

100k

PFC_Vout

Q2N904

IL1

C43

C41

R58

C17

PWM_Rload
500m

IC10

R35

4.7

PFC_Vout

C10

C22

ILOAD

IC18

Q2N2222

IL4

IC17

R31

R29

10k

R28

PWM_IN

IBIAS

R26
18k

U2 CM6800/01/24

IAC

IEAO

I-SENSE

VCC

VREF

VFB

VEAO

VRMS

VDC

RAMP1

RAMP2 ILIMIT

GND

PWM-OUT

PFC-OUT

R68

Q2N2222

D12

1N4148

PWM_OUT

VCC

D10

MUR1100

1N4002

C55A

R65A

R59

R17A

R18

R16A

C33

R14

R15

R67

R12

R13

C30

D9A

MUR1100

D16

1N4148

D9B

ILIMIT

ZD1

6.8V

R10

R34

4.7

R11

C14

T 2:3

VIN

PFC_VIN

R62

C50

ISO1

R57

RT1

C49

R56

C48

VDC

10n

100n

10n

100n

470p

EMC FILTER

10n

CM6800/1

TART-

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PFC/PWM C

ONTROLLER

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2004/02/11

Rev. 1.6

Champion Microelectronic Corporation

Page 19

IMPORTANT NOTICE

Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to
discontinue any integrated circuit product or service without notice, and advises its customers to obtain
the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.

A few applications using integrated circuit products may involve potential risks of death, personal injury, or
severe property or environmental damage. CMC integrated circuit products are not designed, intended,
authorized, or warranted to be suitable for use in life-support applications, devices or systems or other
critical applications. Use of CMC products in such applications is understood to be fully at the risk of the
customer. In order to minimize risks associated with the customer's applications, the customer should
provide adequate design and operating safeguards.

HsinChu Headquarter

Sales & Marketing

5F, No. 11, Park Avenue II,
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T E L : +886-3-567 9979

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