Celeritous Technical Services Corp 800.687.6510 / 806.793.0708
3308 34th St FAX 806.793.0710
Lubbock, Texas 79410 http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

UNCTIONS

Five 16 bit programmable up/down counters

Programmable Pulse Generation

Programmable Delay Generator

Pulse Measurement

Event Counting

Frequency Measurement

System Synchronization

Real Time Clock

PPLICATIONS

Computer System Timing

Real Time Clock with Alarm
Watchdog Timer
Programmable System/Bus Clock
Wait State Generation

Data Acquisition

Programmable Converter Clock
Pulse Measurement
Frequency Counter
Event Counter

ATE

Programmable Stimulus Generator
Timing Extremes Generator

Laser Systems

Timing Sequencer
Programmable Delay Generator
External Equipment Synchronization
Burst Mode Generator

Industrial Process Control

Pulse Frequency Sensor conversion
System Timing/Synchronization

XTENDED

EATURES

Up to 20 MHz Maximum input frequency

Lower Power

TANDARD

AM9513 F

EATURES

Five independent 16 bit counters

Up/Down, Binary/BCD Counting

Internal Binary/BCD Prescaling

One Shot/Continuous Outputs

Software/External triggering

Tri-state Outputs

Programmable output polarities

Programmable gate polarities/edges

Time of Day/Alarm Functions

Programmable Internal/External Counter Source

Fully AM9513 Hardware/Software Compatible

Dual count registers on each counter

CTS9513 OVERVIEW

For two decades the most flexible counter/timer
peripheral device available was the Advanced Micro
Devices AM9513 Counter Timer. Until discontinued in
1995 the AM9513 was a leading device in industrial
and scientific timing controllers. Its only limitation was
its 7 Mhz maximum clock speed...............until
now............

Building on over two decades of successful use as
the most flexible programmable counter/timer device,
the CTS9513 breaks the old limitations of the
AM9513 in a new technology device with over 3
times the speed of the venerable `9513 with 16 bit
counters. Sporting up to a 20 MHz maximum Input
clock, the CTS9513 allows timing resolutions of 50 ns
and gate pulses as short as 50nS. This opens up a
whole new range of capabilities and applications for
this device.

The CTS9513 is an ideal solution for direct
replacement or new designs. With its CMOS
construction it consumes far less power and runs
much cooler than the original NMOS device. Due to
its ASIC construction it can not be obsoleted

The CTS9513 is Hardware and Software compatible
with the AM9513, allowing use of your present
software drivers. Standard Packaging for the
CTS9513 is the DIP-40, PLCC-44

THER

RODUCTS

Celeritous Technical Service specializes in the
creation of replacements for discontinued and
obsolete ICs. Using the latest in ASIC technology and
EDA Design Tools, Celeritous Technical can provide
rapid, high quality, cost effective form, fit and function
replacements for obsolete digital ICs. Visit us on the
web at http://www.celeritous.com for more
information on our products and services.

Figure 1 - CTS9513 DIP-40 Package

Celeritous Technical Services Corp 800.687.6510 / 806.793.0708
3308 34th St FAX 806.793.0710
Lubbock, Texas 79410 http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

DEVICE DESCRIPTION

The CTS9513 is a custom, high speed ASIC
implementation of the AMD AM9513 System Timing
Controller. The `9513 has long been the most
versatile counter/timer peripheral device, featuring far
more flexibility than competing timing devices such
as the Intel 8253/8254, Motorola 6840 or others. A
large installed base of devices and software drivers
already exists.

The principal limitation of the AM9513 was its
maximum frequency limitation of 7 Mhz imposed by
its late 1970's NMOS LSI design. The CTS9513
shatters this barrier with a 20 MHz maximum clock
speed and much lower power consumption due to its
CMOS construction.

The CTS9513 Counter/Timer is capable of a wide
variety of applications including, but not limited to:

Event Counting

Event Sequencing

Programmable pulse generation

Programmable delay generation

Frequency counting

Frequency synthesis

Real Time Clock

Alarm Clock Functions

Watchdog Timing

Retriggerable Pulse Generation

Non-Retriggerable Pulse Generation

Waveform Analysis

Interrupt Generation

Pulse burst generation

The user has control over key features such as:

Output Polarities

Output Impedance

Input Trigger, Edge Polarities

Hardware gating/triggering

Software gating/triggering

Count Up/Down

BCD/Binary Counting

Real time count register read

Internal counter concatenation (up to 80 bits)

Programmable frequency source selection

Programmable internal clock pre-scaling

FEATURES
B

ACKWARDS

OMPATIBLE

The CTS9513 maintains backwards compatibility with
most AM9513 features, allowing continued use of
your existing software drivers. Data may be
transferred in 8 or 16 bit increments. All internal data
paths in the CTS9513 are 16 bit. All `9513
commands registers and modes are supported.

ACKAGING

Figure 2 illustrates the DIP-40 Package pinout of the
device which conforms to the original AM9513
pinouts.

Table 2 summarizes the pinouts of the PLCC-44
package illustrated in Figure 3 which conform to the
original AM9513 PLCC pinouts.

IGNALS

The following signal names and description conform
to the original AM9513 device.

VCC

+5 Volt Power Supply

VSS

Ground

The CTS9513 does not provide an internal
crystal oscillator and must be driven from an
external source. X1 should be left open

X2 should be connected to an external TTL
source and pulled up to VCC

FOUT (Frequency Divider Outputs)

The FOUT line is generated by internally
programmable counters. The clock source for
these counters may be any of the external
GATE or SOURCE inputs as well as any of
the internally prescaled clock outputs.

SOURCE1-5 (Count Source Inputs)

Source inputs 1-5 provide external clock
source lines which may be routed to any of
the internal counters or the FOUT divider. The
active count edge for the source is
programmed at the counter.

Symbol

Description

Min

Max

Units

DC Supply Voltage

-0.3

Volts

Input Voltage at Any Pin

-0.3

+.3

Volts

Operating Temperature AxI

-40

Storage Temperature

-55

150

Table 1. Absolute Maximum Ratings

Celeritous Technical Services Corp 800.687.6510 / 806.793.0708
3308 34th St FAX 806.793.0710
Lubbock, Texas 79410 http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

VCC

OUT 2

OUT 1

GATE 1

X 1

X 2

FOUT

C/D

GATE 1A / D8

OUT 3

GATE 2

OUT 4

OUT 5

GATE 3

GATE 4

GATE 5

SOURCE 1

SOURCE 2

SOURCE 3

SOURCE 4

SOURCE 5

D 15

D 14

D 13

GATE 5A / D12

GATE 4A / D11

GATE 3A / D10

GATE 2A / D9

VSS

Figure 2 - CTS9513 DIP-40 Package Pinouts

Table 2 - CTS9513 Ordering Information

CTSC9513A

Package

Plastic DIP-40

Plastic PLCC-44

Temperature Range

Industrial (-40 - 85º C)

Maximum Clock Speed

20 MHz

Pin

Signal

Pin

Signal

VCC

OUT2

VSS

OUT1

D10

GATE1

D11

D12

D13

FOUT

D14

D15

C/D

SOURCE5

SOURCE4

SOURCE3

SOURCE2

SOURCE1

GATE5

GATE4

GATE3

OUT5

OUT4

GATE2

OUT3

PLCC-44 Package Pinouts

Table 2. PLCC-44 Pinouts

Figure 3. PLCC-44 Outline

GATE1-5 (Counter Gate Inputs)

Gate inputs are used to control counter
behavior. Any gate may be routed to one of
three internal counters. They may also be
used as clock or count input sources for the
internal counters or FOUT divider. The GATE
lines may be programmed for use as counter
enables, counter triggers or inhibits. Individ-
ual counters may be programmed for active
polarity as well as to be level or edge sensitive
to the GATE line.

OUT1-5 (Counter Outputs)

OUT1-5 are associated with individual
counters. Outputs are tri-state and may be
programmed by the counter for output polarity,
initialized to a given state and programmed for
pulse, square wave or complex duty cycle
waveforms.

D0-15 (Data Bus)

D0-15 form a bi-directional 16 bit data bus for
exchanging programming and status informa-
tion with a host processor, or system. These
lines act as inputs to the counter when CS
and WR are asserted and as outputs when
RD and CS are asserted. While CS is de-
asserted these lines are placed in a high
impedance state.

Celeritous Technical Services Corp 800.687.6510 / 806.793.0708
3308 34th St FAX 806.793.0710
Lubbock, Texas 79410 http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

On power-up, the data bus is configured for 8
bit transfers. The data bus may be reconfig-
ured for 16 bit by programming Master Mode
register Bit 13. If D8-15 are not used they
should be pulled up.

!CS (Chip Select Input)

The chip select line is an active low I/O control
signal used to enable the device for read and
write operations.

!WR (Write Input)

The write line is an active low I/O control
signal which is used to transfer information
from the data bus to one of the internal
command or data registers.

!RD (Read Input)

The read line is an active low I/O control
signal which is used to transfer information
from one of the internal data or command
registers to the data bus.

C/!D (Control/Data Port Select Input)

The C/D line is used in conjunction with the
CS, RD, and WR to select which internal
command or data register is being written to
or read from. The C/D line selects between
the command and data register sets as
summarized in Table 3

FUNCTIONAL DESCRIPTION
S

YSTEM

EVEL

The CTS9513 is addressed by the external system
through two address locations. Counter and com-
mand data are written to individual counters through
a sequence of indirectly addressing the internal com-
mand or data register through the command port
address, followed by a write to the data port address
which points to the indirectly addressed register
location.

Data is transferred through either two 8 bit transfers
or a single 16 bit transfer. Pointer sequencing for 8 bit
transfers is automatic and is transferred as least
significant byte first, most significant byte second.

Rapid programming of the CTS9513 may be
accomplished by use of the auto-increment feature of
the data pointer. This feature is enabled by setting
Master Mode Register bit 14 (MM14). When enabled,
the data pointer may be sequenced through a single
counter group, all counter group registers, all counter
group Hold registers only, or just the control group
registers.

NTERNAL

ONFIGURATION

Overview

A simplified block diagram of the CTS9513 is shown
in Figure 4. This diagram shows the major device
elements consisting of:

five counter groups,

internal frequency prescaler which divides
down the primary external clock source from
clock input X2,

external FOUT clock prescalers which
provide prescaled or divided outputs from a
variety of sources,

the Bus interface,

Master mode register and

the status register.

Not shown are the extended set registers, power-on
reset circuitry or internal control lines. The counter
group block diagrams are shown in Figures 5 and 6.
Counter groups 1 and 2 as shown in Figure 5 have
an additional programmable alarm register and 16 bit
comparator for implementation of time-of-day and
alarm functions.

Counter Groups

All of the counter groups have a 16 bit counter and
four programmable registers. The primary and
auxiliary counter mode register controls the count
source, gating and counting modes, input and output
polarities, binary or BCD counting and other
parameters.

Load Register

The Load register is the primary register used for
storing count-up or count-down values which may be
automatically reloaded into the counter for repetitive
counting.

Hold Register

The Hold register may be used for storing the
instantaneous count value without disturbing the
count process for reading by the host system. It may
also be used in certain count modes for storing
alternate count values and alternately counting the
load and hold register values to generate complex
waveforms.

Counter Outputs

Each of the counters has a single dedicated output
pin which is programmable for polarity, tri-state, low-Z
to ground and a variety of output modes as described
later. This flexibility allows operation in a variety of
bus and processor architectures.

Source Inputs

Each counter group may be programmed for a variety
of count sources including any of the five source
input lines, any of the internal prescaler outputs or

Celeritous Technical Services Corp 800.687.6510 / 806.793.0708
3308 34th St FAX 806.793.0710
Lubbock, Texas 79410 http://www.celeritous.com

SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE

Rev E

Tuesday, September 25,

CTS9513-2

5 Chan 16 bit 20MHz Counter/Timer

the output of the previous counter, allowing counter
concatenation and FOUT divided outputs.

Gate Inputs

Gate inputs are used for external hardware triggering
or synchronization of the counters. Each counter may
be programmed to be gated from its own gate line or
the gate lines from the previous or next counter. The
gate lines may also be programmed to be level or
edge sensitive and respond to active high or low
signals.

The gate line may be used to either initiate one or
more count sequences or used as a count enable
line, allowing the counter to count only while the gate
line is held active. Another mode allows the counter
to be reloaded from the load or hold register
depending on the state of the gate line.

PROGRAMMING
R

EGISTER

ROGRAMMING

Data Bus Operation

Table 3 summarizes the I/O control signal and data
status during bus reads and writes to the CTS9513.
The interface control logic assumes that

RD and WR are never active simultaneously

RD, WR, C/D are ignored unless CS is asserted.

Register Programming

Accessing and writing to a specific data or command
register from the data port is as follows.

Set Data Pointer

Select the appropriate data pointer value
to access the desired register (example
Counter group 1 Mode register 0x01)

Write LOAD DATA POINTER command
to primary command address (write
0x0001 to device address 0x01) to set
data pointer to Counter Group 1 Mode
register.

This points the data port to the Group 1 mode
register and set the word pointer to 1 indicating a
least significant word is expected.

RITING

EGISTERS

Write Data to Register

If the 16 bit transfer mode is selected, the
next write to the Primary Data Port
(Device Address 0x00) will write data to
the Counter mode register.

If the 8 bit transfer mode is selected, the
next write to the Primary Data Port
Address will expect the least significant
word of the register value, followed by a

write of the most significant word to the
data port. The internal word pointer is
automatically incremented.

If an automatic sequence command has
been given the data pointer will
automatically be sequenced to the next
register.

EADING

EGISTERS

Reading from a device register follows the write
sequence very closely, requiring a write to the
command register to set the appropriate data pointer,
followed by a read or reads from the data port.
Several items should be noted when reading from the
device registers:

The data pointer should always be
reloaded before reading from the data
port if the prior command was anything
but a LOAD DATA POINTER command
in order to update the Read data pre-
fetch latch.

A LOAD DATA POINTER command
should be issued to the device prior to
reading a HOLD register following a
hardware triggered SAVE of the counter
contents to the HOLD register.

COMMANDS
C

OUNTER

OMMANDS

Counter commands are divided into two main groups.
Those commands which directly affect counter
operation, often shortcuts to programming specific
register functions, and those associated with
indirectly addressing the counters' internal registers.

Counter control commands can be further subdivided
into those commands which affect individual counter
operation and those which affect the overall device
operation.

Table 4 Lists the commands associated with indirect
addressing of the counter internal registers. These
commands point the data port to the appropriate
internal register in order to read or write to them.

Table 5 Lists the commands associated with
controlling the actions of individual counters. They
are made up basically of the ARM, DISARM, LOAD,
SAVE, CLEAR, SET and STEP commands.

ARM Command

A counter must be ARMed before it can commence
counting. Once ARMed, a counter may be
programmed to begin counting immediately or to
await a hardware trigger to initiate counting.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CTS9513AJI-2

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CTS9513AJI-2